| 1 | /* |
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| 2 | * SyncLink Multiprotocol Serial Adapter Driver |
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| 3 | * |
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| 4 | * |
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| 5 | * Copyright (C) 1998-2000 by Microgate Corporation |
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| 6 | * |
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| 7 | * Redistribution of this file is permitted under |
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| 8 | * the terms of the GNU Public License (GPL) |
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| 9 | */ |
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| 10 | |
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| 11 | #ifndef _SYNCLINK_H_ |
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| 12 | #define _SYNCLINK_H_ |
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| 13 | #define SYNCLINK_H_VERSION 3.6 |
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| 14 | |
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| 15 | #include <asm/types.h> |
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| 16 | |
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| 17 | #define BOOLEAN int |
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| 18 | #define TRUE 1 |
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| 19 | #define FALSE 0 |
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| 20 | |
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| 21 | #define BIT0 0x0001 |
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| 22 | #define BIT1 0x0002 |
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| 23 | #define BIT2 0x0004 |
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| 24 | #define BIT3 0x0008 |
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| 25 | #define BIT4 0x0010 |
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| 26 | #define BIT5 0x0020 |
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| 27 | #define BIT6 0x0040 |
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| 28 | #define BIT7 0x0080 |
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| 29 | #define BIT8 0x0100 |
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| 30 | #define BIT9 0x0200 |
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| 31 | #define BIT10 0x0400 |
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| 32 | #define BIT11 0x0800 |
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| 33 | #define BIT12 0x1000 |
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| 34 | #define BIT13 0x2000 |
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| 35 | #define BIT14 0x4000 |
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| 36 | #define BIT15 0x8000 |
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| 37 | #define BIT16 0x00010000 |
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| 38 | #define BIT17 0x00020000 |
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| 39 | #define BIT18 0x00040000 |
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| 40 | #define BIT19 0x00080000 |
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| 41 | #define BIT20 0x00100000 |
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| 42 | #define BIT21 0x00200000 |
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| 43 | #define BIT22 0x00400000 |
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| 44 | #define BIT23 0x00800000 |
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| 45 | #define BIT24 0x01000000 |
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| 46 | #define BIT25 0x02000000 |
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| 47 | #define BIT26 0x04000000 |
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| 48 | #define BIT27 0x08000000 |
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| 49 | #define BIT28 0x10000000 |
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| 50 | #define BIT29 0x20000000 |
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| 51 | #define BIT30 0x40000000 |
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| 52 | #define BIT31 0x80000000 |
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| 53 | |
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| 54 | |
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| 55 | #define HDLC_MAX_FRAME_SIZE 65535 |
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| 56 | #define MAX_ASYNC_TRANSMIT 4096 |
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| 57 | #define MAX_ASYNC_BUFFER_SIZE 4096 |
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| 58 | |
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| 59 | #define ASYNC_PARITY_NONE 0 |
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| 60 | #define ASYNC_PARITY_EVEN 1 |
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| 61 | #define ASYNC_PARITY_ODD 2 |
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| 62 | #define ASYNC_PARITY_SPACE 3 |
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| 63 | |
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| 64 | #define HDLC_FLAG_UNDERRUN_ABORT7 0x0000 |
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| 65 | #define HDLC_FLAG_UNDERRUN_ABORT15 0x0001 |
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| 66 | #define HDLC_FLAG_UNDERRUN_FLAG 0x0002 |
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| 67 | #define HDLC_FLAG_UNDERRUN_CRC 0x0004 |
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| 68 | #define HDLC_FLAG_SHARE_ZERO 0x0010 |
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| 69 | #define HDLC_FLAG_AUTO_CTS 0x0020 |
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| 70 | #define HDLC_FLAG_AUTO_DCD 0x0040 |
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| 71 | #define HDLC_FLAG_AUTO_RTS 0x0080 |
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| 72 | #define HDLC_FLAG_RXC_DPLL 0x0100 |
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| 73 | #define HDLC_FLAG_RXC_BRG 0x0200 |
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| 74 | #define HDLC_FLAG_RXC_TXCPIN 0x8000 |
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| 75 | #define HDLC_FLAG_RXC_RXCPIN 0x0000 |
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| 76 | #define HDLC_FLAG_TXC_DPLL 0x0400 |
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| 77 | #define HDLC_FLAG_TXC_BRG 0x0800 |
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| 78 | #define HDLC_FLAG_TXC_TXCPIN 0x0000 |
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| 79 | #define HDLC_FLAG_TXC_RXCPIN 0x0008 |
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| 80 | #define HDLC_FLAG_DPLL_DIV8 0x1000 |
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| 81 | #define HDLC_FLAG_DPLL_DIV16 0x2000 |
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| 82 | #define HDLC_FLAG_DPLL_DIV32 0x0000 |
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| 83 | #define HDLC_FLAG_HDLC_LOOPMODE 0x4000 |
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| 84 | |
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| 85 | #define HDLC_CRC_NONE 0 |
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| 86 | #define HDLC_CRC_16_CCITT 1 |
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| 87 | #define HDLC_CRC_32_CCITT 2 |
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| 88 | #define HDLC_CRC_MASK 0x00ff |
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| 89 | #define HDLC_CRC_RETURN_EX 0x8000 |
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| 90 | |
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| 91 | #define RX_OK 0 |
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| 92 | #define RX_CRC_ERROR 1 |
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| 93 | |
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| 94 | #define HDLC_TXIDLE_FLAGS 0 |
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| 95 | #define HDLC_TXIDLE_ALT_ZEROS_ONES 1 |
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| 96 | #define HDLC_TXIDLE_ZEROS 2 |
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| 97 | #define HDLC_TXIDLE_ONES 3 |
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| 98 | #define HDLC_TXIDLE_ALT_MARK_SPACE 4 |
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| 99 | #define HDLC_TXIDLE_SPACE 5 |
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| 100 | #define HDLC_TXIDLE_MARK 6 |
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| 101 | |
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| 102 | #define HDLC_ENCODING_NRZ 0 |
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| 103 | #define HDLC_ENCODING_NRZB 1 |
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| 104 | #define HDLC_ENCODING_NRZI_MARK 2 |
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| 105 | #define HDLC_ENCODING_NRZI_SPACE 3 |
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| 106 | #define HDLC_ENCODING_NRZI HDLC_ENCODING_NRZI_SPACE |
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| 107 | #define HDLC_ENCODING_BIPHASE_MARK 4 |
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| 108 | #define HDLC_ENCODING_BIPHASE_SPACE 5 |
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| 109 | #define HDLC_ENCODING_BIPHASE_LEVEL 6 |
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| 110 | #define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7 |
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| 111 | |
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| 112 | #define HDLC_PREAMBLE_LENGTH_8BITS 0 |
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| 113 | #define HDLC_PREAMBLE_LENGTH_16BITS 1 |
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| 114 | #define HDLC_PREAMBLE_LENGTH_32BITS 2 |
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| 115 | #define HDLC_PREAMBLE_LENGTH_64BITS 3 |
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| 116 | |
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| 117 | #define HDLC_PREAMBLE_PATTERN_NONE 0 |
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| 118 | #define HDLC_PREAMBLE_PATTERN_ZEROS 1 |
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| 119 | #define HDLC_PREAMBLE_PATTERN_FLAGS 2 |
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| 120 | #define HDLC_PREAMBLE_PATTERN_10 3 |
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| 121 | #define HDLC_PREAMBLE_PATTERN_01 4 |
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| 122 | #define HDLC_PREAMBLE_PATTERN_ONES 5 |
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| 123 | |
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| 124 | #define MGSL_MODE_ASYNC 1 |
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| 125 | #define MGSL_MODE_HDLC 2 |
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| 126 | #define MGSL_MODE_RAW 6 |
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| 127 | |
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| 128 | #define MGSL_BUS_TYPE_ISA 1 |
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| 129 | #define MGSL_BUS_TYPE_EISA 2 |
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| 130 | #define MGSL_BUS_TYPE_PCI 5 |
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| 131 | |
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| 132 | #define MGSL_INTERFACE_DISABLE 0 |
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| 133 | #define MGSL_INTERFACE_RS232 1 |
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| 134 | #define MGSL_INTERFACE_V35 2 |
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| 135 | #define MGSL_INTERFACE_RS422 3 |
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| 136 | |
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| 137 | typedef struct _MGSL_PARAMS |
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| 138 | { |
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| 139 | /* Common */ |
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| 140 | |
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| 141 | unsigned long mode; /* Asynchronous or HDLC */ |
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| 142 | unsigned char loopback; /* internal loopback mode */ |
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| 143 | |
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| 144 | /* HDLC Only */ |
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| 145 | |
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| 146 | unsigned short flags; |
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| 147 | unsigned char encoding; /* NRZ, NRZI, etc. */ |
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| 148 | unsigned long clock_speed; /* external clock speed in bits per second */ |
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| 149 | unsigned char addr_filter; /* receive HDLC address filter, 0xFF = disable */ |
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| 150 | unsigned short crc_type; /* None, CRC16-CCITT, or CRC32-CCITT */ |
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| 151 | unsigned char preamble_length; |
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| 152 | unsigned char preamble; |
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| 153 | |
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| 154 | /* Async Only */ |
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| 155 | |
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| 156 | unsigned long data_rate; /* bits per second */ |
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| 157 | unsigned char data_bits; /* 7 or 8 data bits */ |
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| 158 | unsigned char stop_bits; /* 1 or 2 stop bits */ |
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| 159 | unsigned char parity; /* none, even, or odd */ |
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| 160 | |
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| 161 | } MGSL_PARAMS, *PMGSL_PARAMS; |
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| 162 | |
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| 163 | #define MICROGATE_VENDOR_ID 0x13c0 |
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| 164 | #define SYNCLINK_DEVICE_ID 0x0010 |
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| 165 | #define MGSCC_DEVICE_ID 0x0020 |
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| 166 | #define SYNCLINK_SCA_DEVICE_ID 0x0030 |
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| 167 | #define MGSL_MAX_SERIAL_NUMBER 30 |
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| 168 | |
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| 169 | /* |
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| 170 | ** device diagnostics status |
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| 171 | */ |
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| 172 | |
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| 173 | #define DiagStatus_OK 0 |
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| 174 | #define DiagStatus_AddressFailure 1 |
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| 175 | #define DiagStatus_AddressConflict 2 |
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| 176 | #define DiagStatus_IrqFailure 3 |
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| 177 | #define DiagStatus_IrqConflict 4 |
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| 178 | #define DiagStatus_DmaFailure 5 |
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| 179 | #define DiagStatus_DmaConflict 6 |
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| 180 | #define DiagStatus_PciAdapterNotFound 7 |
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| 181 | #define DiagStatus_CantAssignPciResources 8 |
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| 182 | #define DiagStatus_CantAssignPciMemAddr 9 |
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| 183 | #define DiagStatus_CantAssignPciIoAddr 10 |
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| 184 | #define DiagStatus_CantAssignPciIrq 11 |
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| 185 | #define DiagStatus_MemoryError 12 |
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| 186 | |
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| 187 | #define SerialSignal_DCD 0x01 /* Data Carrier Detect */ |
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| 188 | #define SerialSignal_TXD 0x02 /* Transmit Data */ |
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| 189 | #define SerialSignal_RI 0x04 /* Ring Indicator */ |
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| 190 | #define SerialSignal_RXD 0x08 /* Receive Data */ |
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| 191 | #define SerialSignal_CTS 0x10 /* Clear to Send */ |
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| 192 | #define SerialSignal_RTS 0x20 /* Request to Send */ |
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| 193 | #define SerialSignal_DSR 0x40 /* Data Set Ready */ |
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| 194 | #define SerialSignal_DTR 0x80 /* Data Terminal Ready */ |
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| 195 | |
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| 196 | |
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| 197 | /* |
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| 198 | * Counters of the input lines (CTS, DSR, RI, CD) interrupts |
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| 199 | */ |
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| 200 | struct mgsl_icount { |
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| 201 | __u32 cts, dsr, rng, dcd, tx, rx; |
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| 202 | __u32 frame, parity, overrun, brk; |
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| 203 | __u32 buf_overrun; |
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| 204 | __u32 txok; |
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| 205 | __u32 txunder; |
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| 206 | __u32 txabort; |
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| 207 | __u32 txtimeout; |
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| 208 | __u32 rxshort; |
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| 209 | __u32 rxlong; |
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| 210 | __u32 rxabort; |
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| 211 | __u32 rxover; |
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| 212 | __u32 rxcrc; |
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| 213 | __u32 rxok; |
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| 214 | __u32 exithunt; |
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| 215 | __u32 rxidle; |
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| 216 | }; |
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| 217 | |
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| 218 | |
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| 219 | #define DEBUG_LEVEL_DATA 1 |
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| 220 | #define DEBUG_LEVEL_ERROR 2 |
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| 221 | #define DEBUG_LEVEL_INFO 3 |
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| 222 | #define DEBUG_LEVEL_BH 4 |
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| 223 | #define DEBUG_LEVEL_ISR 5 |
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| 224 | |
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| 225 | /* |
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| 226 | ** Event bit flags for use with MgslWaitEvent |
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| 227 | */ |
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| 228 | |
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| 229 | #define MgslEvent_DsrActive 0x0001 |
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| 230 | #define MgslEvent_DsrInactive 0x0002 |
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| 231 | #define MgslEvent_Dsr 0x0003 |
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| 232 | #define MgslEvent_CtsActive 0x0004 |
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| 233 | #define MgslEvent_CtsInactive 0x0008 |
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| 234 | #define MgslEvent_Cts 0x000c |
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| 235 | #define MgslEvent_DcdActive 0x0010 |
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| 236 | #define MgslEvent_DcdInactive 0x0020 |
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| 237 | #define MgslEvent_Dcd 0x0030 |
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| 238 | #define MgslEvent_RiActive 0x0040 |
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| 239 | #define MgslEvent_RiInactive 0x0080 |
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| 240 | #define MgslEvent_Ri 0x00c0 |
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| 241 | #define MgslEvent_ExitHuntMode 0x0100 |
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| 242 | #define MgslEvent_IdleReceived 0x0200 |
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| 243 | |
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| 244 | /* Private IOCTL codes: |
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| 245 | * |
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| 246 | * MGSL_IOCSPARAMS set MGSL_PARAMS structure values |
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| 247 | * MGSL_IOCGPARAMS get current MGSL_PARAMS structure values |
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| 248 | * MGSL_IOCSTXIDLE set current transmit idle mode |
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| 249 | * MGSL_IOCGTXIDLE get current transmit idle mode |
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| 250 | * MGSL_IOCTXENABLE enable or disable transmitter |
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| 251 | * MGSL_IOCRXENABLE enable or disable receiver |
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| 252 | * MGSL_IOCTXABORT abort transmitting frame (HDLC) |
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| 253 | * MGSL_IOCGSTATS return current statistics |
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| 254 | * MGSL_IOCWAITEVENT wait for specified event to occur |
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| 255 | * MGSL_LOOPTXDONE transmit in HDLC LoopMode done |
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| 256 | * MGSL_IOCSIF set the serial interface type |
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| 257 | * MGSL_IOCGIF get the serial interface type |
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| 258 | */ |
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| 259 | #define MGSL_MAGIC_IOC 'm' |
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| 260 | #define MGSL_IOCSPARAMS _IOW(MGSL_MAGIC_IOC,0,struct _MGSL_PARAMS) |
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| 261 | #define MGSL_IOCGPARAMS _IOR(MGSL_MAGIC_IOC,1,struct _MGSL_PARAMS) |
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| 262 | #define MGSL_IOCSTXIDLE _IO(MGSL_MAGIC_IOC,2) |
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| 263 | #define MGSL_IOCGTXIDLE _IO(MGSL_MAGIC_IOC,3) |
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| 264 | #define MGSL_IOCTXENABLE _IO(MGSL_MAGIC_IOC,4) |
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| 265 | #define MGSL_IOCRXENABLE _IO(MGSL_MAGIC_IOC,5) |
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| 266 | #define MGSL_IOCTXABORT _IO(MGSL_MAGIC_IOC,6) |
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| 267 | #define MGSL_IOCGSTATS _IO(MGSL_MAGIC_IOC,7) |
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| 268 | #define MGSL_IOCWAITEVENT _IOWR(MGSL_MAGIC_IOC,8,int) |
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| 269 | #define MGSL_IOCCLRMODCOUNT _IO(MGSL_MAGIC_IOC,15) |
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| 270 | #define MGSL_IOCLOOPTXDONE _IO(MGSL_MAGIC_IOC,9) |
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| 271 | #define MGSL_IOCSIF _IO(MGSL_MAGIC_IOC,10) |
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| 272 | #define MGSL_IOCGIF _IO(MGSL_MAGIC_IOC,11) |
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| 273 | |
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| 274 | #endif /* _SYNCLINK_H_ */ |
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