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breg_mem.c

Last change on this file was 2, checked in by phkim, 11 years ago

1.phkim

revision copy newcon3sk r27

Property svn:executable set to *

File size: 52.0 KB

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1	/***************************************************************************
2	* Copyright (c) 2003-2012, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: breg_mem.c $
11	* $brcm_Revision: Hydra_Software_Devel/86 $
12	* $brcm_Date: 3/14/12 5:38p $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: R:/views/refsw_latest_97468/magnum/basemodules/reg/breg_mem.c $
19	*
20	* Hydra_Software_Devel/86 3/14/12 5:38p jtna
21	* SW7468-401: add 7468 atomic registers
22	*
23	* Hydra_Software_Devel/85 3/14/12 2:45p xhuang
24	* SW7552-220: Add RFM atom register
25	*
26	* Hydra_Software_Devel/84 3/9/12 4:48p erickson
27	* SW7231-705: add BDBG_OBJECT_ASSERT
28	*
29	* Hydra_Software_Devel/83 2/29/12 12:24p mward
30	* SW7435-7: Update atomic list for 7435
31	*
32	* Hydra_Software_Devel/82 2/23/12 4:47p jrubio
33	* SW7344-104: update atomic list for 7346
34	*
35	* Hydra_Software_Devel/81 2/13/12 4:14p randyjew
36	* SW7344-104: Update atomic register list for 7344
37	*
38	* Hydra_Software_Devel/80 2/2/12 5:14p jrubio
39	* SW7344-104: add more 7346 atomic registers
40	*
41	* Hydra_Software_Devel/79 1/26/12 11:56a katrep
42	* SW7429-1:fixed run time warning messages
43	*
44	* Hydra_Software_Devel/78 1/13/12 1:25p xhuang
45	* SW7552-191: Add one more register to atom table
46	*
47	* Hydra_Software_Devel/77 12/13/11 12:01p mward
48	* SW7125-1180: Add BCHP_SMARTCARD_PLL_SC_MACRO and
49	* BCHP_VCXO_CTL_MISC_VC0_CTRL to the atomic update list.
50	*
51	* Hydra_Software_Devel/76 11/17/11 2:42p jessem
52	* SW7425-1596: Updated atomic register check list for 7425B0.
53	*
54	* Hydra_Software_Devel/75 11/3/11 5:00p katrep
55	* SW7231-317:add atmic regs for 7231B0
56	*
57	* Hydra_Software_Devel/74 10/27/11 12:25p jessem
58	* SW7425-1097: Added CLKGEN_PM_CLOCK_216_ALIVE_SEL to check atomic
59	* register list.
60	*
61	* Hydra_Software_Devel/73 10/27/11 11:54a jessem
62	* SW7425-1097: Added CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO and
63	* CLKGEN_PM_PLL_ALIVE_SEL to check atomic register list.
64	*
65	* Hydra_Software_Devel/72 10/27/11 2:06p xhuang
66	* SW7552-9: Add 7552 power management support
67	*
68	* Hydra_Software_Devel/71 10/20/11 3:42p bselva
69	* SW7358-169: Changes added for power management support
70	*
71	* Hydra_Software_Devel/70 8/29/11 11:35a jrubio
72	* SW7346-470: add 7346 B0 support
73	*
74	* Hydra_Software_Devel/69 8/24/11 3:41p jessem
75	* SW7425-533: Added BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY and
76	* BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY to atomic register access
77	* list.
78	*
79	* Hydra_Software_Devel/68 8/16/11 3:10p jessem
80	* SW7425-1097: Added B0 support.
81	*
82	* Hydra_Software_Devel/67 8/15/11 10:26a randyjew
83	* SW7344-149: Add 7344 B0 support
84	*
85	* Hydra_Software_Devel/66 8/11/11 3:28p katrep
86	* SW7231-317:add 7231B0 support
87	*
88	* Hydra_Software_Devel/65 7/26/11 4:28p gmohile
89	* SW7425-533 : Add atomic access reg
90	*
91	* Hydra_Software_Devel/64 6/22/11 6:42p randyjew
92	* SW7344-104:Add atomic access registers for 7344/7346
93	*
94	* Hydra_Software_Devel/63 6/17/11 11:18a gmohile
95	* SWDTV-7435 : Add atomic access registers for 35233
96	*
97	* Hydra_Software_Devel/62 6/16/11 5:34p nickh
98	* SW7425-533: Add atomic access registers
99	*
100	* Hydra_Software_Devel/61 6/13/11 10:28a randyjew
101	* SW7468-6: Update Atomic update list
102	*
103	* Hydra_Software_Devel/60 6/2/11 1:55p gmohile
104	* SW7231-128 : Update atomic update list
105	*
106	* Hydra_Software_Devel/59 5/12/11 1:39p gmohile
107	* SW7231-128 : Update 7231 register list for atomic access
108	*
109	* Hydra_Software_Devel/58 4/13/11 12:09p mward
110	* SW7125-905: Add atomic access registers.
111	*
112	* Hydra_Software_Devel/57 3/14/11 10:50a randyjew
113	* SW7468-6: Update list of atomic update registers for 7468
114	*
115	* Hydra_Software_Devel/56 3/11/11 5:40p jtna
116	* SW7420-1628: add BCHP_CLK_SYS_PLL_0_PLL_3 to list
117	*
118	* Hydra_Software_Devel/55 3/2/11 4:35p gmohile
119	* SW7408-190 : Update list of atomic update registers for 7408
120	*
121	* Hydra_Software_Devel/54 2/17/11 5:20p nitinb
122	* SW7572-297: Added BCHP_CLK_MISC_CLK_SEL to atomic register list of 7550
123	*
124	* Hydra_Software_Devel/53 1/17/11 3:31p gmohile
125	* SW7408-190 : Add CLK_PM_CTRL as atomic access
126	*
127	* Hydra_Software_Devel/52 12/6/10 4:50p gmohile
128	* SW7408-190 : Add list of atomic reg for 7408
129	*
130	* Hydra_Software_Devel/51 12/2/10 4:54p gmohile
131	* SW7408-147 : Add atomic access registers for 7408
132	*
133	* Hydra_Software_Devel/50 11/24/10 2:35p nickh
134	* SW7422-12: Remove PFRI and STRIPE registers from atomic register list
135	*
136	* Hydra_Software_Devel/49 11/10/10 7:28p shyi
137	* SW35230-1755: Added atomic access registers for 35230
138	*
139	* Hydra_Software_Devel/48 11/9/10 1:35p nickh
140	* SW7422-12: add BCHP_SUN_TOP_CTRL_SW_RESET defines back in
141	*
142	* Hydra_Software_Devel/47 11/9/10 1:29p nickh
143	* SW7422-12: SW_INIT register doesn't require Atomic access
144	*
145	* Hydra_Software_Devel/46 8/24/10 8:33a erickson
146	* SW3548-815: allow BREG_Read/Write to be used inside a
147	* BREG_AtomicUpdate32 callback without warning. this avoids the need for
148	* the app to create a second method of accessing registers.
149	*
150	* Hydra_Software_Devel/45 8/17/10 6:33p nickh
151	* SW7422-12: Add support for 7422
152	*
153	* Hydra_Software_Devel/44 8/17/10 5:52p mward
154	* SW7125-237: BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6 s/b on atomic list
155	* for >= c0, not <c0.
156	*
157	* Hydra_Software_Devel/43 8/6/10 9:59a mward
158	* SW7125-237: Adding BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6 to atomic list
159	* for 7125.
160	*
161	* Hydra_Software_Devel/42 6/22/10 1:32p vanessah
162	* SW7422-12: fix the 35230 auto build error
163	*
164	* Hydra_Software_Devel/40 5/3/10 10:41a erickson
165	* SW3548-815: document BREG_AtomicUpdate32 and
166	* BREG_SetAtomicUpdate32Callback more
167	*
168	* Hydra_Software_Devel/39 4/22/10 1:56p mward
169	* SW7125-358: Add BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL to Atomic list.
170	*
171	* Hydra_Software_Devel/38 4/9/10 7:45a erickson
172	* SW7550-373: merge BREG_CAPTURE utility code to mainline. default off.
173	* add BDBG_WRN to help prevent enabling in production code. refactored
174	* to make calls less indirect.
175	*
176	* Hydra_Software_Devel/SPLASH_Devel/3 10/2/08 6:06p shyam
177	* PR41450 : Merge in latest from main to Splash Devel branch
178	*
179	* Hydra_Software_Devel/37 3/24/10 9:21p jrubio
180	* SW7342-11: 734X support
181	*
182	* Hydra_Software_Devel/36 3/2/10 10:27a mward
183	* SW7125-176: BCHP_VER_C0, not BCHP_REV_C0.
184	*
185	* Hydra_Software_Devel/35 3/1/10 5:30p mward
186	* SW7125-176: PM register changes for 7125C0.
187	*
188	* Hydra_Software_Devel/34 2/11/10 8:02p nitinb
189	* SW7550-83: Added atomic access registers for 7550
190	*
191	* Hydra_Software_Devel/33 12/22/09 1:22p nickh
192	* SW7420-70: Add more registers for atomic access
193	*
194	* Hydra_Software_Devel/33 12/22/09 1:21p nickh
195	* SW7420-70: Add more registers for atomic access
196	*
197	* Hydra_Software_Devel/32 10/27/09 9:35a jrubio
198	* SW7342-11: add support for 7342/7340 Atomic Registers
199	*
200	* Hydra_Software_Devel/31 8/27/09 8:09p mward
201	* SW7125-4: Specify atomic access registers for 7125.
202	*
203	* Hydra_Software_Devel/30 8/16/09 6:30p nickh
204	* PR47760: Use atomic access for 7420 Power management registers
205	*
206	* Hydra_Software_Devel/29 7/30/09 5:49p jrubio
207	* PR57226: add AVD into the register list for 7325
208	*
209	* Hydra_Software_Devel/28 7/30/09 2:48p jrubio
210	* PR56659: remove VCXO from 7325
211	*
212	* Hydra_Software_Devel/27 7/30/09 12:17a pntruong
213	* PR55856: Fixed 7325 build errors.
214	*
215	* Hydra_Software_Devel/26 7/29/09 2:38p jrubio
216	* PR56659: CLCK_MISC is not protected
217	*
218	* Hydra_Software_Devel/25 7/9/09 5:51p jrubio
219	* PR56659: include the necessary Registers for 7335 for AtomicUpdate
220	*
221	* Hydra_Software_Devel/24 7/8/09 4:50p jrubio
222	* PR55856: fix 7325 includes
223	*
224	* Hydra_Software_Devel/23 7/6/09 11:42a jrubio
225	* PR55856: add PM Register for 7335/7325
226	*
227	* Hydra_Software_Devel/22 7/1/09 5:18p katrep
228	* PR56528: atomic access should be used for CLK_PM_CTRL and
229	* SCXO_CTL_MISC_AVD registers
230	*
231	* Hydra_Software_Devel/21 6/9/09 1:53p mward
232	* PR55856 : Add BCHP_CLK_PM_CTRL registers to atomic reg access list.
233	*
234	* Hydra_Software_Devel/20 2/9/09 4:54p erickson
235	* PR51629: add 7336 register
236	*
237	* Hydra_Software_Devel/19 2/4/09 5:22p tdo
238	* PR51627: Add support for 7336 and 7420
239	*
240	* Hydra_Software_Devel/18 11/3/08 10:21a erickson
241	* PR48615: add BCHP_VCXO_CTL_MISC_AVD_CTRL to AtomicUpdate list, remove
242	* USB
243	*
244	* Hydra_Software_Devel/17 9/26/08 11:56a erickson
245	* PR45703: fix warning
246	*
247	* Hydra_Software_Devel/16 9/24/08 7:32p vsilyaev
248	* PR 46950: Use unified declaration of BREG handle for debug and release
249	* builds
250	*
251	* Hydra_Software_Devel/15 9/23/08 3:43p erickson
252	* PR46950: added BREG_SetAtomicUpdate32Callback
253	*
254	* Hydra_Software_Devel/14 7/30/08 4:05p vishk
255	* PR45177: uintptr_t is now defined in linux 2.6.18-5.1 header files
256	*
257	* Hydra_Software_Devel/13 6/30/08 3:28p vsilyaev
258	* PR 43119: Using atomic update functions for the 7325 platform
259	*
260	* Hydra_Software_Devel/12 6/12/08 1:00p vsilyaev
261	* PR 43119: Added AVD registers for the 3548/3556 build
262	*
263	* Hydra_Software_Devel/11 6/7/08 8:22a pntruong
264	* PR43119: Fixed build errors.
265	*
266	* Hydra_Software_Devel/10 6/5/08 5:28p vsilyaev
267	* PR43119: PR 43119: Added API for atomic register access
268	*
269	* Hydra_Software_Devel/PR43119/1 5/29/08 12:14p vsilyaev
270	* PR 43119: Added API for atomic register access
271	*
272	* Hydra_Software_Devel/9 9/14/06 2:44p jgarrett
273	* PR 23982: Removing warning in release mode
274	*
275	* Hydra_Software_Devel/8 7/21/06 11:27a vsilyaev
276	* PR 22695: Changes to make BREG_MEM compatible between debug and release
277	* builds
278	*
279	* Hydra_Software_Devel/7 9/19/03 8:55a marcusk
280	* Added volatile to typecasts to ensure compiler does not optimize
281	* register reads and writes.
282	*
283	* Hydra_Software_Devel/6 9/15/03 6:08p marcusk
284	* Updated to use void * as register base address.
285	*
286	* Hydra_Software_Devel/5 5/30/03 12:03p marcusk
287	* Changed CreateRegHandle/DestroyRegHandle to Open/Close to be more
288	* consistant.
289	*
290	* Hydra_Software_Devel/4 3/10/03 6:37p vsilyaev
291	* Integrated with bstd.h .
292	*
293	* Hydra_Software_Devel/3 3/7/03 9:24a marcusk
294	* Minor cleanup.
295	*
296	* Hydra_Software_Devel/2 3/5/03 4:19p marcusk
297	* Fixed minor issues (got it to compile).
298	*
299	* Hydra_Software_Devel/1 3/5/03 3:33p marcusk
300	* Initial version.
301	*
302	***************************************************************************/
303	#include "bstd.h"
304	#include "bkni.h"
305	#include "breg_mem.h"
306
307	BDBG_MODULE(breg_mem);
308
309	BDBG_OBJECT_ID(BREG);
310
311	void BREG_Open( BREG_Handle pRegHandle, void Address, size_t MaxRegOffset )
312	{
313	*pRegHandle = (BREG_Handle)BKNI_Malloc( sizeof(BREG_Impl) );
314	BDBG_ASSERT(*pRegHandle != NULL );
315	BDBG_OBJECT_SET(*pRegHandle, BREG);
316
317	#if BDBG_DEBUG_BUILD
318	(*pRegHandle)->MaxRegOffset = MaxRegOffset;
319	#else
320	BSTD_UNUSED(MaxRegOffset);
321	#endif
322	(*pRegHandle)->BaseAddr = (uint32_t)Address;
323	(*pRegHandle)->inAtomicUpdateCallback = false;
324
325	/* set default callback */
326	BREG_SetAtomicUpdate32Callback( *pRegHandle, NULL, NULL );
327
328	}
329
330	void BREG_Close( BREG_Handle RegHandle )
331	{
332	BDBG_OBJECT_ASSERT(RegHandle, BREG);
333	BDBG_OBJECT_DESTROY(RegHandle, BREG);
334	BKNI_Free(RegHandle);
335	}
336
337	/* compile the register access functions even for the release build */
338	#undef BREG_Write32
339	#undef BREG_Write16
340	#undef BREG_Write8
341
342	#undef BREG_Read32
343	#undef BREG_Read16
344	#undef BREG_Read8
345
346	#if BDBG_DEBUG_BUILD
347	#include "bchp_sun_top_ctrl.h"
348
349	/**
350	BREG_P_CheckAtomicRegister is a development-time debug function. It's purpose is to warn the developer that a non-atomic
351	read/modify/write is being done on a register that requires BREG_AtomicUpdate32 access. If you see a warning, you should
352	modify the code to use BREG_AtomicUpdate32 or BREG_AtomicUpdate32_isr.
353	See BREG_AtomicUpdate32 and BREG_SetAtomicUpdate32Callback in breg_mem.h for more information on atomic access.
354	**/
355	#define BREG_P_ATOMIC_REG(reg) case reg: name=#reg;regAtomic=true;break
356	static void BREG_P_CheckAtomicRegister(BREG_Handle regHandle, uint32_t reg, const char *function, bool atomic )
357	{
358	const char *name;
359	bool regAtomic;
360
361	/* the atomic update callback can turn around and use normal BREG_Read/Write calls without having any violation.
362	this allows the layer above to not invent a second way of doing register access. */
363	if (regHandle->inAtomicUpdateCallback) {
364	return;
365	}
366
367	switch(reg) {
368	#ifdef BCHP_SUN_TOP_CTRL_SW_RESET
369	BREG_P_ATOMIC_REG(BCHP_SUN_TOP_CTRL_SW_RESET);
370	#endif
371
372	#if (BCHP_CHIP==7405)
373	#include "bchp_decode_sd_0.h"
374	#include "bchp_decode_ip_shim_0.h"
375	#include "bchp_clk.h"
376	#include "bchp_vcxo_ctl_misc.h"
377	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH);
378	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH);
379	BREG_P_ATOMIC_REG(BCHP_DECODE_IP_SHIM_0_PFRI_REG);
380	BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL);
381	BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL_1);
382	BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL_2);
383	BREG_P_ATOMIC_REG(BCHP_VCXO_CTL_MISC_AVD_CTRL);
384	#elif (BCHP_CHIP==7400)
385	#include "bchp_clk.h"
386	BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL);
387	BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL_1);
388	BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL_2);
389	#elif (BCHP_CHIP==3556 \|\| BCHP_CHIP==3548)
390	#include "bchp_decode_sd_0.h"
391	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH);
392	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH);
393	#include "bchp_clkgen.h"
394	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_0);
395	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_1);
396	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_2);
397	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_3);
398	#include "bchp_vcxo_ctl_misc.h"
399	BREG_P_ATOMIC_REG(BCHP_VCXO_CTL_MISC_AVD_CTRL);
400	#elif ( BCHP_CHIP==7335 )
401	#include "bchp_clk.h"
402	#include "bchp_decode_sd_0.h"
403	#include "bchp_decode_ip_shim_0.h"
404	#include "bchp_vcxo_ctl_misc.h"
405	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH);
406	BREG_P_ATOMIC_REG(BCHP_DECODE_IP_SHIM_0_PFRI_REG);
407	BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL);
408	BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL_1);
409	BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL_2);
410	BREG_P_ATOMIC_REG(BCHP_VCXO_CTL_MISC_AVD_CTRL);
411	#elif (BCHP_CHIP==7325 )
412	#include "bchp_clkgen.h"
413	#include "bchp_decode_sd_0.h"
414	#include "bchp_decode_ip_shim_0.h"
415	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH);
416	BREG_P_ATOMIC_REG(BCHP_DECODE_IP_SHIM_0_PFRI_REG);
417	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_0);
418	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_1);
419	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_2);
420	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_3);
421	BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD_CTRL);
422	#elif (BCHP_CHIP==7340 )
423	#include "bchp_clkgen.h"
424	#include "bchp_decode_sd_0.h"
425	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH);
426	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH);
427	#if (BCHP_VER==BCHP_VER_A0)
428	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_0);
429	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_216_108_0);
430	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_216_108_1);
431	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_MISC_CLOCKS);
432	#endif
433	#elif (BCHP_CHIP==7342 )
434	#include "bchp_clk.h"
435	#include "bchp_decode_sd_0.h"
436	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH);
437	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH);
438	#elif (BCHP_CHIP==7125 )
439	#include "bchp_clkgen.h"
440	#include "bchp_decode_sd_0.h"
441	#include "bchp_decode_ip_shim_0.h"
442	#include "bchp_vcxo_ctl_misc.h"
443	#include "bchp_smartcard_pll.h"
444	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH);
445	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH);
446	BREG_P_ATOMIC_REG(BCHP_DECODE_IP_SHIM_0_PFRI_REG);
447	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL);
448	#if (BCHP_VER<BCHP_VER_C0)
449	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_0);
450	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_1);
451	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PWRDN_CTRL_2);
452	#else
453	BREG_P_ATOMIC_REG(BCHP_CLKGEN_TDAC0_CLK_PM_CTRL);
454	BREG_P_ATOMIC_REG(BCHP_CLKGEN_TDAC1_CLK_PM_CTRL);
455	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RPTD_AIO_CLK_PM_CTRL);
456	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_CLK_PM_CTRL);
457	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GFX_CLK_PM_CTRL);
458	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GFX_3D_OTP_CLK_PM_CTRL);
459	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_CLK_PM_CTRL);
460	BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD_CLK_PM_CTRL);
461	BREG_P_ATOMIC_REG(BCHP_CLKGEN_XPT_CLK_PM_CTRL);
462	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_DMA_CLK_PM_CTRL);
463	BREG_P_ATOMIC_REG(BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6);
464	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_MAIN_CH3_PM_CTRL);
465	BREG_P_ATOMIC_REG(BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1);
466	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_CLK_PM_CTRL);
467	BREG_P_ATOMIC_REG(BCHP_SMARTCARD_PLL_SC_MACRO);
468	BREG_P_ATOMIC_REG(BCHP_VCXO_CTL_MISC_VC0_CTRL);
469	#endif
470	#elif (BCHP_CHIP==7420)
471	#include "bchp_decode_sd_0.h"
472	#include "bchp_decode_sd_1.h"
473	#include "bchp_clk.h"
474	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH);
475	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH);
476	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_1_REG_SD_PFRI_DATA_WIDTH);
477	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_1_REG_SD_STRIPE_WIDTH);
478	BREG_P_ATOMIC_REG(BCHP_CLK_DVP_HT_CLK_PM_CTRL);
479	BREG_P_ATOMIC_REG(BCHP_CLK_UHFR_CLK_PM_CTRL);
480	BREG_P_ATOMIC_REG(BCHP_CLK_SUN_DAA_CLK_PM_CTRL);
481	BREG_P_ATOMIC_REG(BCHP_CLK_SUN_SM_CLK_PM_CTRL);
482	BREG_P_ATOMIC_REG(BCHP_CLK_RFM_CLK_PM_CTRL);
483	BREG_P_ATOMIC_REG(BCHP_CLK_TDAC_CLK_PM_CTRL);
484	BREG_P_ATOMIC_REG(BCHP_CLK_QDAC_CLK_PM_CTRL);
485	BREG_P_ATOMIC_REG(BCHP_CLK_RPT_AIO_CLK_PM_CTRL);
486	BREG_P_ATOMIC_REG(BCHP_CLK_VEC_656_CLK_PM_CTRL);
487	BREG_P_ATOMIC_REG(BCHP_CLK_VEC_CLK_PM_CTRL);
488	BREG_P_ATOMIC_REG(BCHP_CLK_GFX_2D_PM_CTRL);
489	BREG_P_ATOMIC_REG(BCHP_CLK_GFX_3D_PM_CTRL);
490	BREG_P_ATOMIC_REG(BCHP_CLK_BVN_EDGE_PM_CTRL);
491	BREG_P_ATOMIC_REG(BCHP_CLK_BVN_MCVP_PM_CTRL);
492	BREG_P_ATOMIC_REG(BCHP_CLK_BVN_MIDDLE_PM_CTRL);
493	BREG_P_ATOMIC_REG(BCHP_CLK_AVD0_CLK_PM_CTRL);
494	BREG_P_ATOMIC_REG(BCHP_CLK_AVD1_CLK_PM_CTRL);
495	BREG_P_ATOMIC_REG(BCHP_CLK_XPT_CLK_PM_CTRL);
496	BREG_P_ATOMIC_REG(BCHP_CLK_SECTOP_DMA_PM_CTRL);
497	BREG_P_ATOMIC_REG(BCHP_CLK_TOP1394_CLK_PM_CTRL);
498	BREG_P_ATOMIC_REG(BCHP_CLK_SYS_PLL_0_PLL_3);
499	BREG_P_ATOMIC_REG(BCHP_CLK_MISC);
500	#elif (BCHP_CHIP==7550)
501	#include "bchp_decode_sd_0.h"
502	#include "bchp_clk.h"
503	#include "bchp_avd_cache_0.h"
504	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH);
505	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH);
506	BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL);
507	BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL_1);
508	BREG_P_ATOMIC_REG(BCHP_CLK_PM_CTRL_2);
509	BREG_P_ATOMIC_REG(BCHP_CLK_MISC_CLK_SEL);
510	BREG_P_ATOMIC_REG(BCHP_AVD_CACHE_0_REG_PCACHE_MODE0);
511	#elif (BCHP_CHIP==7422)
512	#include "bchp_decode_sd_0.h"
513	#include "bchp_decode_sd_1.h"
514	/* TODO: Add other clocks */
515	#elif (BCHP_CHIP==35230)
516	#include "bchp_avd_cache_0.h"
517	BREG_P_ATOMIC_REG(BCHP_AVD_CACHE_0_REG_PCACHE_MODE0);
518	#include "bchp_decode_sd_0.h"
519	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH);
520	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH);
521	#elif ((BCHP_CHIP==35233))
522	#include "bchp_clock_gating_regs.h"
523	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_RAAGA_CLOCK_CONTROL);
524	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_DVP_HR_CLOCK_CONTROL);
525	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_PCU_CLOCK_CONTROL);
526	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_HIF_CLOCK_CONTROL);
527	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_SYS_CTRL_CLOCK_CONTROL);
528	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_USB0_CLOCK_CONTROL);
529	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_USB1_CLOCK_CONTROL);
530	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_GNET_CLOCK_CONTROL);
531	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_MCVP_FRONT_CLOCK_CONTROL);
532	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_BVN_MCDI_CLOCK_CONTROL);
533	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_CORE_XPT_CLOCK_CONTROL);
534	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_GRAPHICS_CLOCK_CONTROL);
535	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_OTP_PROD_CLOCK_CONTROL);
536	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_DS_TOP_CLOCK_CONTROL);
537	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_ADEC_CLOCK_CONTROL);
538	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_DFE_CLOCK_CONTROL);
539	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_VDEC_CLOCK_CONTROL);
540	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_X8_MASTER_CLOCK_CONTROL);
541	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_DVP_LT_CLOCK_CONTROL);
542	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_AVS_CLOCK_CONTROL);
543	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_DVP_PT_CLOCK_CONTROL);
544	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_AVD0_CLOCK_CONTROL);
545	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_VEC_CLOCK_CONTROL);
546	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_MEMSYS_CLOCK_CONTROL);
547	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_MEMSYS_1_CLOCK_CONTROL);
548	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_AVFE_CLOCK_CONTROL);
549	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_PINMUX_CLOCK_CONTROL);
550	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_AIO_CLOCK_CONTROL);
551	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_ZCPU_TOP_CLOCK_CONTROL);
552	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_V3D_CLOCK_CONTROL);
553	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_FRC_CLOCK_CONTROL);
554	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_VIDBLK_CLOCK_CONTROL);
555	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_VINDECO_CLOCK_CONTROL);
556	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_TCON_CLOCK_CONTROL);
557	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_SHARF_CLOCK_CONTROL);
558	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_BVN_EDGE_CLOCK_CONTROL);
559	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_BVN_MIDDLE_CLOCK_CONTROL);
560	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_BVN_PDP_CLOCK_CONTROL);
561	BREG_P_ATOMIC_REG(BCHP_Clock_gating_regs_THD_TOP_CLOCK_CONTROL);
562	#elif (BCHP_CHIP==7468)
563	#include "bchp_decode_sd_0.h"
564	#include "bchp_avd_rgr_0.h"
565	#include "bchp_clk.h"
566	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH);
567	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH);
568	BREG_P_ATOMIC_REG(BCHP_CLK_AVD0_CLK_PM_CTRL);
569	BREG_P_ATOMIC_REG(BCHP_CLK_BVN_TOP_CLK_PM_CTRL);
570	BREG_P_ATOMIC_REG(BCHP_CLK_RPT_AIO_CLK_PM_CTRL);
571	BREG_P_ATOMIC_REG(BCHP_CLK_VEC_CLK_PM_CTRL);
572	BREG_P_ATOMIC_REG(BCHP_CLK_QDAC_CLK_PM_CTRL);
573	BREG_P_ATOMIC_REG(BCHP_CLK_XPT_CLK_PM_CTRL);
574	BREG_P_ATOMIC_REG(BCHP_CLK_DVP_HT_CLK_PM_CTRL);
575	BREG_P_ATOMIC_REG(BCHP_CLK_SYS_PLL_1_3);
576	BREG_P_ATOMIC_REG(BCHP_CLK_SYS_PLL_1_6);
577	BREG_P_ATOMIC_REG(BCHP_CLK_SYS_PLL_0_2);
578	BREG_P_ATOMIC_REG(BCHP_CLK_M2MC_CLK_PM_CTRL);
579	BREG_P_ATOMIC_REG(BCHP_CLK_MISC);
580	BREG_P_ATOMIC_REG(BCHP_AVD_RGR_0_SW_RESET_0);
581	#elif (BCHP_CHIP==7408)
582	#include "bchp_decode_sd_0.h"
583	#include "bchp_clk.h"
584	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_PFRI_DATA_WIDTH);
585	BREG_P_ATOMIC_REG(BCHP_DECODE_SD_0_REG_SD_STRIPE_WIDTH);
586	BREG_P_ATOMIC_REG(BCHP_CLK_DVP_HT_CLK_PM_CTRL);
587	BREG_P_ATOMIC_REG(BCHP_CLK_AVD0_CLK_PM_CTRL);
588	BREG_P_ATOMIC_REG(BCHP_CLK_SYS_PLL_1_1);
589	BREG_P_ATOMIC_REG(BCHP_CLK_GFX_2D_CLK_PM_CTRL);
590	BREG_P_ATOMIC_REG(BCHP_CLK_GFX_3D_CLK_PM_CTRL);
591	BREG_P_ATOMIC_REG(BCHP_CLK_AIO_CLK_PM_CTRL);
592	BREG_P_ATOMIC_REG(BCHP_CLK_XPT_CLK_PM_CTRL);
593	BREG_P_ATOMIC_REG(BCHP_CLK_VEC_CLK_PM_CTRL);
594	BREG_P_ATOMIC_REG(BCHP_CLK_BVN_TOP_CLK_PM_CTRL);
595	BREG_P_ATOMIC_REG(BCHP_CLK_UHFR_CLK_PM_CTRL);
596	#elif (BCHP_CHIP==7231)
597	#include "bchp_clkgen.h"
598	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0);
599	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1);
600	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2);
601	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3);
602	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_PWRDN );
603	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_RESET);
604	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD0_TOP_CLOCK_ENABLE);
605	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_CLOCK_ENABLE);
606	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE);
607	BREG_P_ATOMIC_REG(BCHP_CLKGEN_ANA_QDAC40G_M7FC_CLOCK_DISABLE);
608	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE);
609	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE);
610	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE);
611	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE);
612	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE);
613	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0);
614	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1);
615	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE);
616	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_RESET);
617	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_PWRDN);
618	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET);
619	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN);
620	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET);
621	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN);
622	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE);
623	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0);
624	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1);
625	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2);
626	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_RESET);
627	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN);
628	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY);
629	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY);
630	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY);
631	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY);
632	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD0_TOP_POWER_SWITCH_MEMORY);
633	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4);
634	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_M2MC);
635	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE_V3D);
636	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_M2MC);
637	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_MEMORY_STANDBY_ENABLE_V3D);
638	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_M2MC);
639	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY_V3D);
640	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_OBSERVE_CLOCK);
641	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_CLOCK_ENABLE_M2MDMA);
642	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO);
643	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC);
644	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO);
645	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC);
646	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO);
647	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC);
648	BREG_P_ATOMIC_REG(BCHP_CLKGEN_HIF_CLOCK_ENABLE_SID);
649	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_PLL_ALIVE_SEL);
650	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL);
651	#elif (BCHP_CHIP==7429)
652	#include "bchp_clkgen.h"
653	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE);
654	#elif (BCHP_CHIP==7425)
655	#include "bchp_clkgen.h"
656	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE);
657	BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE);
658	BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY);
659	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY);
660	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE);
661	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY);
662	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0);
663	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE);
664	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE);
665	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY);
666	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET);
667	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN);
668	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET);
669	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN);
670	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET);
671	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN);
672	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1);
673	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE);
674	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY);
675	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE);
676	#if (BCHP_VER == BCHP_VER_A0 \|\| BCHP_VER == BCHP_VER_A1)
677	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_A);
678	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_ENABLE);
679	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE);
680	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_4);
681	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE);
682	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HR_INST_ENABLE);
683	#elif (BCHP_VER >= BCHP_VER_B0)
684	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO);
685	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC);
686	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC);
687	BREG_P_ATOMIC_REG(BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE);
688	BREG_P_ATOMIC_REG(BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE);
689	BREG_P_ATOMIC_REG(BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY);
690	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA);
691	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_PLL_ALIVE_SEL);
692	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL);
693	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_PLL_LDO_POWERUP);
694	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO);
695	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE);
696	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1);
697	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2);
698	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5);
699	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PAD_CLOCK_DISABLE);
700	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1);
701	#endif
702	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE);
703	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE);
704	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE);
705	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY);
706	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE);
707	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY);
708	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE);
709	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY);
710	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE);
711	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE);
712	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0);
713	BREG_P_ATOMIC_REG(BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE);
714	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2);
715	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3);
716	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0);
717	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1);
718	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN);
719	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_RESET);
720	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0);
721	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_RESET);
722	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_PWRDN);
723	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2);
724	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_RESET);
725	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN);
726	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0);
727	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2);
728	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_RESET);
729	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN);
730	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0);
731	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2);
732	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_RESET);
733	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN);
734	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_RAAGA_PLL_RESET);
735	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN);
736	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE);
737	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY);
738	#elif (BCHP_CHIP==7435)
739	#include "bchp_clkgen.h"
740	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE);
741	#if 0
742	BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE);
743	BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY);
744	#endif
745	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY);
746	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE);
747	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY);
748	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0);
749	#if 0
750	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE);
751	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE);
752	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY);
753	#endif
754	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET);
755	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN);
756	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET);
757	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN);
758	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET);
759	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN);
760	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1);
761	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE);
762	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY);
763	#if 0
764	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE);
765	#endif
766	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO);
767	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC);
768	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC);
769	BREG_P_ATOMIC_REG(BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE);
770	#if 0
771	BREG_P_ATOMIC_REG(BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE);
772	BREG_P_ATOMIC_REG(BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY);
773	#endif
774	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA);
775	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_PLL_ALIVE_SEL);
776	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL);
777	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_PLL_LDO_POWERUP);
778	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO);
779	#if 0
780	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE);
781	#endif
782	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1);
783	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2);
784	#if 0
785	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5);
786	#endif
787	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PAD_CLOCK_DISABLE);
788	#if 0
789	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1);
790	#endif
791	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE);
792	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE);
793	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE);
794	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY);
795	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE);
796	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY);
797	#if 0
798	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE);
799	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY);
800	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE);
801	#endif
802	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE);
803	#if 0
804	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0);
805	#endif
806	BREG_P_ATOMIC_REG(BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE);
807	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2);
808	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3);
809	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0);
810	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1);
811	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN);
812	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD1_PLL_RESET);
813	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0);
814	#if 0
815	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_RESET);
816	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_PWRDN);
817	#endif
818	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2);
819	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_RESET);
820	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN);
821	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0);
822	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2);
823	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_RESET);
824	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN);
825	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0);
826	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2);
827	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_RESET);
828	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN);
829	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_RAAGA_PLL_RESET);
830	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN);
831	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE);
832	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY);
833	#elif (BCHP_CHIP==7552)
834	#include "bchp_clkgen.h"
835	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN);
836	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1);
837	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2);
838	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3);
839	BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE);
840	BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY);
841	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE);
842	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE);
843	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET);
844	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN);
845	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET);
846	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN);
847	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY);
848	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_ENABLE);
849	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY);
850	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE);
851	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A);
852	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE);
853	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE);
854	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY);
855	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_ENABLE);
856	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE);
857	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY);
858	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE);
859	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE);
860	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY);
861	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE);
862	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE);
863	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0);
864	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1);
865	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0);
866	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_RESET);
867	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_PWRDN);
868	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2);
869	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_RESET);
870	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN);
871	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE);
872	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY);
873	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE);
874	#elif (BCHP_CHIP==7344)
875	#include "bchp_clkgen.h"
876	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE);
877	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE);
878	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE);
879	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET);
880	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN );
881	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET);
882	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN);
883	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE);
884	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY);
885	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE);
886	#if BCHP_VER == BCHP_VER_A0
887	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_A);
888	#else
889	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO);
890	#endif
891	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE);
892	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE);
893	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE);
894	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY);
895	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE);
896	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE);
897	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY);
898	#if BCHP_VER == BCHP_VER_A0
899	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE);
900	#else
901	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA);
902	#endif
903	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE);
904	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0);
905	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1);
906	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0);
907	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1);
908	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2);
909	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_PWRDN);
910	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_RESET);
911	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0);
912	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1);
913	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2);
914	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_RESET);
915	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN);
916	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_RESET);
917	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_PWRDN);
918	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY);
919	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL);
920	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_PLL_ALIVE_SEL);
921	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY);
922	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO);
923	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC);
924	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC);
925	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY);
926	#elif (BCHP_CHIP==7346)
927	#include "bchp_clkgen.h"
928	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE);
929	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE);
930	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE);
931	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET);
932	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN );
933	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET);
934	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN);
935	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE);
936	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY);
937	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE);
938	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE);
939	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE);
940	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY);
941	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE);
942	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE);
943	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY);
944	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE);
945	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0);
946	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1);
947	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0);
948	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1);
949	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2);
950	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_PWRDN);
951	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_PLL_RESET);
952	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0);
953	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1);
954	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2);
955	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_RESET);
956	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN);
957	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_RESET);
958	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_PWRDN);
959	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE);
960	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE);
961	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_MIPS_PLL_DIV);
962	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE);
963	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL);
964	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PM_PLL_ALIVE_SEL);
965	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA);
966	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC);
967	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC);
968	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY);
969	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO);
970	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY);
971	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY);
972	#elif (BCHP_CHIP==7358)
973	#include "bchp_clkgen.h"
974	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN);
975	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1);
976	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2);
977	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3);
978	BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE);
979	BREG_P_ATOMIC_REG(BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY);
980	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE);
981	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_CLOCK_ENABLE);
982	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET);
983	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN);
984	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET);
985	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN);
986	BREG_P_ATOMIC_REG(BCHP_CLKGEN_RAAGA_DSP_TOP_POWER_SWITCH_MEMORY);
987	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_ENABLE);
988	BREG_P_ATOMIC_REG(BCHP_CLKGEN_BVN_TOP_POWER_SWITCH_MEMORY);
989	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE);
990	BREG_P_ATOMIC_REG(BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_A);
991	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE);
992	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE);
993	BREG_P_ATOMIC_REG(BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY);
994	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_ENABLE);
995	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE);
996	BREG_P_ATOMIC_REG(BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY);
997	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_CLOCK_ENABLE);
998	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_CLOCK_DISABLE);
999	BREG_P_ATOMIC_REG(BCHP_CLKGEN_GRAPHICS_POWER_SWITCH_MEMORY);
1000	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE);
1001	BREG_P_ATOMIC_REG(BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE);
1002	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0);
1003	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1);
1004	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0);
1005	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_RESET);
1006	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_SC_PLL_PWRDN);
1007	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2);
1008	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_RESET);
1009	BREG_P_ATOMIC_REG(BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN);
1010
1011	#endif
1012	default:
1013	name = "";
1014	regAtomic = false;
1015	break;
1016	}
1017	if(regAtomic!=atomic) {
1018	if(!atomic) {
1019	BDBG_ERR(("%s: register %s(%#lx) should only be used with atomic access", function, name, (unsigned long)reg));
1020	} else {
1021	BDBG_ERR(("%s: register %#lx shouldn't be used for atomic access", function, (unsigned long)reg));
1022	}
1023	}
1024	}
1025	#else
1026	#define BREG_P_CheckAtomicRegister(regHandle, reg, function, atomic)
1027	#endif
1028
1029	uint32_t BREG_Read32(BREG_Handle RegHandle, uint32_t reg)
1030	{
1031	/* BDBG_OBJECT_ASSERT(RegHandle, BREG); */
1032	BDBG_ASSERT(reg < RegHandle->MaxRegOffset);
1033
1034	return ((volatile uint32_t )(RegHandle->BaseAddr+reg));
1035	}
1036
1037	uint16_t BREG_Read16(BREG_Handle RegHandle, uint32_t reg)
1038	{
1039	BDBG_ASSERT(reg < RegHandle->MaxRegOffset);
1040
1041	return ((volatile uint16_t )(RegHandle->BaseAddr+reg));
1042	}
1043
1044	uint8_t BREG_Read8(BREG_Handle RegHandle, uint32_t reg)
1045	{
1046	BDBG_ASSERT(reg < RegHandle->MaxRegOffset);
1047
1048	return ((volatile uint8_t )(RegHandle->BaseAddr+reg));
1049	}
1050
1051	#if BREG_CAPTURE
1052	/* BREG_CAPTURE is a hook to capture all register writes from magnum. It is used by the splashgen utility.
1053	The feature should not be enabled for a production system. */
1054	extern void APP_BREG_Write32(BREG_Handle RegHandle, uint32_t reg, uint32_t data);
1055	#endif
1056
1057	void BREG_Write32(BREG_Handle RegHandle, uint32_t reg, uint32_t data)
1058	{
1059	/* BDBG_OBJECT_ASSERT(RegHandle, BREG); */
1060	BDBG_ASSERT(reg < RegHandle->MaxRegOffset);
1061	BREG_P_CheckAtomicRegister(RegHandle, reg, "BREG_Write32", false);
1062
1063	#if BREG_CAPTURE
1064	{
1065	static int warning_count = 0;
1066	if (warning_count < 5) {
1067	warning_count++;
1068	BDBG_WRN(("You are running with BREG_CAPTURE defined. This utility mode is used for running the register capture utility, not production code."));
1069	}
1070	}
1071	APP_BREG_Write32(RegHandle, reg, data) ;
1072	#endif
1073	((volatile uint32_t )(RegHandle->BaseAddr+reg)) = data;
1074	}
1075
1076	void BREG_Write16(BREG_Handle RegHandle, uint32_t reg, uint16_t data)
1077	{
1078	BDBG_ASSERT(reg < RegHandle->MaxRegOffset);
1079	BREG_P_CheckAtomicRegister(RegHandle, reg, "BREG_Write16", false);
1080
1081	((volatile uint16_t )(RegHandle->BaseAddr+reg)) = data;
1082	}
1083
1084	void BREG_Write8(BREG_Handle RegHandle, uint32_t reg, uint8_t data)
1085	{
1086	BDBG_ASSERT(reg < RegHandle->MaxRegOffset);
1087	BREG_P_CheckAtomicRegister(RegHandle, reg, "BREG_Write8", false);
1088
1089	((volatile uint8_t )(RegHandle->BaseAddr+reg)) = data;
1090	}
1091
1092
1093	static void BREG_P_AtomicUpdate32_Impl_isr(void *context, uint32_t addr, uint32_t mask, uint32_t value)
1094	{
1095	uint32_t temp;
1096	BREG_Handle RegHandle = context;
1097	BDBG_OBJECT_ASSERT(RegHandle, BREG);
1098	addr = RegHandle->BaseAddr + addr;
1099	temp = (volatile uint32_t )addr;
1100	temp = (temp&~mask)\|value;
1101	(volatile uint32_t )addr = temp;
1102	return;
1103	}
1104
1105	void BREG_AtomicUpdate32_isr(BREG_Handle RegHandle, uint32_t reg, uint32_t mask, uint32_t value)
1106	{
1107	BDBG_OBJECT_ASSERT(RegHandle, BREG);
1108	BDBG_ASSERT(reg < RegHandle->MaxRegOffset);
1109	BREG_P_CheckAtomicRegister(RegHandle, reg, "BREG_AtomicUpdate32_isr", true);
1110	RegHandle->inAtomicUpdateCallback = true;
1111	(*RegHandle->atomicUpdate32.callback_isr)(RegHandle->atomicUpdate32.callbackContext, reg, mask, value);
1112	RegHandle->inAtomicUpdateCallback = false;
1113	#if BREG_CAPTURE
1114	APP_BREG_Write32(RegHandle,reg,BREG_Read32(RegHandle,reg));
1115	#endif
1116	}
1117
1118
1119	void BREG_AtomicUpdate32(BREG_Handle RegHandle, uint32_t reg, uint32_t mask, uint32_t value )
1120	{
1121	BDBG_OBJECT_ASSERT(RegHandle, BREG);
1122	BDBG_ASSERT(reg < RegHandle->MaxRegOffset);
1123	BREG_P_CheckAtomicRegister(RegHandle, reg, "BREG_AtomicUpdate32", true);
1124	BKNI_EnterCriticalSection();
1125	RegHandle->inAtomicUpdateCallback = true;
1126	(*RegHandle->atomicUpdate32.callback_isr)(RegHandle->atomicUpdate32.callbackContext, reg, mask, value);
1127	RegHandle->inAtomicUpdateCallback = false;
1128	#if BREG_CAPTURE
1129	APP_BREG_Write32(RegHandle,reg,BREG_Read32(RegHandle,reg));
1130	#endif
1131	BKNI_LeaveCriticalSection();
1132	}
1133
1134	static uint32_t BREG_P_CompareAndSwap32_Impl_isr(uint32_t addr, uint32_t oldValue, uint32_t newValue)
1135	{
1136	uint32_t result = (volatile uint32_t )addr;
1137	if(result == oldValue) {
1138	(volatile uint32_t )addr = newValue;
1139	}
1140	return result;
1141	}
1142
1143	uint32_t BREG_CompareAndSwap32(BREG_Handle RegHandle, uint32_t reg, uint32_t oldValue, uint32_t newValue )
1144	{
1145	uint32_t result;
1146	BDBG_ASSERT(reg < RegHandle->MaxRegOffset);
1147	BREG_P_CheckAtomicRegister(RegHandle, reg, "BREG_CompareAndSwap32", true);
1148	BKNI_EnterCriticalSection();
1149	result = BREG_P_CompareAndSwap32_Impl_isr(RegHandle->BaseAddr+reg, oldValue, newValue);
1150	BKNI_LeaveCriticalSection();
1151	return result;
1152	}
1153
1154	uint32_t BREG_CompareAndSwap32_isr(BREG_Handle RegHandle, uint32_t reg, uint32_t oldValue, uint32_t newValue )
1155	{
1156	uint32_t result;
1157	BDBG_ASSERT(reg < RegHandle->MaxRegOffset);
1158	BREG_P_CheckAtomicRegister(RegHandle, reg, "BREG_CompareAndSwap32_isr", true);
1159	result = BREG_P_CompareAndSwap32_Impl_isr(RegHandle->BaseAddr+reg, oldValue, newValue);
1160	return result;
1161	}
1162
1163	void BREG_SetAtomicUpdate32Callback( BREG_Handle RegHandle, BREG_AtomicUpdate32Callback callback_isr, void *callbackContext )
1164	{
1165	BDBG_OBJECT_ASSERT(RegHandle, BREG);
1166	BKNI_EnterCriticalSection();
1167	if (callback_isr) {
1168	RegHandle->atomicUpdate32.callback_isr = callback_isr;
1169	RegHandle->atomicUpdate32.callbackContext = callbackContext;
1170	}
1171	else {
1172	/* restore default */
1173	RegHandle->atomicUpdate32.callback_isr = BREG_P_AtomicUpdate32_Impl_isr;
1174	RegHandle->atomicUpdate32.callbackContext = RegHandle;
1175	}
1176	BKNI_LeaveCriticalSection();
1177	}
1178
1179	/* End of File */
1180
1181
1182

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source: svn/branches/kctv/newcon3bcm2_21bu/magnum/basemodules/reg/breg_mem.c

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