| 1 | /* |
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| 2 | * Carsten Langgaard, carstenl@mips.com |
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| 3 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. |
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| 4 | * |
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| 5 | * This program is free software; you can distribute it and/or modify it |
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| 6 | * under the terms of the GNU General Public License (Version 2) as |
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| 7 | * published by the Free Software Foundation. |
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| 8 | * |
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| 9 | * This program is distributed in the hope it will be useful, but WITHOUT |
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| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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| 12 | * for more details. |
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| 13 | * |
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| 14 | * You should have received a copy of the GNU General Public License along |
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| 15 | * with this program; if not, write to the Free Software Foundation, Inc., |
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| 16 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
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| 17 | * |
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| 18 | * Register definitions for Intel PIIX4 South Bridge Device. |
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| 19 | */ |
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| 20 | #ifndef __ASM_MIPS_BOARDS_PIIX4_H |
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| 21 | #define __ASM_MIPS_BOARDS_PIIX4_H |
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| 22 | |
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| 23 | /************************************************************************ |
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| 24 | * IO register offsets |
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| 25 | ************************************************************************/ |
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| 26 | #define PIIX4_ICTLR1_ICW1 0x20 |
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| 27 | #define PIIX4_ICTLR1_ICW2 0x21 |
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| 28 | #define PIIX4_ICTLR1_ICW3 0x21 |
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| 29 | #define PIIX4_ICTLR1_ICW4 0x21 |
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| 30 | #define PIIX4_ICTLR2_ICW1 0xa0 |
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| 31 | #define PIIX4_ICTLR2_ICW2 0xa1 |
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| 32 | #define PIIX4_ICTLR2_ICW3 0xa1 |
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| 33 | #define PIIX4_ICTLR2_ICW4 0xa1 |
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| 34 | #define PIIX4_ICTLR1_OCW1 0x21 |
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| 35 | #define PIIX4_ICTLR1_OCW2 0x20 |
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| 36 | #define PIIX4_ICTLR1_OCW3 0x20 |
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| 37 | #define PIIX4_ICTLR1_OCW4 0x20 |
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| 38 | #define PIIX4_ICTLR2_OCW1 0xa1 |
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| 39 | #define PIIX4_ICTLR2_OCW2 0xa0 |
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| 40 | #define PIIX4_ICTLR2_OCW3 0xa0 |
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| 41 | #define PIIX4_ICTLR2_OCW4 0xa0 |
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| 42 | |
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| 43 | |
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| 44 | /************************************************************************ |
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| 45 | * Register encodings. |
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| 46 | ************************************************************************/ |
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| 47 | #define PIIX4_OCW2_NSEOI (0x1 << 5) |
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| 48 | #define PIIX4_OCW2_SEOI (0x3 << 5) |
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| 49 | #define PIIX4_OCW2_RNSEOI (0x5 << 5) |
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| 50 | #define PIIX4_OCW2_RAEOIS (0x4 << 5) |
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| 51 | #define PIIX4_OCW2_RAEOIC (0x0 << 5) |
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| 52 | #define PIIX4_OCW2_RSEOI (0x7 << 5) |
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| 53 | #define PIIX4_OCW2_SP (0x6 << 5) |
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| 54 | #define PIIX4_OCW2_NOP (0x2 << 5) |
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| 55 | |
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| 56 | #define PIIX4_OCW2_SEL (0x0 << 3) |
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| 57 | |
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| 58 | #define PIIX4_OCW2_ILS_0 0 |
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| 59 | #define PIIX4_OCW2_ILS_1 1 |
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| 60 | #define PIIX4_OCW2_ILS_2 2 |
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| 61 | #define PIIX4_OCW2_ILS_3 3 |
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| 62 | #define PIIX4_OCW2_ILS_4 4 |
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| 63 | #define PIIX4_OCW2_ILS_5 5 |
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| 64 | #define PIIX4_OCW2_ILS_6 6 |
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| 65 | #define PIIX4_OCW2_ILS_7 7 |
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| 66 | #define PIIX4_OCW2_ILS_8 0 |
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| 67 | #define PIIX4_OCW2_ILS_9 1 |
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| 68 | #define PIIX4_OCW2_ILS_10 2 |
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| 69 | #define PIIX4_OCW2_ILS_11 3 |
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| 70 | #define PIIX4_OCW2_ILS_12 4 |
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| 71 | #define PIIX4_OCW2_ILS_13 5 |
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| 72 | #define PIIX4_OCW2_ILS_14 6 |
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| 73 | #define PIIX4_OCW2_ILS_15 7 |
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| 74 | |
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| 75 | #define PIIX4_OCW3_SEL (0x1 << 3) |
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| 76 | |
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| 77 | #define PIIX4_OCW3_IRR 0x2 |
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| 78 | #define PIIX4_OCW3_ISR 0x3 |
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| 79 | |
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| 80 | #endif /* __ASM_MIPS_BOARDS_PIIX4_H */ |
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