| 1 | /* |
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| 2 | * Author: MontaVista Software, Inc. |
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| 3 | * source@mvista.com |
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| 4 | * |
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| 5 | * Copyright 2001-2002 MontaVista Software Inc. |
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| 6 | * |
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| 7 | * This program is free software; you can redistribute it and/or modify it |
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| 8 | * under the terms of the GNU General Public License as published by the |
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| 9 | * Free Software Foundation; either version 2 of the License, or (at your |
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| 10 | * option) any later version. |
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| 11 | * |
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| 12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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| 13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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| 14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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| 15 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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| 16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, |
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| 17 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS |
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| 18 | * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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| 19 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR |
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| 20 | * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE |
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| 21 | * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 22 | * |
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| 23 | * You should have received a copy of the GNU General Public License along |
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| 24 | * with this program; if not, write to the Free Software Foundation, Inc., |
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| 25 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
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| 26 | */ |
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| 27 | #ifndef __ASM_TX4927_TX4927_H |
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| 28 | #define __ASM_TX4927_TX4927_H |
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| 29 | |
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| 30 | #include <asm/tx4927/tx4927_mips.h> |
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| 31 | |
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| 32 | /* |
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| 33 | This register naming came from the intergrate cpu/controoler name TX4927 |
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| 34 | followed by the device name from table 4.2.2 on page 4-3 and then followed |
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| 35 | by the register name from table 4.2.3 on pages 4-4 to 4-8. The manaul |
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| 36 | used is "TMPR4927BT Preliminary Rev 0.1 20.Jul.2001". |
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| 37 | */ |
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| 38 | |
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| 39 | #define TX4927_SIO_0_BASE |
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| 40 | |
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| 41 | /* TX4927 controller */ |
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| 42 | #define TX4927_BASE 0xfff1f0000 |
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| 43 | #define TX4927_BASE 0xfff1f0000 |
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| 44 | #define TX4927_LIMIT 0xfff1fffff |
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| 45 | |
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| 46 | |
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| 47 | /* TX4927 SDRAM controller (64-bit registers) */ |
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| 48 | #define TX4927_SDRAMC_BASE 0x8000 |
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| 49 | #define TX4927_SDRAMC_SDCCR0 0x8000 |
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| 50 | #define TX4927_SDRAMC_SDCCR1 0x8008 |
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| 51 | #define TX4927_SDRAMC_SDCCR2 0x8010 |
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| 52 | #define TX4927_SDRAMC_SDCCR3 0x8018 |
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| 53 | #define TX4927_SDRAMC_SDCTR 0x8040 |
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| 54 | #define TX4927_SDRAMC_SDCMD 0x8058 |
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| 55 | #define TX4927_SDRAMC_LIMIT 0x8fff |
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| 56 | |
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| 57 | |
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| 58 | /* TX4927 external bus controller (64-bit registers) */ |
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| 59 | #define TX4927_EBUSC_BASE 0x9000 |
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| 60 | #define TX4927_EBUSC_EBCCR0 0x9000 |
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| 61 | #define TX4927_EBUSC_EBCCR1 0x9008 |
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| 62 | #define TX4927_EBUSC_EBCCR2 0x9010 |
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| 63 | #define TX4927_EBUSC_EBCCR3 0x9018 |
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| 64 | #define TX4927_EBUSC_EBCCR4 0x9020 |
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| 65 | #define TX4927_EBUSC_EBCCR5 0x9028 |
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| 66 | #define TX4927_EBUSC_EBCCR6 0x9030 |
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| 67 | #define TX4927_EBUSC_EBCCR7 0x9008 |
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| 68 | #define TX4927_EBUSC_LIMIT 0x9fff |
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| 69 | |
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| 70 | |
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| 71 | /* TX4927 SDRRAM Error Check Correction (64-bit registers) */ |
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| 72 | #define TX4927_ECC_BASE 0xa000 |
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| 73 | #define TX4927_ECC_ECCCR 0xa000 |
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| 74 | #define TX4927_ECC_ECCSR 0xa008 |
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| 75 | #define TX4927_ECC_LIMIT 0xafff |
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| 76 | |
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| 77 | |
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| 78 | /* TX4927 DMA Controller (64-bit registers) */ |
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| 79 | #define TX4927_DMAC_BASE 0xb000 |
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| 80 | #define TX4927_DMAC_TBD 0xb000 |
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| 81 | #define TX4927_DMAC_LIMIT 0xbfff |
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| 82 | |
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| 83 | |
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| 84 | /* TX4927 PCI Controller (32-bit registers) */ |
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| 85 | #define TX4927_PCIC_BASE 0xd000 |
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| 86 | #define TX4927_PCIC_TBD 0xb000 |
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| 87 | #define TX4927_PCIC_LIMIT 0xdfff |
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| 88 | |
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| 89 | |
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| 90 | /* TX4927 Configuration registers (64-bit registers) */ |
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| 91 | #define TX4927_CONFIG_BASE 0xe000 |
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| 92 | #define TX4927_CONFIG_CCFG 0xe000 |
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| 93 | #define TX4927_CONFIG_CCFG_RESERVED_42_63 BM_63_42 |
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| 94 | #define TX4927_CONFIG_CCFG_WDRST BM_41_41 |
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| 95 | #define TX4927_CONFIG_CCFG_WDREXEN BM_40_40 |
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| 96 | #define TX4927_CONFIG_CCFG_BCFG BM_39_32 |
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| 97 | #define TX4927_CONFIG_CCFG_RESERVED_27_31 BM_31_27 |
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| 98 | #define TX4927_CONFIG_CCFG_GTOT BM_26_25 |
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| 99 | #define TX4927_CONFIG_CCFG_GTOT_4096 BM_26_25 |
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| 100 | #define TX4927_CONFIG_CCFG_GTOT_2048 BM_26_26 |
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| 101 | #define TX4927_CONFIG_CCFG_GTOT_1024 BM_25_25 |
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| 102 | #define TX4927_CONFIG_CCFG_GTOT_0512 (~BM_26_25) |
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| 103 | #define TX4927_CONFIG_CCFG_TINTDIS BM_24_24 |
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| 104 | #define TX4927_CONFIG_CCFG_PCI66 BM_23_23 |
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| 105 | #define TX4927_CONFIG_CCFG_PCIMODE BM_22_22 |
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| 106 | #define TX4927_CONFIG_CCFG_RESERVED_20_21 BM_21_20 |
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| 107 | #define TX4927_CONFIG_CCFG_DIVMODE BM_19_17 |
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| 108 | #define TX4927_CONFIG_CCFG_DIVMODE_2_0 BM_19_19 |
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| 109 | #define TX4927_CONFIG_CCFG_DIVMODE_3_0 (BM_19_19|BM_17_17) |
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| 110 | #define TX4927_CONFIG_CCFG_DIVMODE_4_0 BM_19_18 |
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| 111 | #define TX4927_CONFIG_CCFG_DIVMODE_2_5 BM_19_17 |
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| 112 | #define TX4927_CONFIG_CCFG_DIVMODE_8_0 (~BM_19_17) |
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| 113 | #define TX4927_CONFIG_CCFG_DIVMODE_12_0 BM_17_17 |
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| 114 | #define TX4927_CONFIG_CCFG_DIVMODE_16_0 BM_18_18 |
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| 115 | #define TX4927_CONFIG_CCFG_DIVMODE_10_0 BM_18_17 |
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| 116 | #define TX4927_CONFIG_CCFG_BEOW BM_16_16 |
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| 117 | #define TX4927_CONFIG_CCFG_WR BM_15_15 |
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| 118 | #define TX4927_CONFIG_CCFG_TOE BM_14_14 |
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| 119 | #define TX4927_CONFIG_CCFG_PCIARB BM_13_13 |
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| 120 | #define TX4927_CONFIG_CCFG_PCIDIVMODE BM_12_11 |
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| 121 | #define TX4927_CONFIG_CCFG_RESERVED_08_10 BM_10_08 |
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| 122 | #define TX4927_CONFIG_CCFG_SYSSP BM_07_06 |
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| 123 | #define TX4927_CONFIG_CCFG_RESERVED_03_05 BM_05_03 |
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| 124 | #define TX4927_CONFIG_CCFG_ENDIAN BM_02_02 |
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| 125 | #define TX4927_CONFIG_CCFG_ARMODE BM_01_01 |
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| 126 | #define TX4927_CONFIG_CCFG_ACEHOLD BM_00_00 |
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| 127 | #define TX4927_CONFIG_REVID 0xe008 |
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| 128 | #define TX4927_CONFIG_REVID_RESERVED_32_63 BM_32_63 |
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| 129 | #define TX4927_CONFIG_REVID_PCODE BM_16_31 |
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| 130 | #define TX4927_CONFIG_REVID_MJERREV BM_12_15 |
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| 131 | #define TX4927_CONFIG_REVID_MINEREV BM_08_11 |
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| 132 | #define TX4927_CONFIG_REVID_MJREV BM_04_07 |
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| 133 | #define TX4927_CONFIG_REVID_MINREV BM_00_03 |
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| 134 | #define TX4927_CONFIG_PCFG 0xe010 |
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| 135 | #define TX4927_CONFIG_PCFG_RESERVED_57_63 BM_57_63 |
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| 136 | #define TX4927_CONFIG_PCFG_DRVDATA BM_56_56 |
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| 137 | #define TX4927_CONFIG_PCFG_DRVCB BM_55_55 |
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| 138 | #define TX4927_CONFIG_PCFG_DRVDQM BM_54_54 |
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| 139 | #define TX4927_CONFIG_PCFG_DRVADDR BM_53_53 |
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| 140 | #define TX4927_CONFIG_PCFG_DRVCKE BM_52_52 |
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| 141 | #define TX4927_CONFIG_PCFG_DRVRAS BM_51_51 |
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| 142 | #define TX4927_CONFIG_PCFG_DRVCAS BM_50_50 |
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| 143 | #define TX4927_CONFIG_PCFG_DRVWE BM_49_49 |
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| 144 | #define TX4927_CONFIG_PCFG_DRVCS3 BM_48_48 |
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| 145 | #define TX4927_CONFIG_PCFG_DRVCS2 BM_47_47 |
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| 146 | #define TX4927_CONFIG_PCFG_DRVCS1 BM_46_4k |
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| 147 | #define TX4927_CONFIG_PCFG_DRVCS0 BM_45_45 |
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| 148 | #define TX4927_CONFIG_PCFG_DRVCK3 BM_44_44 |
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| 149 | #define TX4927_CONFIG_PCFG_DRVCK2 BM_43_43 |
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| 150 | #define TX4927_CONFIG_PCFG_DRVCK1 BM_42_42 |
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| 151 | #define TX4927_CONFIG_PCFG_DRVCK0 BM_41_41 |
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| 152 | #define TX4927_CONFIG_PCFG_DRVCKIN BM_40_40 |
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| 153 | #define TX4927_CONFIG_PCFG_RESERVED_33_39 BM_33_39 |
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| 154 | #define TX4927_CONFIG_PCFG_BYPASS_PLL BM_32_32 |
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| 155 | #define TX4927_CONFIG_PCFG_RESERVED_30_31 BM_30_31 |
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| 156 | #define TX4927_CONFIG_PCFG_SDCLKDLY BM_28_29 |
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| 157 | #define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_1 (~BM_28_29) |
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| 158 | #define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_2 BM_28_28 |
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| 159 | #define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_3 BM_29_29 |
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| 160 | #define TX4927_CONFIG_PCFG_SDCLKDLY_DELAY_4 BM_28_29 |
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| 161 | #define TX4927_CONFIG_PCFG_SYSCLKEN BM_27_27 |
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| 162 | #define TX4927_CONFIG_PCFG_SDCLKEN3 BM_26_26 |
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| 163 | #define TX4927_CONFIG_PCFG_SDCLKEN2 BM_25_25 |
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| 164 | #define TX4927_CONFIG_PCFG_SDCLKEN1 BM_24_24 |
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| 165 | #define TX4927_CONFIG_PCFG_SDCLKEN0 BM_23_23 |
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| 166 | #define TX4927_CONFIG_PCFG_SDCLKINEN BM_22_22 |
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| 167 | #define TX4927_CONFIG_PCFG_PCICLKEN5 BM_21_21 |
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| 168 | #define TX4927_CONFIG_PCFG_PCICLKEN4 BM_20_20 |
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| 169 | #define TX4927_CONFIG_PCFG_PCICLKEN3 BM_19_19 |
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| 170 | #define TX4927_CONFIG_PCFG_PCICLKEN2 BM_18_18 |
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| 171 | #define TX4927_CONFIG_PCFG_PCICLKEN1 BM_17_17 |
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| 172 | #define TX4927_CONFIG_PCFG_PCICLKEN0 BM_16_16 |
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| 173 | #define TX4927_CONFIG_PCFG_RESERVED_10_15 BM_10_15 |
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| 174 | #define TX4927_CONFIG_PCFG_SEL2 BM_09_09 |
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| 175 | #define TX4927_CONFIG_PCFG_SEL1 BM_08_08 |
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| 176 | #define TX4927_CONFIG_PCFG_DMASEL3 BM_06_07 |
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| 177 | #define TX4927_CONFIG_PCFG_DMASEL3_DMAREQ3 (~BM_06_07) |
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| 178 | #define TX4927_CONFIG_PCFG_DMASEL3_SIO0 BM_06_06 |
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| 179 | #define TX4927_CONFIG_PCFG_DMASEL3_ACLC3 BM_07_07 |
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| 180 | #define TX4927_CONFIG_PCFG_DMASEL3_ACLC1 BM_06_07 |
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| 181 | #define TX4927_CONFIG_PCFG_DMASEL2 BM_06_07 |
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| 182 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_DMAREQ2 (~BM_06_07) |
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| 183 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_SIO0 BM_06_06 |
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| 184 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_10 BM_07_07 |
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| 185 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_0_RESERVED_11 BM_06_07 |
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| 186 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC1 (~BM_06_07) |
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| 187 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_SIO0 BM_06_06 |
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| 188 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC2 BM_07_07 |
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| 189 | #define TX4927_CONFIG_PCFG_DMASEL2_SEL2_1_ACLC0 BM_06_07 |
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| 190 | #define TX4927_CONFIG_PCFG_DMASEL1 BM_02_03 |
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| 191 | #define TX4927_CONFIG_PCFG_DMASEL1_DMAREQ1 (~BM_02_03) |
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| 192 | #define TX4927_CONFIG_PCFG_DMASEL1_SIO1 BM_02_02 |
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| 193 | #define TX4927_CONFIG_PCFG_DMASEL1_ACLC1 BM_03_03 |
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| 194 | #define TX4927_CONFIG_PCFG_DMASEL1_ACLC3 BM_02_03 |
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| 195 | #define TX4927_CONFIG_PCFG_DMASEL0 BM_00_01 |
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| 196 | #define TX4927_CONFIG_PCFG_DMASEL0_DMAREQ0 (~BM_00_01) |
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| 197 | #define TX4927_CONFIG_PCFG_DMASEL0_SIO1 BM_00_00 |
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| 198 | #define TX4927_CONFIG_PCFG_DMASEL0_ACLC0 BM_01_01 |
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| 199 | #define TX4927_CONFIG_PCFG_DMASEL0_ACLC2 BM_00_01 |
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| 200 | #define TX4927_CONFIG_TOEA 0xe018 |
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| 201 | #define TX4927_CONFIG_TOEA_RESERVED_36_63 BM_36_63 |
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| 202 | #define TX4927_CONFIG_TOEA_TOEA BM_00_35 |
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| 203 | #define TX4927_CONFIG_CLKCTR 0xe020 |
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| 204 | #define TX4927_CONFIG_CLKCTR_RESERVED_26_63 BM_26_63 |
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| 205 | #define TX4927_CONFIG_CLKCTR_ACLCKD BM_25_25 |
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| 206 | #define TX4927_CONFIG_CLKCTR_PIOCKD BM_24_24 |
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| 207 | #define TX4927_CONFIG_CLKCTR_DMACKD BM_23_23 |
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| 208 | #define TX4927_CONFIG_CLKCTR_PCICKD BM_22_22 |
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| 209 | #define TX4927_CONFIG_CLKCTR_SET_21 BM_21_21 |
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| 210 | #define TX4927_CONFIG_CLKCTR_TM0CKD BM_20_20 |
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| 211 | #define TX4927_CONFIG_CLKCTR_TM1CKD BM_19_19 |
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| 212 | #define TX4927_CONFIG_CLKCTR_TM2CKD BM_18_18 |
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| 213 | #define TX4927_CONFIG_CLKCTR_SIO0CKD BM_17_17 |
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| 214 | #define TX4927_CONFIG_CLKCTR_SIO1CKD BM_16_16 |
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| 215 | #define TX4927_CONFIG_CLKCTR_RESERVED_10_15 BM_10_15 |
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| 216 | #define TX4927_CONFIG_CLKCTR_ACLRST BM_09_09 |
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| 217 | #define TX4927_CONFIG_CLKCTR_PIORST BM_08_08 |
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| 218 | #define TX4927_CONFIG_CLKCTR_DMARST BM_07_07 |
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| 219 | #define TX4927_CONFIG_CLKCTR_PCIRST BM_06_06 |
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| 220 | #define TX4927_CONFIG_CLKCTR_RESERVED_05_05 BM_05_05 |
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| 221 | #define TX4927_CONFIG_CLKCTR_TM0RST BM_04_04 |
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| 222 | #define TX4927_CONFIG_CLKCTR_TM1RST BM_03_03 |
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| 223 | #define TX4927_CONFIG_CLKCTR_TM2RST BM_02_02 |
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| 224 | #define TX4927_CONFIG_CLKCTR_SIO0RST BM_01_01 |
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| 225 | #define TX4927_CONFIG_CLKCTR_SIO1RST BM_00_00 |
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| 226 | #define TX4927_CONFIG_GARBC 0xe030 |
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| 227 | #define TX4927_CONFIG_GARBC_RESERVED_10_63 BM_10_63 |
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| 228 | #define TX4927_CONFIG_GARBC_SET_09 BM_09_09 |
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| 229 | #define TX4927_CONFIG_GARBC_ARBMD BM_08_08 |
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| 230 | #define TX4927_CONFIG_GARBC_RESERVED_06_07 BM_06_07 |
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| 231 | #define TX4927_CONFIG_GARBC_PRIORITY_H1 BM_04_05 |
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| 232 | #define TX4927_CONFIG_GARBC_PRIORITY_H1_PCI (~BM_04_05) |
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| 233 | #define TX4927_CONFIG_GARBC_PRIORITY_H1_PDMAC BM_04_04 |
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| 234 | #define TX4927_CONFIG_GARBC_PRIORITY_H1_DMAC BM_05_05 |
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| 235 | #define TX4927_CONFIG_GARBC_PRIORITY_H1_BAD_VALUE BM_04_05 |
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| 236 | #define TX4927_CONFIG_GARBC_PRIORITY_H2 BM_02_03 |
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| 237 | #define TX4927_CONFIG_GARBC_PRIORITY_H2_PCI (~BM_02_03) |
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| 238 | #define TX4927_CONFIG_GARBC_PRIORITY_H2_PDMAC BM_02_02 |
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| 239 | #define TX4927_CONFIG_GARBC_PRIORITY_H2_DMAC BM_03_03 |
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| 240 | #define TX4927_CONFIG_GARBC_PRIORITY_H2_BAD_VALUE BM_02_03 |
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| 241 | #define TX4927_CONFIG_GARBC_PRIORITY_H3 BM_00_01 |
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| 242 | #define TX4927_CONFIG_GARBC_PRIORITY_H3_PCI (~BM_00_01) |
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| 243 | #define TX4927_CONFIG_GARBC_PRIORITY_H3_PDMAC BM_00_00 |
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| 244 | #define TX4927_CONFIG_GARBC_PRIORITY_H3_DMAC BM_01_01 |
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| 245 | #define TX4927_CONFIG_GARBC_PRIORITY_H3_BAD_VALUE BM_00_01 |
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| 246 | #define TX4927_CONFIG_RAMP 0xe048 |
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| 247 | #define TX4927_CONFIG_RAMP_RESERVED_20_63 BM_20_63 |
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| 248 | #define TX4927_CONFIG_RAMP_RAMP BM_00_19 |
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| 249 | #define TX4927_CONFIG_LIMIT 0xefff |
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| 250 | |
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| 251 | |
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| 252 | /* TX4927 Timer 0 (32-bit registers) */ |
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| 253 | #define TX4927_TMR0_BASE 0xf000 |
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| 254 | #define TX4927_TMR0_TMTCR0 0xf004 |
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| 255 | #define TX4927_TMR0_TMTISR0 0xf008 |
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| 256 | #define TX4927_TMR0_TMCPRA0 0xf008 |
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| 257 | #define TX4927_TMR0_TMCPRB0 0xf00c |
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| 258 | #define TX4927_TMR0_TMITMR0 0xf010 |
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| 259 | #define TX4927_TMR0_TMCCDR0 0xf020 |
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| 260 | #define TX4927_TMR0_TMPGMR0 0xf030 |
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| 261 | #define TX4927_TMR0_TMTRR0 0xf0f0 |
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| 262 | #define TX4927_TMR0_LIMIT 0xf0ff |
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| 263 | |
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| 264 | |
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| 265 | /* TX4927 Timer 1 (32-bit registers) */ |
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| 266 | #define TX4927_TMR1_BASE 0xf100 |
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| 267 | #define TX4927_TMR1_TMTCR1 0xf104 |
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| 268 | #define TX4927_TMR1_TMTISR1 0xf108 |
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| 269 | #define TX4927_TMR1_TMCPRA1 0xf108 |
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| 270 | #define TX4927_TMR1_TMCPRB1 0xf10c |
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| 271 | #define TX4927_TMR1_TMITMR1 0xf110 |
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| 272 | #define TX4927_TMR1_TMCCDR1 0xf120 |
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| 273 | #define TX4927_TMR1_TMPGMR1 0xf130 |
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| 274 | #define TX4927_TMR1_TMTRR1 0xf1f0 |
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| 275 | #define TX4927_TMR1_LIMIT 0xf1ff |
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| 276 | |
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| 277 | |
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| 278 | /* TX4927 Timer 2 (32-bit registers) */ |
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| 279 | #define TX4927_TMR2_BASE 0xf200 |
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| 280 | #define TX4927_TMR2_TMTCR2 0xf104 |
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| 281 | #define TX4927_TMR2_TMTISR2 0xf208 |
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| 282 | #define TX4927_TMR2_TMCPRA2 0xf208 |
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| 283 | #define TX4927_TMR2_TMCPRB2 0xf20c |
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| 284 | #define TX4927_TMR2_TMITMR2 0xf210 |
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| 285 | #define TX4927_TMR2_TMCCDR2 0xf220 |
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| 286 | #define TX4927_TMR2_TMPGMR2 0xf230 |
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| 287 | #define TX4927_TMR2_TMTRR2 0xf2f0 |
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| 288 | #define TX4927_TMR2_LIMIT 0xf2ff |
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| 289 | |
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| 290 | |
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| 291 | /* TX4927 serial port 0 (32-bit registers) */ |
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| 292 | #define TX4927_SIO0_BASE 0xf300 |
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| 293 | #define TX4927_SIO0_SILCR0 0xf300 |
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| 294 | #define TX4927_SIO0_SILCR0_RESERVED_16_31 BM_16_31 |
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| 295 | #define TX4927_SIO0_SILCR0_RWUB BM_15_15 |
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| 296 | #define TX4927_SIO0_SILCR0_TWUB BM_14_14 |
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| 297 | #define TX4927_SIO0_SILCR0_UODE BM_13_13 |
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| 298 | #define TX4927_SIO0_SILCR0_RESERVED_07_12 BM_07_12 |
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| 299 | #define TX4927_SIO0_SILCR0_SCS BM_05_06 |
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| 300 | #define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_IC (~BM_05_06) |
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| 301 | #define TX4927_SIO0_SILCR0_SCS_IMBUSCLK_BRG BM_05_05 |
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| 302 | #define TX4927_SIO0_SILCR0_SCS_SCLK_EC BM_06_06 |
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| 303 | #define TX4927_SIO0_SILCR0_SCS_SCLK_BRG BM_05_06 |
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| 304 | #define TX4927_SIO0_SILCR0_UEPS BM_04_04 |
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| 305 | #define TX4927_SIO0_SILCR0_UPEN BM_03_03 |
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| 306 | #define TX4927_SIO0_SILCR0_USBL BM_02_02 |
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| 307 | #define TX4927_SIO0_SILCR0_UMODE BM_00_01 |
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| 308 | #define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT BM_00_01 |
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| 309 | #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT (~BM_00_01) |
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| 310 | #define TX4927_SIO0_SILCR0_UMODE_DATA_8_BIT_MC BM_01_01 |
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| 311 | #define TX4927_SIO0_SILCR0_UMODE_DATA_7_BIT_MC BM_00_01 |
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| 312 | #define TX4927_SIO0_SIDICR0 0xf304 |
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| 313 | #define TX4927_SIO0_SIDICR0_RESERVED_16_31 BM_16_31 |
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| 314 | #define TX4927_SIO0_SIDICR0_TDE BM_15_15 |
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| 315 | #define TX4927_SIO0_SIDICR0_RDE BM_14_14 |
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| 316 | #define TX4927_SIO0_SIDICR0_TIE BM_13_13 |
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| 317 | #define TX4927_SIO0_SIDICR0_RIE BM_12_12 |
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| 318 | #define TX4927_SIO0_SIDICR0_SPIE BM_11_11 |
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| 319 | #define TX4927_SIO0_SIDICR0_CTSAC BM_09_10 |
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| 320 | #define TX4927_SIO0_SIDICR0_CTSAC_NONE (~BM_09_10) |
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| 321 | #define TX4927_SIO0_SIDICR0_CTSAC_RISE BM_09_09 |
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| 322 | #define TX4927_SIO0_SIDICR0_CTSAC_FALL BM_10_10 |
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| 323 | #define TX4927_SIO0_SIDICR0_CTSAC_BOTH BM_09_10 |
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| 324 | #define TX4927_SIO0_SIDICR0_RESERVED_06_08 BM_06_08 |
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| 325 | #define TX4927_SIO0_SIDICR0_STIE BM_00_05 |
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| 326 | #define TX4927_SIO0_SIDICR0_STIE_NONE (~BM_00_05) |
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| 327 | #define TX4927_SIO0_SIDICR0_STIE_OERS BM_05_05 |
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| 328 | #define TX4927_SIO0_SIDICR0_STIE_CTSAC BM_04_04 |
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| 329 | #define TX4927_SIO0_SIDICR0_STIE_RBRKD BM_03_03 |
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| 330 | #define TX4927_SIO0_SIDICR0_STIE_TRDY BM_02_02 |
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| 331 | #define TX4927_SIO0_SIDICR0_STIE_TXALS BM_01_01 |
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| 332 | #define TX4927_SIO0_SIDICR0_STIE_UBRKD BM_00_00 |
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| 333 | #define TX4927_SIO0_SIDISR0 0xf308 |
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| 334 | #define TX4927_SIO0_SIDISR0_RESERVED_16_31 BM_16_31 |
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| 335 | #define TX4927_SIO0_SIDISR0_UBRK BM_15_15 |
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| 336 | #define TX4927_SIO0_SIDISR0_UVALID BM_14_14 |
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| 337 | #define TX4927_SIO0_SIDISR0_UFER BM_13_13 |
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| 338 | #define TX4927_SIO0_SIDISR0_UPER BM_12_12 |
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| 339 | #define TX4927_SIO0_SIDISR0_UOER BM_11_11 |
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| 340 | #define TX4927_SIO0_SIDISR0_ERI BM_10_10 |
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| 341 | #define TX4927_SIO0_SIDISR0_TOUT BM_09_09 |
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| 342 | #define TX4927_SIO0_SIDISR0_TDIS BM_08_08 |
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| 343 | #define TX4927_SIO0_SIDISR0_RDIS BM_07_07 |
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| 344 | #define TX4927_SIO0_SIDISR0_STIS BM_06_06 |
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| 345 | #define TX4927_SIO0_SIDISR0_RESERVED_05_05 BM_05_05 |
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| 346 | #define TX4927_SIO0_SIDISR0_RFDN BM_00_04 |
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| 347 | #define TX4927_SIO0_SISCISR0 0xf30c |
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| 348 | #define TX4927_SIO0_SISCISR0_RESERVED_06_31 BM_06_31 |
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| 349 | #define TX4927_SIO0_SISCISR0_OERS BM_05_05 |
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| 350 | #define TX4927_SIO0_SISCISR0_CTSS BM_04_04 |
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| 351 | #define TX4927_SIO0_SISCISR0_RBRKD BM_03_03 |
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| 352 | #define TX4927_SIO0_SISCISR0_TRDY BM_02_02 |
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| 353 | #define TX4927_SIO0_SISCISR0_TXALS BM_01_01 |
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| 354 | #define TX4927_SIO0_SISCISR0_UBRKD BM_00_00 |
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| 355 | #define TX4927_SIO0_SIFCR0 0xf310 |
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| 356 | #define TX4927_SIO0_SIFCR0_RESERVED_16_31 BM_16_31 |
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| 357 | #define TX4927_SIO0_SIFCR0_SWRST BM_16_31 |
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| 358 | #define TX4927_SIO0_SIFCR0_RESERVED_09_14 BM_09_14 |
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| 359 | #define TX4927_SIO0_SIFCR0_RDIL BM_16_31 |
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| 360 | #define TX4927_SIO0_SIFCR0_RDIL_BYTES_1 (~BM_07_08) |
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| 361 | #define TX4927_SIO0_SIFCR0_RDIL_BYTES_4 BM_07_07 |
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| 362 | #define TX4927_SIO0_SIFCR0_RDIL_BYTES_8 BM_08_08 |
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| 363 | #define TX4927_SIO0_SIFCR0_RDIL_BYTES_12 BM_07_08 |
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| 364 | #define TX4927_SIO0_SIFCR0_RESERVED_05_06 BM_05_06 |
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| 365 | #define TX4927_SIO0_SIFCR0_TDIL BM_03_04 |
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| 366 | #define TX4927_SIO0_SIFCR0_TDIL_BYTES_1 (~BM_03_04) |
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| 367 | #define TX4927_SIO0_SIFCR0_TDIL_BYTES_4 BM_03_03 |
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| 368 | #define TX4927_SIO0_SIFCR0_TDIL_BYTES_8 BM_04_04 |
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| 369 | #define TX4927_SIO0_SIFCR0_TDIL_BYTES_0 BM_03_04 |
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| 370 | #define TX4927_SIO0_SIFCR0_TFRST BM_02_02 |
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| 371 | #define TX4927_SIO0_SIFCR0_RFRST BM_01_01 |
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| 372 | #define TX4927_SIO0_SIFCR0_FRSTE BM_00_00 |
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| 373 | #define TX4927_SIO0_SIFLCR0 0xf314 |
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| 374 | #define TX4927_SIO0_SIFLCR0_RESERVED_13_31 BM_13_31 |
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| 375 | #define TX4927_SIO0_SIFLCR0_RCS BM_12_12 |
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| 376 | #define TX4927_SIO0_SIFLCR0_TES BM_11_11 |
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| 377 | #define TX4927_SIO0_SIFLCR0_RESERVED_10_10 BM_10_10 |
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| 378 | #define TX4927_SIO0_SIFLCR0_RTSSC BM_09_09 |
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| 379 | #define TX4927_SIO0_SIFLCR0_RSDE BM_08_08 |
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| 380 | #define TX4927_SIO0_SIFLCR0_TSDE BM_07_07 |
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| 381 | #define TX4927_SIO0_SIFLCR0_RESERVED_05_06 BM_05_06 |
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| 382 | #define TX4927_SIO0_SIFLCR0_RTSTL BM_01_04 |
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| 383 | #define TX4927_SIO0_SIFLCR0_TBRK BM_00_00 |
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| 384 | #define TX4927_SIO0_SIBGR0 0xf318 |
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| 385 | #define TX4927_SIO0_SIBGR0_RESERVED_10_31 BM_10_31 |
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| 386 | #define TX4927_SIO0_SIBGR0_BCLK BM_08_09 |
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| 387 | #define TX4927_SIO0_SIBGR0_BCLK_T0 (~BM_08_09) |
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| 388 | #define TX4927_SIO0_SIBGR0_BCLK_T2 BM_08_08 |
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| 389 | #define TX4927_SIO0_SIBGR0_BCLK_T4 BM_09_09 |
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| 390 | #define TX4927_SIO0_SIBGR0_BCLK_T6 BM_08_09 |
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| 391 | #define TX4927_SIO0_SIBGR0_BRD BM_00_07 |
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| 392 | #define TX4927_SIO0_SITFIF00 0xf31c |
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| 393 | #define TX4927_SIO0_SITFIF00_RESERVED_08_31 BM_08_31 |
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| 394 | #define TX4927_SIO0_SITFIF00_TXD BM_00_07 |
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| 395 | #define TX4927_SIO0_SIRFIFO0 0xf320 |
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| 396 | #define TX4927_SIO0_SIRFIFO0_RESERVED_08_31 BM_08_31 |
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| 397 | #define TX4927_SIO0_SIRFIFO0_RXD BM_00_07 |
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| 398 | #define TX4927_SIO0_SIRFIFO0 0xf320 |
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| 399 | #define TX4927_SIO0_LIMIT 0xf3ff |
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| 400 | |
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| 401 | |
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| 402 | /* TX4927 serial port 1 (32-bit registers) */ |
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| 403 | #define TX4927_SIO1_BASE 0xf400 |
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| 404 | #define TX4927_SIO1_SILCR1 0xf400 |
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| 405 | #define TX4927_SIO1_SIDICR1 0xf404 |
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| 406 | #define TX4927_SIO1_SIDISR1 0xf408 |
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| 407 | #define TX4927_SIO1_SISCISR1 0xf40c |
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| 408 | #define TX4927_SIO1_SIFCR1 0xf410 |
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| 409 | #define TX4927_SIO1_SIFLCR1 0xf414 |
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| 410 | #define TX4927_SIO1_SIBGR1 0xf418 |
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| 411 | #define TX4927_SIO1_SITFIF01 0xf41c |
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| 412 | #define TX4927_SIO1_SIRFIFO1 0xf420 |
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| 413 | #define TX4927_SIO1_LIMIT 0xf4ff |
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| 414 | |
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| 415 | |
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| 416 | /* TX4927 parallel port (32-bit registers) */ |
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| 417 | #define TX4927_PIO_BASE 0xf500 |
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| 418 | #define TX4927_PIO_PIOD0 0xf500 |
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| 419 | #define TX4927_PIO_PIODI 0xf504 |
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| 420 | #define TX4927_PIO_PIODIR 0xf508 |
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| 421 | #define TX4927_PIO_PIOOD 0xf50c |
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| 422 | #define TX4927_PIO_LIMIT 0xf50f |
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| 423 | |
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| 424 | |
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| 425 | /* TX4927 Interrupt Controller (32-bit registers) */ |
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| 426 | #define TX4927_IRC_BASE 0xf510 |
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| 427 | #define TX4927_IRC_IRFLAG0 0xf510 |
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| 428 | #define TX4927_IRC_IRFLAG1 0xf514 |
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| 429 | #define TX4927_IRC_IRPOL 0xf518 |
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| 430 | #define TX4927_IRC_IRRCNT 0xf51c |
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| 431 | #define TX4927_IRC_IRMASKINT 0xf520 |
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| 432 | #define TX4927_IRC_IRMASKEXT 0xf524 |
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| 433 | #define TX4927_IRC_IRDEN 0xf600 |
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| 434 | #define TX4927_IRC_IRDM0 0xf604 |
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| 435 | #define TX4927_IRC_IRDM1 0xf608 |
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| 436 | #define TX4927_IRC_IRLVL0 0xf610 |
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| 437 | #define TX4927_IRC_IRLVL1 0xf614 |
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| 438 | #define TX4927_IRC_IRLVL2 0xf618 |
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| 439 | #define TX4927_IRC_IRLVL3 0xf61c |
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| 440 | #define TX4927_IRC_IRLVL4 0xf620 |
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| 441 | #define TX4927_IRC_IRLVL5 0xf624 |
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| 442 | #define TX4927_IRC_IRLVL6 0xf628 |
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| 443 | #define TX4927_IRC_IRLVL7 0xf62c |
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| 444 | #define TX4927_IRC_IRMSK 0xf640 |
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| 445 | #define TX4927_IRC_IREDC 0xf660 |
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| 446 | #define TX4927_IRC_IRPND 0xf680 |
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| 447 | #define TX4927_IRC_IRCS 0xf6a0 |
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| 448 | #define TX4927_IRC_LIMIT 0xf6ff |
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| 449 | |
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| 450 | |
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| 451 | /* TX4927 AC-link controller (32-bit registers) */ |
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| 452 | #define TX4927_ACLC_BASE 0xf700 |
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| 453 | #define TX4927_ACLC_ACCTLEN 0xf700 |
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| 454 | #define TX4927_ACLC_ACCTLDIS 0xf704 |
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| 455 | #define TX4927_ACLC_ACREGACC 0xf708 |
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| 456 | #define TX4927_ACLC_ACINTSTS 0xf710 |
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| 457 | #define TX4927_ACLC_ACINTMSTS 0xf714 |
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| 458 | #define TX4927_ACLC_ACINTEN 0xf718 |
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| 459 | #define TX4927_ACLC_ACINTDIS 0xf71c |
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| 460 | #define TX4927_ACLC_ACSEMAPH 0xf720 |
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| 461 | #define TX4927_ACLC_ACGPIDAT 0xf740 |
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| 462 | #define TX4927_ACLC_ACGPODAT 0xf744 |
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| 463 | #define TX4927_ACLC_ACSLTEN 0xf748 |
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| 464 | #define TX4927_ACLC_ACSLTDIS 0xf74c |
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| 465 | #define TX4927_ACLC_ACFIFOSTS 0xf750 |
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| 466 | #define TX4927_ACLC_ACDMASTS 0xf780 |
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| 467 | #define TX4927_ACLC_ACDMASEL 0xf784 |
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| 468 | #define TX4927_ACLC_ACAUDODAT 0xf7a0 |
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| 469 | #define TX4927_ACLC_ACSURRDAT 0xf7a4 |
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| 470 | #define TX4927_ACLC_ACCENTDAT 0xf7a8 |
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| 471 | #define TX4927_ACLC_ACLFEDAT 0xf7ac |
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| 472 | #define TX4927_ACLC_ACAUDIDAT 0xf7b0 |
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| 473 | #define TX4927_ACLC_ACMODODAT 0xf7b8 |
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| 474 | #define TX4927_ACLC_ACMODIDAT 0xf7bc |
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| 475 | #define TX4927_ACLC_ACREVID 0xf7fc |
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| 476 | #define TX4927_ACLC_LIMIT 0xf7ff |
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| 477 | |
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| 478 | |
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| 479 | #define TX4927_REG(x) ((TX4927_BASE)+(x)) |
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| 480 | |
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| 481 | #define TX4927_RD08( reg ) (*(vu08*)(reg)) |
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| 482 | #define TX4927_WR08( reg, val ) ((*(vu08*)(reg))=(val)) |
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| 483 | |
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| 484 | #define TX4927_RD16( reg ) (*(vu16*)(reg)) |
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| 485 | #define TX4927_WR16( reg, val ) ((*(vu16*)(reg))=(val)) |
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| 486 | |
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| 487 | #define TX4927_RD32( reg ) (*(vu32*)(reg)) |
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| 488 | #define TX4927_WR32( reg, val ) ((*(vu32*)(reg))=(val)) |
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| 489 | |
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| 490 | #define TX4927_RD64( reg ) (*(vu64*)(reg)) |
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| 491 | #define TX4927_WR64( reg, val ) ((*(vu64*)(reg))=(val)) |
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| 492 | |
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| 493 | #define TX4927_RD( reg ) TX4927_RD32( reg ) |
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| 494 | #define TX4927_WR( reg, val ) TX4927_WR32( reg, val ) |
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| 495 | |
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| 496 | |
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| 497 | |
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| 498 | |
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| 499 | |
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| 500 | #define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */ |
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| 501 | #define MI8259_IRQ_ISA_RAW_END 15 |
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| 502 | #define TX4927_IRQ_CP0_RAW_BEG 0 /* tx4927 cpu built-in cp0 */ |
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| 503 | #define TX4927_IRQ_CP0_RAW_END 7 |
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| 504 | #define TX4927_IRQ_PIC_RAW_BEG 0 /* tx4927 cpu build-in pic */ |
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| 505 | #define TX4927_IRQ_PIC_RAW_END 31 |
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| 506 | |
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| 507 | |
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| 508 | #define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */ |
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| 509 | #define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */ |
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| 510 | |
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| 511 | #define TX4927_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG) /* 16 */ |
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| 512 | #define TX4927_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END) /* 23 */ |
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| 513 | |
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| 514 | #define TX4927_IRQ_PIC_BEG ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG) /* 24 */ |
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| 515 | #define TX4927_IRQ_PIC_END ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END) /* 55 */ |
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| 516 | |
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| 517 | |
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| 518 | #define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) |
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| 519 | #define TX4927_IRQ_USER1 (TX4927_IRQ_CP0_BEG+1) |
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| 520 | #define TX4927_IRQ_NEST_PIC_ON_CP0 (TX4927_IRQ_CP0_BEG+2) |
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| 521 | #define TX4927_IRQ_CPU_TIMER (TX4927_IRQ_CP0_BEG+7) |
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| 522 | |
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| 523 | #define TX4927_IRQ_NEST_EXT_ON_PIC (TX4927_IRQ_PIC_BEG+3) |
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| 524 | |
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| 525 | #endif /* __ASM_TX4927_TX4927_H */ |
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