source: svn/branches/kctv/zas_dstar/devices/includes/HDMI_TX_System_Config.h

//  ANALOGIX Company 
//  HDMI_TX Demo Firmware on SST

#define USE_HDMI_RX             0

#include "HDMI_TX_DRV.h"

//user interface define begins

//select video hardware interface
#define HDMI_TX_VID_HW_INTERFACE 0x00//0x00:RGB and YcbCr 4:4:4 Formats with Separate Syncs (24-bpp mode)
                                                                 //0x01:YCbCr 4:2:2 Formats with Separate Syncs(16-bbp)
                                                                 //0x02:YCbCr 4:2:2 Formats with Embedded Syncs(No HS/VS/DE)
                                                                 //0x03:YC Mux 4:2:2 Formats with Separate Sync Mode1(bit15:8 and bit 3:0 are used)
                                                                 //0x04:YC Mux 4:2:2 Formats with Separate Sync Mode2(bit11:0 are used)
                                                                 //0x05:YC Mux 4:2:2 Formats with Embedded Sync Mode1(bit15:8 and bit 3:0 are used)
                                                                 //0x06:YC Mux 4:2:2 Formats with Embedded Sync Mode2(bit11:0 are used)
                                                                 //0x07:RGB and YcbCr 4:4:4 DDR Formats with Separate Syncs
                                                                 //0x08:RGB and YcbCr 4:4:4 DDR Formats with Embedded Syncs
                                                                 //0x09:RGB and YcbCr 4:4:4 Formats with Separate Syncs but no DE
                                                                 //0x0a:YCbCr 4:2:2 Formats with Separate Syncs but no DE
//select input color space
#define HDMI_TX_INPUT_COLORSPACE 0x00//0x00: input color space is RGB
                                                                //0x01: input color space is YCbCr422
                                                                //0x02: input color space is YCbCr444
//select input pixel clock edge for DDR mode
#define HDMI_TX_IDCK_EDGE_DDR 0x01  //0x00:use rising edge to latch even numbered pixel data
                                                                //0x01:use falling edge to latch even numbered pixel data 

//select audio hardware interface
#define HDMI_TX_AUD_HW_INTERFACE 0x02//0x01:audio input comes from I2S
                                                                  //0x02:audio input comes from SPDIF
                                                                  //0x04:audio input comes from one bit audio
//select MCLK and Fs relationship if audio HW interface is I2S
#define HDMI_TX_MCLK_Fs_RELATION 0x01//0x00:MCLK = 128 * Fs
                                                                //0x01:MCLK = 256 * Fs
                                                                //0x02:MCLK = 384 * Fs
                                                                //0x03:MCLK = 512 * Fs
//select I2S channel numbers if audio HW interface is I2S
#define HDMI_TX_I2S_CH0_ENABLE 0x01 //0x01:enable channel 0 input; 0x00: disable
#define HDMI_TX_I2S_CH1_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable
#define HDMI_TX_I2S_CH2_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable
#define HDMI_TX_I2S_CH3_ENABLE 0x00 //0x01:enable channel 0 input; 0x00: disable
//select I2S word length if audio HW interface is I2S
#define HDMI_TX_I2S_WORD_LENGTH 0x0b
                                        //0x02 = 16bits; 0x04 = 18 bits; 0x08 = 19 bits; 0x0a = 20 bits(maximal word length is 20bits); 0x0c = 17 bits;
                                        // 0x03 = 20bits(maximal word length is 24bits); 0x05 = 22 bits; 0x09 = 23 bits; 0x0b = 24 bits; 0x0d = 21 bits;
//select audio Fs
#define HDMI_TX_AUD_Fs 0x02 // 0x00 = 44.1 KHz
                                                // 0x02 = 48 KHz
                                                // 0x03 = 32 KHz
//select I2S format if audio HW interface is I2S
#define HDMI_TX_I2S_SHIFT_CTRL 0x00//0x00: fist bit shift(philips spec)
                                                                //0x01:no shift
#define HDMI_TX_I2S_DIR_CTRL 0x00//0x00:SD data MSB first
                                                            //0x01:LSB first
#define HDMI_TX_I2S_WS_POL 0x00//0x00:left polarity when word select is low
                                                        //0x01:left polarity when word select is high
#define HDMI_TX_I2S_JUST_CTRL 0x00//0x00:data is left justified
                                                             //0x01:data is right justified

//user interface define ends

extern BYTE hdmi_tx_new_HW_interface_parameter;

void HDMI_TX_API_Video_Config(BYTE video_id,BYTE input_pixel_rpt_time);
void HDMI_TX_API_AUD_CHStatus_Config(BYTE MODE,BYTE PCM_MODE,BYTE SW_CPRGT,BYTE NON_PCM,
    BYTE PROF_APP,BYTE CAT_CODE,BYTE CH_NUM,BYTE SOURCE_NUM,BYTE CLK_ACCUR,BYTE Fs);
BIT HDMI_TX_API_DetectDevice(void);
void HDMI_TX_API_HoldVideoConfig(BIT hold_video);
void HDMI_TX_API_HoldAudioConfig(BIT hold_audio);
void HDMI_TX_API_ShutDown(BIT bShutDown_HDMI_TX);
void HDMI_TX_API_HDCP_ONorOFF(BIT HDCP_ONorOFF);
void HDMI_TX_API_Packets_Config(BYTE pkt_sel);
void HDMI_TX_API_AVI_Config(BYTE pb1,BYTE pb2,BYTE pb3,BYTE pb4,BYTE pb5,
    BYTE pb6,BYTE pb7,BYTE pb8,BYTE pb9,BYTE pb10,BYTE pb11,BYTE pb12,BYTE pb13);
void HDMI_TX_API_AUD_INFO_Config(BYTE pb1,BYTE pb2,BYTE pb3,BYTE pb4,BYTE pb5,
    BYTE pb6,BYTE pb7,BYTE pb8,BYTE pb9,BYTE pb10);
void HDMI_TX_API_Audio_Config(BYTE aud_fs);
void HDMI_TX_API_SetGamutStatus(DS_BOOL on);
DS_BOOL HDMI_TX_API_GetGamutStatus(void);
void HDMI_TX_Config_Manual_Video_FormatEx(const struct Video_Timing *pVT);