| 1 | #include "bapp.h" |
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| 2 | #include "bstd.h" |
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| 3 | #include "gist.h" |
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| 4 | #include "bchp_aon_ctrl.h" |
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| 5 | #include "bchp_aon_pm_l2.h" |
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| 6 | #include "bchp_kbd1.h" |
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| 7 | #include "bchp_gio_aon.h" |
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| 8 | |
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| 9 | BDBG_MODULE("birw"); |
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| 10 | |
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| 11 | extern void bdisplay_standby(bdisplay_t display, bool standby); |
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| 12 | #if HAS_HDMI |
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| 13 | extern void bsettop_hdmi_standby(bsettop_hdmi_t h_hdmi, bool standby); |
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| 14 | #endif |
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| 15 | extern void brfm_standby(brfm_t rfm, bool standby); |
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| 16 | extern void baudio_decode_standby(baudio_decode_t audio, bool standby); |
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| 17 | |
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| 18 | #ifdef ACB612 |
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| 19 | #if(USERIO_ID == 5) |
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| 20 | const uint32_t cir_rca_param_regs[] = |
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| 21 | { |
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| 22 | //BCHP_KBD1_CMD, 0, |
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| 23 | BCHP_KBD1_CIR_ADDR, 0, BCHP_KBD1_CIR_DATA, 0x87, |
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| 24 | BCHP_KBD1_CIR_ADDR, 1, BCHP_KBD1_CIR_DATA, 0, |
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| 25 | BCHP_KBD1_CIR_ADDR, 2, BCHP_KBD1_CIR_DATA, 0x02, |
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| 26 | BCHP_KBD1_CIR_ADDR, 3, BCHP_KBD1_CIR_DATA, 0x190, |
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| 27 | BCHP_KBD1_CIR_ADDR, 4, BCHP_KBD1_CIR_DATA, 0, |
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| 28 | BCHP_KBD1_CIR_ADDR, 5, BCHP_KBD1_CIR_DATA, 0x190, |
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| 29 | BCHP_KBD1_CIR_ADDR, 6, BCHP_KBD1_CIR_DATA, 0, |
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| 30 | BCHP_KBD1_CIR_ADDR, 7, BCHP_KBD1_CIR_DATA, 0, |
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| 31 | BCHP_KBD1_CIR_ADDR, 8, BCHP_KBD1_CIR_DATA, 0, |
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| 32 | BCHP_KBD1_CIR_ADDR, 9, BCHP_KBD1_CIR_DATA, 0, |
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| 33 | BCHP_KBD1_CIR_ADDR, 10, BCHP_KBD1_CIR_DATA, 0, |
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| 34 | BCHP_KBD1_CIR_ADDR, 11, BCHP_KBD1_CIR_DATA, 0x17, |
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| 35 | BCHP_KBD1_CIR_ADDR, 12, BCHP_KBD1_CIR_DATA, 0xc32, |
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| 36 | BCHP_KBD1_CIR_ADDR, 13, BCHP_KBD1_CIR_DATA, 0x400, |
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| 37 | BCHP_KBD1_CIR_ADDR, 14, BCHP_KBD1_CIR_DATA, 0x96, |
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| 38 | BCHP_KBD1_CIR_ADDR, 15, BCHP_KBD1_CIR_DATA, 0x64, |
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| 39 | BCHP_KBD1_CIR_ADDR, 16, BCHP_KBD1_CIR_DATA, 0x10d, |
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| 40 | BCHP_KBD1_CIR_ADDR, 17, BCHP_KBD1_CIR_DATA, 0x32, |
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| 41 | BCHP_KBD1_CIR_ADDR, 18, BCHP_KBD1_CIR_DATA, 0xb0, |
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| 42 | BCHP_KBD1_CIR_ADDR, 19, BCHP_KBD1_CIR_DATA, 0x31, |
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| 43 | BCHP_KBD1_CIR_ADDR, 20, BCHP_KBD1_CIR_DATA, 0xb, |
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| 44 | BCHP_KBD1_CIR_ADDR, 21, BCHP_KBD1_CIR_DATA, 0xc, |
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| 45 | BCHP_KBD1_CIR_ADDR, 22, BCHP_KBD1_CIR_DATA, 0, |
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| 46 | BCHP_KBD1_CIR_ADDR, 23, BCHP_KBD1_CIR_DATA, 0, |
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| 47 | BCHP_KBD1_CIR_ADDR, 24, BCHP_KBD1_CIR_DATA, 0, |
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| 48 | //BCHP_KBD1_CMD, 0x130, /* must match, enable interrupt, CIR */ |
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| 49 | 0 |
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| 50 | }; |
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| 51 | #endif |
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| 52 | |
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| 53 | #if(USERIO_ID == 4 || USERIO_ID == 10 || USERIO_ID == 11 || USERIO_ID == 12 || USERIO_ID == 15) |
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| 54 | |
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| 55 | const uint32_t cir_nec_param_regs[] = |
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| 56 | { |
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| 57 | //BCHP_KBD1_CMD, 0, |
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| 58 | BCHP_KBD1_CIR_ADDR, 0, BCHP_KBD1_CIR_DATA, 0xc8, |
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| 59 | BCHP_KBD1_CIR_ADDR, 1, BCHP_KBD1_CIR_DATA, 0, |
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| 60 | BCHP_KBD1_CIR_ADDR, 2, BCHP_KBD1_CIR_DATA, 0x12, |
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| 61 | BCHP_KBD1_CIR_ADDR, 3, BCHP_KBD1_CIR_DATA, 0x384, |
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| 62 | BCHP_KBD1_CIR_ADDR, 4, BCHP_KBD1_CIR_DATA, 0x381, |
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| 63 | BCHP_KBD1_CIR_ADDR, 5, BCHP_KBD1_CIR_DATA, 0x1c2, |
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| 64 | BCHP_KBD1_CIR_ADDR, 6, BCHP_KBD1_CIR_DATA, 0xe1, |
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| 65 | BCHP_KBD1_CIR_ADDR, 7, BCHP_KBD1_CIR_DATA, 0, |
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| 66 | BCHP_KBD1_CIR_ADDR, 8, BCHP_KBD1_CIR_DATA, 0, |
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| 67 | BCHP_KBD1_CIR_ADDR, 9, BCHP_KBD1_CIR_DATA, 0, |
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| 68 | BCHP_KBD1_CIR_ADDR, 10, BCHP_KBD1_CIR_DATA, 0, |
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| 69 | BCHP_KBD1_CIR_ADDR, 11, BCHP_KBD1_CIR_DATA, 0x1f, |
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| 70 | BCHP_KBD1_CIR_ADDR, 12, BCHP_KBD1_CIR_DATA, 0xc32, |
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| 71 | BCHP_KBD1_CIR_ADDR, 13, BCHP_KBD1_CIR_DATA, 0x400, |
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| 72 | BCHP_KBD1_CIR_ADDR, 14, BCHP_KBD1_CIR_DATA, 0x71, |
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| 73 | BCHP_KBD1_CIR_ADDR, 15, BCHP_KBD1_CIR_DATA, 0x71, |
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| 74 | BCHP_KBD1_CIR_ADDR, 16, BCHP_KBD1_CIR_DATA, 0x10d, |
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| 75 | BCHP_KBD1_CIR_ADDR, 17, BCHP_KBD1_CIR_DATA, 0x32, |
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| 76 | BCHP_KBD1_CIR_ADDR, 18, BCHP_KBD1_CIR_DATA, 0xb0, |
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| 77 | BCHP_KBD1_CIR_ADDR, 19, BCHP_KBD1_CIR_DATA, 0x31, |
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| 78 | BCHP_KBD1_CIR_ADDR, 20, BCHP_KBD1_CIR_DATA, 0x16, |
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| 79 | BCHP_KBD1_CIR_ADDR, 21, BCHP_KBD1_CIR_DATA, 0x6, |
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| 80 | BCHP_KBD1_CIR_ADDR, 22, BCHP_KBD1_CIR_DATA, 0, |
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| 81 | BCHP_KBD1_CIR_ADDR, 23, BCHP_KBD1_CIR_DATA, 0, |
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| 82 | BCHP_KBD1_CIR_ADDR, 24, BCHP_KBD1_CIR_DATA, 0, |
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| 83 | 0 |
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| 84 | }; |
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| 85 | #endif |
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| 86 | #endif |
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| 87 | |
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| 88 | void b_s3_standby(uint32_t id) |
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| 89 | { |
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| 90 | uint32_t val; |
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| 91 | |
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| 92 | /* setup data filter for PWR IR code */ |
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| 93 | if (id == 1) { |
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| 94 | BREG_Write32(GetREG(), BCHP_KBD1_CMD, 0x121); |
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| 95 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK0,0xFFFF00FF); |
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| 96 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK1,0x00FFFFFF); |
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| 97 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK2,0xFFFFFFFF); |
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| 98 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT0, 0x00000F00); |
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| 99 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT1, 0x0F000000); |
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| 100 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT2, 0x00000000); |
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| 101 | } |
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| 102 | else if (id == 8) { |
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| 103 | BREG_Write32(GetREG(), BCHP_KBD1_CMD, 0x134); |
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| 104 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK0,0xFFFFFF00); |
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| 105 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK1,0xFF00FFFF); |
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| 106 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK2,0xFFFFFFFF); |
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| 107 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT0, 0x0000000A); |
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| 108 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT1, 0x000A0000); |
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| 109 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT2, 0x00000000); |
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| 110 | } |
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| 111 | else if (id == 9) { |
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| 112 | BREG_Write32(GetREG(), BCHP_KBD1_CMD, 0x130); |
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| 113 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK0,0xFF00FFFF); |
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| 114 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK1,0xFFFFFFFF); |
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| 115 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK2,0xFFFFFF00); |
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| 116 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT0, 0x000a0000); |
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| 117 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT1, 0x00000000); |
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| 118 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT2, 0x0000000a); |
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| 119 | } |
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| 120 | #ifdef ACB612 |
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| 121 | #if(USERIO_ID == 5) |
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| 122 | else if (5 == id) { |
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| 123 | int i, count; |
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| 124 | |
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| 125 | count = sizeof(cir_rca_param_regs)/sizeof(cir_rca_param_regs[0]); |
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| 126 | i = 0; |
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| 127 | do { |
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| 128 | if (0 == cir_rca_param_regs[i]) { |
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| 129 | break; |
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| 130 | } |
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| 131 | if (BCHP_KBD1_CMD == cir_rca_param_regs[i]) { |
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| 132 | BREG_Write32(GetREG(), cir_rca_param_regs[i], cir_rca_param_regs[i+1]); |
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| 133 | i += 2; |
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| 134 | } |
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| 135 | else { |
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| 136 | /* progress CIR */ |
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| 137 | /* CIR address */ |
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| 138 | BREG_Write32(GetREG(), cir_rca_param_regs[i], cir_rca_param_regs[i+1]); i += 2; |
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| 139 | /* CIR data */ |
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| 140 | BREG_Write32(GetREG(), cir_rca_param_regs[i], cir_rca_param_regs[i+1]); i += 2; |
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| 141 | } |
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| 142 | } while (i < count); |
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| 143 | |
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| 144 | /* RCA */ |
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| 145 | BREG_Write32(GetREG(), BCHP_KBD1_CMD, 0x130); /* must match, enable interrupt, CIR */ |
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| 146 | |
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| 147 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK0,0xFF8FFF00); |
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| 148 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT0, 0x007000d5); |
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| 149 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK1,0xFF00FFFF); |
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| 150 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT1, 0x00d50000); |
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| 151 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK2,0xFFFFFF8F); |
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| 152 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT2, 0x00000070); |
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| 153 | } |
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| 154 | #endif |
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| 155 | #if(USERIO_ID == 12 || USERIO_ID == 11 || USERIO_ID == 10 || USERIO_ID == 4 || USERIO_ID == 15) |
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| 156 | else if (12 == id ||11 == id || 10 == id || 4 == id || 15 == id) { |
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| 157 | int i, count; |
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| 158 | |
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| 159 | count = sizeof(cir_nec_param_regs)/sizeof(cir_nec_param_regs[0]); |
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| 160 | i = 0; |
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| 161 | do { |
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| 162 | if (0 == cir_nec_param_regs[i]) { |
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| 163 | break; |
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| 164 | } |
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| 165 | if (BCHP_KBD1_CMD == cir_nec_param_regs[i]) { |
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| 166 | BREG_Write32(GetREG(), cir_nec_param_regs[i], cir_nec_param_regs[i+1]); |
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| 167 | i += 2; |
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| 168 | } |
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| 169 | else { |
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| 170 | /* progress CIR */ |
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| 171 | /* CIR address */ |
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| 172 | BREG_Write32(GetREG(), cir_nec_param_regs[i], cir_nec_param_regs[i+1]); i += 2; |
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| 173 | /* CIR data */ |
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| 174 | BREG_Write32(GetREG(), cir_nec_param_regs[i], cir_nec_param_regs[i+1]); i += 2; |
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| 175 | } |
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| 176 | } while (i < count); |
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| 177 | /* NEC */ |
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| 178 | #if( USERIO_ID == 12)/*janzy@20121030,add remote Skyworth_01*//*0x80BF3BC4*/ |
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| 179 | BREG_Write32(GetREG(), BCHP_KBD1_CMD, 0x130); /* must match, enable interrupt, CIR */ |
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| 180 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK0, 0xFFFFFF00); |
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| 181 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT0, 0x000000C4); |
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| 182 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK1, 0xFF00FFFF); |
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| 183 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT1, 0x00BF0000); |
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| 184 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK2, 0xFFFFFFFF); |
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| 185 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT2, 0x00000000); |
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| 186 | #endif |
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| 187 | |
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| 188 | #if( USERIO_ID == 11)/*0x008118e7*/ |
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| 189 | BREG_Write32(GetREG(), BCHP_KBD1_CMD, 0x130); /* must match, enable interrupt, CIR */ |
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| 190 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK0, 0xFFFFFF00); |
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| 191 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT0, 0x000000E7); |
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| 192 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK1, 0xFF00FFFF); |
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| 193 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT1, 0x00810000); |
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| 194 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK2, 0xFFFFFFFF); |
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| 195 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT2, 0x00000000); |
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| 196 | #endif |
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| 197 | #if( USERIO_ID == 10)/*0x01FEC03F*/ |
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| 198 | BREG_Write32(GetREG(), BCHP_KBD1_CMD, 0x130); /* must match, enable interrupt, CIR */ |
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| 199 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK0, 0xFFFFFF00); |
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| 200 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT0, 0x0000003F); |
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| 201 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK1, 0xFF00FFFF); |
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| 202 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT1, 0x003F0000); |
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| 203 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK2, 0xFFFFFFFF); |
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| 204 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT2, 0x00000000); |
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| 205 | #endif |
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| 206 | #if(USERIO_ID == 4)/*0x0066B847*/ |
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| 207 | BREG_Write32(GetREG(), BCHP_KBD1_CMD, 0x130); /* must match, enable interrupt, CIR */ |
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| 208 | |
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| 209 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK0, 0xFF8FFF00); |
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| 210 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT0, 0x00600047); |
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| 211 | |
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| 212 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK1, 0xFF00FFFF); |
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| 213 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT1, 0x00660000); |
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| 214 | |
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| 215 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK2, 0xFFFF0000); |
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| 216 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT2, 0x0000B847); |
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| 217 | #endif |
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| 218 | #if (15 == USERIO_ID) // CMB 0xFF000820 --> 0x041000FF (ºñÆ® ¹æÇ⠰ŲٷÎ) °Å²Ù·ÎµÈ ºñÆ®¸¦ 24ºñÆ® ´ÜÀ§·Î °ªÀ» ¼³Á¤ÇØ¾ß ÇÔ |
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| 219 | BREG_Write32(GetREG(), BCHP_KBD1_CMD, 0x130); /* must match, enable interrupt, CIR */ |
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| 220 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK0, ~0x041000FF); // 0xF6090820 |
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| 221 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT0, 0x041000FF); |
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| 222 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK1, ~0x00FF0000); |
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| 223 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT1, 0x00FF0000); |
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| 224 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_MASK2, ~0x00000410); |
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| 225 | BREG_Write32(GetREG(), BCHP_KBD1_KBD_PAT2, 0x00000410); |
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| 226 | #endif |
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| 227 | } |
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| 228 | #endif |
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| 229 | #endif |
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| 230 | else { |
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| 231 | BDBG_ERR(("USERIO_ID %d is not supported for S3 standby now", id)); |
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| 232 | return; |
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| 233 | } |
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| 234 | /* clear KBD1 interrupt */ |
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| 235 | val = BREG_Read32(GetREG(), BCHP_KBD1_STATUS); |
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| 236 | val &= ~BCHP_KBD1_STATUS_irq_MASK; |
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| 237 | BREG_Write32(GetREG(), BCHP_KBD1_STATUS, val); |
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| 238 | |
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| 239 | /* clear reset history */ |
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| 240 | BREG_Write32(GetREG(), BCHP_AON_CTRL_RESET_CTRL, BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK); |
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| 241 | |
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| 242 | /* reset wake up device */ |
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| 243 | BREG_Write32(GetREG(), BCHP_AON_PM_L2_CPU_MASK_SET, 0xFFFFFFFF); |
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| 244 | BREG_Write32(GetREG(), BCHP_AON_PM_L2_CPU_CLEAR, 0xFFFFFFF); |
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| 245 | |
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| 246 | #ifdef ACB612 |
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| 247 | /* just allow the power button to generate wake up interrupt, Agpio07 */ |
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| 248 | BREG_Write32(GetREG(), BCHP_GIO_AON_MASK_LO, 0x00000080); |
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| 249 | BREG_Write32(GetREG(), BCHP_GIO_AON_MASK_EXT, 0x00000000); |
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| 250 | #endif |
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| 251 | |
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| 252 | /* enable IR interrupt and GPIO for wakeup */ |
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| 253 | BREG_Write32(GetREG(), BCHP_AON_CTRL_PM_LED_AUTO_ON_ENABLES, 0x2); |
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| 254 | #ifdef ACB612 |
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| 255 | BREG_Write32(GetREG(), BCHP_AON_PM_L2_CPU_MASK_CLEAR, BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK | BCHP_AON_PM_L2_CPU_MASK_STATUS_GPIO_MASK); |
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| 256 | #else |
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| 257 | BREG_Write32(GetREG(), BCHP_AON_PM_L2_CPU_MASK_CLEAR, BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK); |
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| 258 | #endif |
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| 259 | BREG_Write32(GetREG(), BCHP_AON_CTRL_PM_LED_CTRL, BCHP_AON_CTRL_PM_LED_CTRL_led_turn_on_MASK); |
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| 260 | /* power down request */ |
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| 261 | BREG_Write32(GetREG(), BCHP_AON_CTRL_PM_CTRL, 0); |
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| 262 | |
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| 263 | /* enable S3 standby */ |
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| 264 | val = BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK; |
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| 265 | BREG_Write32(GetREG(), BCHP_AON_CTRL_PM_CTRL, val); |
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| 266 | |
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| 267 | /* load precharge value for fast pwrdn */ |
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| 268 | BREG_Write32(GetREG(), BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE, 0xB9E1DC ); |
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| 269 | /* enable fast power down, and issue pwrn down 0->1 transition */ |
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| 270 | val |= BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK|BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK; |
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| 271 | BREG_Write32(GetREG(), BCHP_AON_CTRL_PM_CTRL, val); |
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| 272 | } |
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| 273 | |
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| 274 | void bpwr_control(bapp_t *p_app, bool standby) |
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| 275 | { |
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| 276 | #if HAS_HDMI |
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| 277 | bsettop_hdmi_standby(p_app->hdmi, standby); |
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| 278 | #endif |
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| 279 | brfm_standby(p_app->p_rfm, standby); |
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| 280 | bdisplay_standby(p_app->display, standby); |
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| 281 | baudio_decode_standby(p_app->audio,standby); |
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| 282 | } |
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