| 1 | /************************************************************************* |
|---|
| 2 | ** Broadcom Corp. Confidential |
|---|
| 3 | ** Copyright 2010 Broadcom Corp. All Rights Reserved. |
|---|
| 4 | ** |
|---|
| 5 | ** THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE |
|---|
| 6 | ** AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR |
|---|
| 7 | ** EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. |
|---|
| 8 | ** |
|---|
| 9 | ** File: bls1.S |
|---|
| 10 | ** Description: stage 1 of two stage bootloader for 755x chip. |
|---|
| 11 | ** Created: alexp |
|---|
| 12 | ** |
|---|
| 13 | ** REVISION: |
|---|
| 14 | ** |
|---|
| 15 | ***************************************************************************/ |
|---|
| 16 | |
|---|
| 17 | #include "bmips3300.h" |
|---|
| 18 | #include "bchp.h" |
|---|
| 19 | #include "bchp_common.h" |
|---|
| 20 | #include "bchp_sca.h" |
|---|
| 21 | #include "bchp_scb.h" |
|---|
| 22 | #include "bchp_sun_top_ctrl.h" |
|---|
| 23 | #include "bchp_bsp_glb_control.h" |
|---|
| 24 | #if defined(MEMSYSINIT) |
|---|
| 25 | #include "bchp_memc_gen_0.h" |
|---|
| 26 | #include "bchp_ddr40_phy_control_regs_0.h" |
|---|
| 27 | #include "bchp_memc_ddr23_shim_addr_cntl_0.h" |
|---|
| 28 | #else |
|---|
| 29 | #include "memc_0_config.h" |
|---|
| 30 | #endif |
|---|
| 31 | |
|---|
| 32 | #define BCHP_REG_BASE PHYS_TO_K1(BCHP_PHYSICAL_OFFSET) |
|---|
| 33 | #define INITIAL_SR ((CP0_STATUS_SR_MASK | CP0_STATUS_CU0_MASK | CP0_STATUS_CU1_MASK | CP0_STATUS_BEV_MASK | CP0_STATUS_IE_MASK) & ~( CP0_STATUS_ERL_MASK | CP0_STATUS_EXL_MASK)) |
|---|
| 34 | BL_STACK_SIZE = 0x1000 |
|---|
| 35 | #if (BCHP_VER == BCHP_VER_A0) |
|---|
| 36 | #define PARTB_OFFSET 0xc60 |
|---|
| 37 | #endif |
|---|
| 38 | #if (BCHP_VER == BCHP_VER_B0) |
|---|
| 39 | #define PARTB_OFFSET 0xc80 |
|---|
| 40 | #endif |
|---|
| 41 | .lcomm bl_stack, BL_STACK_SIZE |
|---|
| 42 | .text |
|---|
| 43 | .globl __start |
|---|
| 44 | .set noreorder |
|---|
| 45 | .func __start |
|---|
| 46 | __start: |
|---|
| 47 | b nmi_check |
|---|
| 48 | nop |
|---|
| 49 | nop |
|---|
| 50 | nop |
|---|
| 51 | /* size of stage1+stage2 */ |
|---|
| 52 | .word _bootloader_size |
|---|
| 53 | .org __start+0x180 |
|---|
| 54 | except1: |
|---|
| 55 | b except1 |
|---|
| 56 | nop |
|---|
| 57 | .org __start+0x200 |
|---|
| 58 | except2: |
|---|
| 59 | b except2 |
|---|
| 60 | nop |
|---|
| 61 | .org __start+0x380 |
|---|
| 62 | rom_gen_ex: # general exception will loop here |
|---|
| 63 | b rom_gen_ex |
|---|
| 64 | nop |
|---|
| 65 | /* Starting at offset 0x400 various fields for BSP must be placed in the |
|---|
| 66 | flash image.*/ |
|---|
| 67 | .org __start+0x400 |
|---|
| 68 | #if (BCHP_VER == BCHP_VER_A0) |
|---|
| 69 | .word 0x000073a0 |
|---|
| 70 | /* flash block size */ |
|---|
| 71 | .word 0x80 |
|---|
| 72 | /* flags */ |
|---|
| 73 | .word 0x07000202 |
|---|
| 74 | /* stage 2 boot code size */ |
|---|
| 75 | .word 0x12345678 |
|---|
| 76 | .org __start+0x420 |
|---|
| 77 | /* bsec parameter signature */ |
|---|
| 78 | .fill 0x100,1,0x22 |
|---|
| 79 | /* stage 1 signature */ |
|---|
| 80 | .fill 0x100,1,0x33 |
|---|
| 81 | /* key 1 */ |
|---|
| 82 | .fill 0x100,1,0x44 |
|---|
| 83 | /* key 1 parameters */ |
|---|
| 84 | .word 0x08000100 |
|---|
| 85 | /* market id */ |
|---|
| 86 | .word 0x00000000 |
|---|
| 87 | /* filler data, can be anything */ |
|---|
| 88 | .word 0xf111f111, 0xf111f111 |
|---|
| 89 | /* key 1 signature calculated from 0x620 to 0x72f */ |
|---|
| 90 | .fill 0x100,1,0x55 |
|---|
| 91 | .fill 0x20, 1, 0x66 |
|---|
| 92 | #endif |
|---|
| 93 | #if (BCHP_VER == BCHP_VER_B0) |
|---|
| 94 | /* stage 1 part b size, hardcoded to max size */ |
|---|
| 95 | .word 0x00006F80 |
|---|
| 96 | /* reserved, must be this value */ |
|---|
| 97 | .word 0x00000080 |
|---|
| 98 | /* flags */ |
|---|
| 99 | .word 0x07000202 |
|---|
| 100 | /* stage 2 boot code size */ |
|---|
| 101 | .word 0x12345678 |
|---|
| 102 | .org __start+0x440 |
|---|
| 103 | /* bsec parameter signature */ |
|---|
| 104 | .fill 0x100,1,0x22 |
|---|
| 105 | /* stage 1 signature 0x540*/ |
|---|
| 106 | .fill 0x100,1,0x33 |
|---|
| 107 | /* include oem key file */ |
|---|
| 108 | #include "dummy_key1.S" |
|---|
| 109 | #endif |
|---|
| 110 | /* bsp pointers */ |
|---|
| 111 | .word __bsp_key0 |
|---|
| 112 | .word __bsp_fw |
|---|
| 113 | .org __start + PARTB_OFFSET |
|---|
| 114 | .align 4 |
|---|
| 115 | nmi_check: |
|---|
| 116 | mfc0 k0, CP0_STATUS |
|---|
| 117 | nop |
|---|
| 118 | nop |
|---|
| 119 | li k1, 0x00080000 |
|---|
| 120 | and k0, k0, k1 |
|---|
| 121 | beqz k0, start1 |
|---|
| 122 | nop |
|---|
| 123 | /* NMI handler */ |
|---|
| 124 | mfc0 k0, CP0_STATUS |
|---|
| 125 | nop |
|---|
| 126 | nop |
|---|
| 127 | li k1, ~0x00080000 |
|---|
| 128 | and k0, k0, k1 |
|---|
| 129 | mtc0 k0, CP0_STATUS |
|---|
| 130 | nop |
|---|
| 131 | nop |
|---|
| 132 | li k0, 0x1 |
|---|
| 133 | li k1, PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_SCA_SC_IF_CMD_1) |
|---|
| 134 | sw k0, 0(k1) |
|---|
| 135 | li k1, PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_SCB_SC_IF_CMD_1) |
|---|
| 136 | sw k0, 0(k1) |
|---|
| 137 | eret |
|---|
| 138 | nop |
|---|
| 139 | start1: |
|---|
| 140 | li t0, INITIAL_SR |
|---|
| 141 | mtc0 t0, CP0_STATUS |
|---|
| 142 | nop |
|---|
| 143 | nop |
|---|
| 144 | /* Clear software interrupts */ |
|---|
| 145 | mtc0 zero, CP0_CAUSE |
|---|
| 146 | nop |
|---|
| 147 | nop |
|---|
| 148 | |
|---|
| 149 | /* Allow NMI from BSP */ |
|---|
| 150 | li t0, PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_BSP_GLB_CONTROL_MIPS_NMI_STATUS) |
|---|
| 151 | lw t1, 0(t0) |
|---|
| 152 | or t1, t1, BCHP_BSP_GLB_CONTROL_MIPS_NMI_STATUS_NMI_STATUS_MASK |
|---|
| 153 | sw t1, 0(t0) |
|---|
| 154 | |
|---|
| 155 | bal init_serial |
|---|
| 156 | nop |
|---|
| 157 | |
|---|
| 158 | bal _writeasm |
|---|
| 159 | li a0, '$' |
|---|
| 160 | |
|---|
| 161 | bal do_chip_init |
|---|
| 162 | nop |
|---|
| 163 | |
|---|
| 164 | bal _writeasm |
|---|
| 165 | li a0, '>' |
|---|
| 166 | |
|---|
| 167 | bal read_pc |
|---|
| 168 | lui t1,0x2000 |
|---|
| 169 | read_pc: |
|---|
| 170 | and t1, t1, ra |
|---|
| 171 | beqz t1, running_from_cache |
|---|
| 172 | nop |
|---|
| 173 | /* we are running from uncached space. initialize mips and cache*/ |
|---|
| 174 | bal init_mips |
|---|
| 175 | nop |
|---|
| 176 | |
|---|
| 177 | la t1, running_from_cache |
|---|
| 178 | jr t1 |
|---|
| 179 | nop |
|---|
| 180 | running_from_cache: |
|---|
| 181 | #if defined(MEMSYSINIT) |
|---|
| 182 | #define SHMOO_STACK_SIZE (32 * 1024) |
|---|
| 183 | #define SHMOO_STACK_START (0x80000000) |
|---|
| 184 | li a0, SHMOO_STACK_START |
|---|
| 185 | li a1, SHMOO_STACK_SIZE |
|---|
| 186 | bal validate_dcache_data |
|---|
| 187 | nop |
|---|
| 188 | la sp, (SHMOO_STACK_START + SHMOO_STACK_SIZE - 24) |
|---|
| 189 | #if defined(AVS_ENABLE) |
|---|
| 190 | la t0, AvsStart |
|---|
| 191 | jalr t0 |
|---|
| 192 | nop |
|---|
| 193 | #endif |
|---|
| 194 | li a0, 0xbfc00000+MCB0_OFFSET |
|---|
| 195 | li a1, PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_MEMC_GEN_0_CORE_REV_ID) // MEMC_TOP register base addr |
|---|
| 196 | |
|---|
| 197 | li a2, PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION) // DDR40_PHY register base addr |
|---|
| 198 | li a3, PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG) // DDR23_SHIM register base addr |
|---|
| 199 | li t0, 0x0 |
|---|
| 200 | sw t0, 16(sp) |
|---|
| 201 | jal memsys_init |
|---|
| 202 | nop |
|---|
| 203 | |
|---|
| 204 | // check v0 here |
|---|
| 205 | beqz v0, shmoo_step |
|---|
| 206 | nop |
|---|
| 207 | 1: /* infinite loop */ |
|---|
| 208 | b 1b |
|---|
| 209 | nop |
|---|
| 210 | shmoo_step: |
|---|
| 211 | bal run_shmoo |
|---|
| 212 | nop |
|---|
| 213 | beqz v0, shmoo_done |
|---|
| 214 | nop |
|---|
| 215 | 1: /* infinite loop */ |
|---|
| 216 | b 1b |
|---|
| 217 | nop |
|---|
| 218 | |
|---|
| 219 | #else |
|---|
| 220 | bal memc_0_ddr_init |
|---|
| 221 | nop |
|---|
| 222 | |
|---|
| 223 | bal _writeasm |
|---|
| 224 | li a0, '=' |
|---|
| 225 | |
|---|
| 226 | #if BCHP_VER == BCHP_VER_A0 |
|---|
| 227 | /* DUMMY SCB0 write from MIPS */ |
|---|
| 228 | li a0, 0xa0000000 |
|---|
| 229 | sw zero, 0(a0) |
|---|
| 230 | #endif |
|---|
| 231 | bal run_shmoo |
|---|
| 232 | nop |
|---|
| 233 | #endif |
|---|
| 234 | shmoo_done: |
|---|
| 235 | #if defined(BOOT_SCRAMBLE_DRAM) |
|---|
| 236 | bal scramble_sdram |
|---|
| 237 | nop |
|---|
| 238 | #endif |
|---|
| 239 | /* mips boot rom must be hidden otherwise BSP will reboot MIPS upon |
|---|
| 240 | transferring execution to the ram address */ |
|---|
| 241 | bal hide_mips_boot_rom |
|---|
| 242 | nop |
|---|
| 243 | |
|---|
| 244 | la a0, _stage2_start |
|---|
| 245 | or a0, 0x20000000 |
|---|
| 246 | la a1, __start_s2 |
|---|
| 247 | la a2, _stage2_size |
|---|
| 248 | addiu a2, a2, 0x100 |
|---|
| 249 | bal aligned_copy |
|---|
| 250 | nop |
|---|
| 251 | /* flush invalidate d cache */ |
|---|
| 252 | bal clear_all_d_cache |
|---|
| 253 | nop |
|---|
| 254 | |
|---|
| 255 | #if 0 |
|---|
| 256 | /* authenticate stage 2 */ |
|---|
| 257 | la a0, __start_s2 |
|---|
| 258 | and a0, 0xffff |
|---|
| 259 | move a1, a0 |
|---|
| 260 | addiu a0, a0, 2 |
|---|
| 261 | la a3, _stage2_size |
|---|
| 262 | add a1, a1, a3 |
|---|
| 263 | move a2, a1 |
|---|
| 264 | addiu a1, a1, -1 |
|---|
| 265 | li a3, 0x01ff0000 |
|---|
| 266 | bal aegis_arch_r2_setup |
|---|
| 267 | nop |
|---|
| 268 | #endif |
|---|
| 269 | la t0,__start_s2 |
|---|
| 270 | or t0, 0x20000000 |
|---|
| 271 | jalr t0 |
|---|
| 272 | nop |
|---|
| 273 | loop: |
|---|
| 274 | b loop |
|---|
| 275 | nop |
|---|
| 276 | .endfunc |
|---|
| 277 | |
|---|
| 278 | LEAF(aligned_copy) |
|---|
| 279 | |
|---|
| 280 | 1: |
|---|
| 281 | lw v0, 0(a0) |
|---|
| 282 | addiu a2, a2, -4 |
|---|
| 283 | sw v0, 0(a1) |
|---|
| 284 | addiu a0, a0, 4 |
|---|
| 285 | bnez a2, 1b |
|---|
| 286 | addiu a1, a1, 4 |
|---|
| 287 | |
|---|
| 288 | jr ra |
|---|
| 289 | nop |
|---|
| 290 | |
|---|
| 291 | END(aligned_copy) |
|---|
| 292 | |
|---|
| 293 | #include "uart.s" |
|---|
| 294 | #include "chip.s" |
|---|
| 295 | #include "cache_lib.s" |
|---|
| 296 | #if !defined(MEMSYSINIT) |
|---|
| 297 | #include "memc_0_ddr_init.s" |
|---|
| 298 | #endif |
|---|
| 299 | #undef SHMOO_STACK_START |
|---|
| 300 | #include "run_shmoo.s" |
|---|
| 301 | #if defined(BOOT_SCRAMBLE_DRAM) |
|---|
| 302 | #include "scramble.s" |
|---|
| 303 | #endif |
|---|
| 304 | #define delay_loop dl1 |
|---|
| 305 | #include "hide_rom.s" |
|---|
| 306 | #include "bsp_util.s" |
|---|
| 307 | #include "mips_libs.s" |
|---|
