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bls2.S @ 2

Last change on this file since 2 was 2, checked in by phkim, 11 years ago

1.phkim

revision copy newcon3sk r27

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1	/*************************************************************************
2	** Broadcom Corp. Confidential
3	** Copyright 2011 Broadcom Corp. All Rights Reserved.
4	**
5	** THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
6	** AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
7	** EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
8	**
9	** File: bls2.S
10	** Description: low level board dependent startup code stage 2
11	** Created: alexp
12	**
13	** REVISION:
14	**
15	***************************************************************************/
16
17	#include "bmips3300.h"
18	#include "bchp_common.h"
19	#include "bchp_sun_top_ctrl.h"
20	#include "bchp_aon_ctrl.h"
21	#include "bchp_aon_pm_l2.h"
22	#include "bchp_kbd1.h"
23	/* for power button */
24	#include "bchp_gio_aon.h"
25
26	#define BCHP_REG_BASE PHYS_TO_K1(BCHP_PHYSICAL_OFFSET)
27
28	#if (USERIO_ID==1)
29	#define IR_WAKEUP_CODE_MASK 0x0000FF00
30	#define IR_WAKEUP_CODE 0x00000F00
31	#elif (USERIO_ID==8)
32	#define IR_WAKEUP_CODE_MASK 0x000000FF
33	#define IR_WAKEUP_CODE 0x0000000A
34	#elif (USERIO_ID==12) /ACM612 XXX-XXXX /
35	#define IR_WAKEUP_CODE_MASK 0x000000FF
36	#define IR_WAKEUP_CODE 0x000000C4
37	#elif (USERIO_ID==11) /ACM612 ZRC-4502 /
38	#define IR_WAKEUP_CODE_MASK 0x000000FF
39	#define IR_WAKEUP_CODE 0x000000E7
40	#elif (USERIO_ID==10) /ACM612 MK 35 /
41	#define IR_WAKEUP_CODE_MASK 0x000000FF
42	#define IR_WAKEUP_CODE 0x0000003F
43	#elif (USERIO_ID==5) /ACM612 RCA /
44	#define IR_WAKEUP_CODE_MASK 0x007000FF
45	#define IR_WAKEUP_CODE 0x007000d5
46	#elif (USERIO_ID==4) /ACM612 ARC xxx /
47	#define IR_WAKEUP_CODE_MASK 0x000000FF
48	#define IR_WAKEUP_CODE 0x00000047
49	#elif (USERIO_ID==15) /* DST IR */
50	#define IR_WAKEUP_CODE_MASK 0x0000FFFF
51	#define IR_WAKEUP_CODE 0x000000FF
52	#else
53	#define IR_WAKEUP_CODE_MASK 0x00FF0000
54	#define IR_WAKEUP_CODE 0x000A0000
55	#endif
56
57
58	#define SR_BEV_0 ((CP0_STATUS_SR_MASK \| CP0_STATUS_CU0_MASK \| CP0_STATUS_CU1_MASK \| CP0_STATUS_IE_MASK) & ~( CP0_STATUS_BEV_MASK \| CP0_STATUS_ERL_MASK \| CP0_STATUS_EXL_MASK))
59	.equ S2_STACK_SIZE, 0x1000
60	.lcomm s2_stack, S2_STACK_SIZE
61	.local __jump_to_cache
62	.extern stage2_main
63	.globl __start_s2
64	.set noreorder
65	.func __start_s2
66	__start_s2:
67
68	bal clear_all_d_cache
69	nop
70
71	bal init_mips
72	nop
73
74	bal _writeasm
75	li a0, 'C'
76	1:
77	/* relocate exception handlers */
78	la t0, exception_handlers
79	la t1, 0x80000000
80	la t2, exception_handlers_end
81	subu t2, t2, t0
82	1:
83	lw a0, 0(t0)
84	sw a0, 0(t1)
85	addi t0, t0, 4
86	addi t1, t1, 4
87	sub t2, t2, 4
88	bnez t2, 1b
89	nop
90	/* flush d cache */
91	bal clear_all_d_cache
92	nop
93	/* invalidate i cache */
94	bal invalidate_all_i_cache
95	nop
96
97	la t0, __jump_to_cache
98	j t0
99	nop
100	__jump_to_cache:
101	/* switch to exception vectors in ddr */
102	li t0, SR_BEV_0
103	mtc0 t0, CP0_STATUS
104	nop
105	nop
106	/* clear bss */
107	la a0,_fbss
108	la a1,_end
109	subu a1,a1,a0
110
111	beqz a1, 2f
112	nop
113	1:
114	sw zero,0(a0)
115	sub a1, a1, 4
116	addi a0, a0, 4
117	bnez a1, 1b
118	nop
119	2:
120	#ifdef CONFIG_STANDBY
121	/* if just power on the box first time, enter standby mode instead boot up directly */
122	.extern cir_configure /* implemented in cir.c */
123	/* cir_configure */
124	bal _writeasm
125	li a0, '>'
126
127	/* set IRR cmd accordingly and configure CIR if needed */
128	li a0,USERIO_ID
129	jal cir_configure
130	nop
131
132	#li a0,(BCHP_REG_BASE\|BCHP_AON_CTRL_RESET_HISTORY)
133	#lw v0,0(a0)
134	#li v1,BCHP_AON_CTRL_RESET_HISTORY_s3_wakeup_reset_MASK
135	#and v0,v0,v1
136	#beqz v0,ir_power_off
137	b check_ir
138	nop
139
140	check_ir:
141	li a0,(BCHP_REG_BASE\|BCHP_AON_PM_L2_CPU_STATUS)
142	lw v0,0(a0)
143	li v1,BCHP_AON_PM_L2_CPU_STATUS_IRR_INTR_MASK
144	and v0,v0,v1
145	bne v0,v1,ir_done
146	nop
147
148	li a0,(BCHP_REG_BASE\|BCHP_KBD1_DATA0)
149	lw t8,0(a0)
150	li t9,IR_WAKEUP_CODE_MASK
151	and t8,t8,t9
152
153	li t7,IR_WAKEUP_CODE
154	beq t8,t7,ir_done
155	nop
156
157	# power button is pressed?
158	li a0,(BCHP_REG_BASE\|BCHP_GIO_AON_DATA_LO)
159	lw v0,0(a0)
160	li v1,0x80
161	and v0,v0,v1
162	beqz v0,ir_done
163	nop
164
165	ir_power_off:
166	/* clear interrupt */
167	li a0,(BCHP_REG_BASE\|BCHP_KBD1_STATUS)
168	sw zero,0(a0)
169
170	/* clear reset history */
171	li a0,(BCHP_REG_BASE\|BCHP_AON_CTRL_RESET_CTRL)
172	sw zero,0(a0)
173	li a1,BCHP_AON_CTRL_RESET_CTRL_clear_reset_history_MASK
174	sw a1,0(a0)
175
176	/* set fast power down mode, pm_start_pwrdn should be 0->1 transition to initiate power down */
177	li a0,(BCHP_REG_BASE\|BCHP_AON_PM_L2_CPU_MASK_SET)
178	li a1,0xFFFFFFFF
179	sw a1,0(a0)
180
181	li a0,(BCHP_REG_BASE\|BCHP_AON_PM_L2_CPU_MASK_SET)
182	li a1,0xFFFFFFFF
183	sw a1,0(a0)
184
185	# just allow the power button to generate wake up interrupt, Agpio07
186	li a0,(BCHP_REG_BASE\|BCHP_GIO_AON_MASK_LO)
187	li a1,0x00000080
188	sw a1,0(a0)
189
190	li a0,(BCHP_REG_BASE\|BCHP_GIO_AON_MASK_EXT)
191	li a1,0x0
192	sw a1,0(a0)
193
194	li a0,(BCHP_REG_BASE\|BCHP_AON_PM_L2_CPU_MASK_CLEAR)
195	# for ACB612
196	li a1,(BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK \| BCHP_AON_PM_L2_CPU_MASK_CLEAR_GPIO_MASK)
197	#li a1,BCHP_AON_PM_L2_CPU_MASK_CLEAR_IRR_INTR_MASK
198	sw a1,0(a0)
199	li a0,(BCHP_REG_BASE\|BCHP_AON_CTRL_PM_FAST_PWRDN_PRECHARGE)
200	li a1,0xB9E1DC
201	sw a1,0(a0)
202	li a0,(BCHP_REG_BASE\|BCHP_AON_CTRL_PM_CTRL)
203	sw zero,0(a0)
204	li a1,(BCHP_AON_CTRL_PM_CTRL_pm_deep_standby_MASK\|BCHP_AON_CTRL_PM_CTRL_pm_fast_power_down_MASK)
205	sw a1,0(a0)
206	nop
207	nop
208	nop
209	or a1,a1,BCHP_AON_CTRL_PM_CTRL_pm_start_pwrdn_MASK
210	sw a1,0(a0)
211
212	nop
213	nop
214	nop
215	nop
216	nop
217	nop
218	b ir_power_off
219	nop
220	#endif
221	ir_done:
222	/* flush cache one more time as CFE does it */
223	bal clear_all_d_cache
224	nop
225
226	la sp, s2_stack + S2_STACK_SIZE - 24
227	jal stage2_main
228	move a0, zero
229	1:
230	b 1b
231	nop
232	.endfunc
233
234	LEAF(aligned_copy)
235
236	1:
237	lw v0, 0(a0)
238	addiu a2, a2, -4
239	sw v0, 0(a1)
240	addiu a0, a0, 4
241	bnez a2, 1b
242	addiu a1, a1, 4
243
244	jr ra
245	nop
246
247	END(aligned_copy)
248
249	LEAF(exception_handlers)
250
251	1:
252	b 1b
253	nop
254	nop
255	nop
256	.skip 0x170
257	1:
258	b 1b
259	nop
260	nop
261	nop
262	exception_handlers_end:
263
264	END(exception_handlers)
265	#include "uart.s"
266	#include "mips_libs.s"
267	#include "cache_lib.s"

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