source: svn/trunk/newcon3bcm2_21bu/dta/src/bootloader7574/bootloader2.mk

Last change on this file was 2, checked in by phkim, 11 years ago

1.phkim

  1. revision copy newcon3sk r27
  • Property svn:executable set to *
File size: 7.4 KB
Line 
1# WARNING: For multi stage bootloader to compile makefile must run from the
2# bootloader directory otherwise it will not link! Please take this in to
3# consideration when modifying this makefile and build process.
4
5# Bootloader with MemsysInitLib support.
6# Older shmoo variants are supported by the bootloader.mk. Only MemsysInitLib
7# supported by this makefile.
8
9# Project Root Directory
10PROOT := $(shell cd ../../../ ; /bin/pwd)
11
12DEBUG ?= y
13
14# we always have to build at least 2 stage bootloader. MULTI_STAGE flag
15# is no longer applicable
16
17BLD_TARGET = bootloader
18
19# Dram scrambling test option. A0/A1 Multistage bootloader only.
20ENABLE_BOOT_SCRAMBLE_DRAM ?= n
21
22# complie in BSP firmware
23ENABLE_BSEC=n
24
25# AVS support, default is y, but can disable for someboard which doesn't have AVS circuitry
26ENABLE_AVS ?=y
27
28include $(PROOT)/dta/build/platform.inc
29
30MAGNUM = $(PROOT)/magnum
31BSP = $(PROOT)/rockford/bsp
32LIBDIR = $(PROOT)/dta/lib
33DTADIR = $(PROOT)/dta
34BLDDIR = $(PROOT)/dta/src/bootloader7574
35
36CFLAGS += -ffunction-sections
37
38CFLAGS += -DBCHP_CHIP=$(BCHP_CHIP) -DBCHP_VER=BCHP_VER_$(BCHP_VER)
39CFLAGS += -DBSTD_CPU_ENDIAN=BSTD_ENDIAN_LITTLE
40
41CFLAGS += -DMEMSYSINIT=1
42ifeq ($(ENABLE_AVS),y)
43CFLAGS += -DAVS_ENABLE=1
44endif
45
46ifeq ($(ENABLE_BOOT_SCRAMBLE_DRAM),y)
47CFLAGS += -DBOOT_SCRAMBLE_DRAM=1
48endif
49
50# start MEMC configuration profiles and related variables
51CFG_MCB0_OFFSET ?= 2176 #0x880
52CFG_MEMC_0_DEV_PROFILE ?= DEFAULT
53CFG_PROFILE ?= 1
54ifeq ($(strip ${CFG_PROFILE}),1)
55        CFG_MEMC_0_FREQ ?= 533
56        CFLAGS += -DPROFILE=1
57        CFLAGS += -DCPU_MDIV=8
58        CFLAGS += -DAVD_MDIV=15
59        CFLAGS += -DAVD_CPU_MDIV=15
60        CFLAGS += -DDSP_MDIV=15
61        CFLAGS += -DSCB_MDIV=12
62        CFLAGS += -DMEMC_0_DDR_FREQ=533
63        ifeq ($(strip ${CFG_MEMC_0_DEV_PROFILE}),DEFAULT)
64                PROFILE_NAME = 1066G
65        else
66                PROFILE_NAME = 1066${CFG_MEMC_0_DEV_PROFILE}
67        endif
68endif   
69ifeq ($(strip ${CFG_PROFILE}),2)
70        CFG_MEMC_0_FREQ ?= 800
71        CFLAGS += -DPROFILE=2
72        CFLAGS += -DCPU_MDIV=6
73        CFLAGS += -DAVD_MDIV=12
74        CFLAGS += -DAVD_CPU_MDIV=12
75        CFLAGS += -DDSP_MDIV=8
76        CFLAGS += -DSCB_MDIV=12
77        CFLAGS += -DMEMC_0_DDR_FREQ=800
78        ifeq ($(strip ${CFG_MEMC_0_DEV_PROFILE}),DEFAULT)
79                PROFILE_NAME = 1600K
80        else
81                PROFILE_NAME = 1600${CFG_MEMC_0_DEV_PROFILE}
82        endif
83endif   
84ifeq ($(strip ${CFG_PROFILE}),3)
85        CFG_MEMC_0_FREQ ?= 933
86        CFLAGS += -DPROFILE=3
87        CFLAGS += -DCPU_MDIV=5
88        CFLAGS += -DAVD_MDIV=10
89        CFLAGS += -DAVD_CPU_MDIV=8
90        CFLAGS += -DDSP_MDIV=8
91        CFLAGS += -DSCB_MDIV=11
92        ifeq ($(strip ${CFG_MEMC_0_FREQ}),833)
93        CFLAGS += -DMEMC_0_DDR_FREQ=833
94        endif
95        ifeq ($(strip ${CFG_MEMC_0_FREQ}),866)
96        CFLAGS += -DMEMC_0_DDR_FREQ=866
97        endif
98        ifeq ($(strip ${CFG_MEMC_0_FREQ}),900)
99        CFLAGS += -DMEMC_0_DDR_FREQ=900
100        endif
101        ifeq ($(strip ${CFG_MEMC_0_FREQ}),933)
102        CFLAGS += -DMEMC_0_DDR_FREQ=933
103        endif
104        ifeq ($(strip ${CFG_MEMC_0_DEV_PROFILE}),DEFAULT)
105                PROFILE_NAME = 1866M
106        else
107                PROFILE_NAME = 1866${CFG_MEMC_0_DEV_PROFILE}
108        endif
109endif   
110ifeq ($(strip ${CFG_PROFILE}),4)
111        CFG_MEMC_0_FREQ ?= 933
112        CFLAGS += -DPROFILE=4
113        CFLAGS += -DCPU_MDIV=4
114        CFLAGS += -DAVD_MDIV=9
115        CFLAGS += -DAVD_CPU_MDIV=7
116        CFLAGS += -DDSP_MDIV=6
117        CFLAGS += -DSCB_MDIV=9
118        ifeq ($(strip ${CFG_MEMC_0_FREQ}),833)
119        CFLAGS += -DMEMC_0_DDR_FREQ=833
120        endif
121        ifeq ($(strip ${CFG_MEMC_0_FREQ}),866)
122        CFLAGS += -DMEMC_0_DDR_FREQ=866
123        endif
124        ifeq ($(strip ${CFG_MEMC_0_FREQ}),900)
125        CFLAGS += -DMEMC_0_DDR_FREQ=900
126        endif
127        ifeq ($(strip ${CFG_MEMC_0_FREQ}),933)
128        CFLAGS += -DMEMC_0_DDR_FREQ=933
129        endif
130        ifeq ($(strip ${CFG_MEMC_0_DEV_PROFILE}),DEFAULT)
131                PROFILE_NAME = 1866M
132        else
133                PROFILE_NAME = 1866${CFG_MEMC_0_DEV_PROFILE}
134        endif
135endif   
136ifeq ($(strip ${CFG_PROFILE}),5)
137        CFG_MEMC_0_FREQ ?= 1067
138        CFLAGS += -DPROFILE=5
139        CFLAGS += -DCPU_MDIV=5
140        CFLAGS += -DAVD_MDIV=10
141        CFLAGS += -DAVD_CPU_MDIV=8
142        CFLAGS += -DDSP_MDIV=8
143        CFLAGS += -DSCB_MDIV=9
144        ifeq ($(strip ${CFG_MEMC_0_FREQ}),966)
145        CFLAGS += -DMEMC_0_DDR_FREQ=966
146        endif
147        ifeq ($(strip ${CFG_MEMC_0_FREQ}),1000)
148        CFLAGS += -DMEMC_0_DDR_FREQ=1000
149        endif
150        ifeq ($(strip ${CFG_MEMC_0_FREQ}),1033)
151        CFLAGS += -DMEMC_0_DDR_FREQ=1033
152        endif
153        ifeq ($(strip ${CFG_MEMC_0_FREQ}),1067)
154        CFLAGS += -DMEMC_0_DDR_FREQ=1067
155        endif
156        PROFILE_NAME = 2133N
157endif   
158ifeq ($(strip ${CFG_PROFILE}),6)
159        CFG_MEMC_0_FREQ ?= 667
160        CFLAGS += -DPROFILE=6
161        CFLAGS += -DCPU_MDIV=5
162        CFLAGS += -DAVD_MDIV=10
163        CFLAGS += -DAVD_CPU_MDIV=8
164        CFLAGS += -DDSP_MDIV=8
165        CFLAGS += -DSCB_MDIV=12
166        CFLAGS += -DMEMC_0_DDR_FREQ=667
167        ifeq ($(strip ${CFG_MEMC_0_DEV_PROFILE}),DEFAULT)
168                PROFILE_NAME = 1333H
169        else
170                PROFILE_NAME = 1333${CFG_MEMC_0_DEV_PROFILE}
171        endif
172endif   
173
174# Following defines are common for both memc0 and memc 1
175CFG_MEMC_0_DEV_TECH ?= 2G
176CFG_MEMC_0_DEV_WIDTH ?= 8
177CFG_MEMC_0_DDR_WIDTH ?= 16
178
179ifeq ($(strip ${CFG_MEMC_0_DDR_WIDTH}),16)
180        CFLAGS += -DMEMC_0_DDR_WIDTH=MEMC_DDR_16BIT
181else
182        CFLAGS += -DMEMC_0_DDR_WIDTH=MEMC_DDR_32BIT
183endif
184CFLAGS += -DMCB0_OFFSET=$(CFG_MCB0_OFFSET)
185# end MEMC configuration profiles and related variables
186
187
188CFLAGS += -I$(MAGNUM)/basemodules/chp/$(BCHP_CHIP)/rdb/$(BCHP_VER_LOWER) \
189        -I$(MAGNUM)/basemodules/chp \
190        -I$(MAGNUM)/basemodules/std \
191        -I$(MAGNUM)/basemodules/std/config \
192        -I$(MAGNUM)/basemodules/std/types/ucos_ii \
193        -I$(MAGNUM)/basemodules/err \
194        -I$(MAGNUM)/basemodules/dbg \
195        -I$(MAGNUM)/basemodules/reg \
196        -I$(MAGNUM)/commonutils/lst \
197
198CFLAGS += -I$(BSP)/bcm9$(BCHP_CHIP)/no-os/src/sde \
199        -I$(BSP)/Shmoo/$(BCHP_CHIP)/memsysinitlib/include \
200        -I$(BSP)/Shmoo/$(BCHP_CHIP)/memsysinitlib/src
201
202CFLAGS += -I$(DTADIR)/src -I$(DTADIR)/src/z
203
204ifeq ($(HAS_STANDBY),y)
205CFLAGS += -DCONFIG_STANDBY -DUSERIO_ID=$(USERIO_ID)
206endif
207
208ifneq ($(DEBUG),y)
209OBJTYPE := _prod
210LIBTYPE := _production
211endif
212
213S1_SRC := bls1.S shmoosupport.S
214
215ifeq ($(ENABLE_AVS),y)
216AVSDIR := $(BSP)/AVS
217S1_SRC += $(AVSDIR)/src/avs_start.c
218CFLAGS += -I$(AVSDIR)/include -I$(BLDDIR)
219SHMOO_LIB += $(AVSDIR)/$(BCHP_CHIP)/avs_lib_le$(OBJTYPE).pof
220endif
221
222SHMOO_LIB += $(BSP)/Shmoo/ddr40phy/build/memsysinitlib_2p2bld1_16bphy$(LIBTYPE)_le.a
223MCB_DIR = $(BSP)/Shmoo/ddr40phy/$(BCHP_CHIP)
224MCB_FILE = $(BCHP_CHIP)_$(CFG_MEMC_0_FREQ)MHz_${CFG_MEMC_0_DDR_WIDTH}b_dev${CFG_MEMC_0_DEV_TECH}x${CFG_MEMC_0_DEV_WIDTH}_DDR3_$(PROFILE_NAME)_le.mcb
225
226XMODEM_SRC := $(DTADIR)/src/xmodem.c
227Z_SRC := $(DTADIR)/src/z/adler32.c \
228        $(DTADIR)/src/z/crc32.c \
229        $(DTADIR)/src/z/inffast.c \
230        $(DTADIR)/src/z/inflate.c \
231        $(DTADIR)/src/z/inftrees.c \
232        $(DTADIR)/src/z/zutil.c
233
234BLD_SRC := bls2.S stage2.c clocks.c fast_heap.c $(XMODEM_SRC) $(Z_SRC)
235
236ifeq (${HAS_STANDBY},y)
237BLD_SRC += cir.c
238endif
239
240S1_OBJ :=  $(subst .S,.o,$(filter %.S, $(S1_SRC))) $(subst .c,.o, $(filter %.c, $(S1_SRC)))
241
242BLD_OBJ := $(patsubst %.S,%.o,$(filter %.S,$(BLD_SRC))) $(patsubst %.s,%.o,$(filter %.s,$(BLD_SRC)))  $(patsubst %.c,%.o,$(filter %.c,$(BLD_SRC)))
243
244BLD_DEP := $(patsubst %.o,%.d,$(filter %.o,$(BLD_OBJ))) 
245
246LDFLAGS += -T $(BLDDIR)/bootloader2s.script --gc-sections
247
248ifeq ($(ENABLE_BSEC),y)
249BSEC_OBJ = key0data.o bsec_053_hddta.o
250endif
251
252CFLAGS := $(filter-out -nostdinc,$(CFLAGS))
253
254all : $(BLD_TARGET).bin
255
256$(BLD_TARGET).bin : $(BLD_TARGET).elf
257        $(OBJCOPY) -S -O binary $< $@
258        dd if=$(MCB_DIR)/$(MCB_FILE) of=$@ bs=1 seek=$(CFG_MCB0_OFFSET) conv=notrunc || rm $@
259
260$(BLD_TARGET).elf : $(BLD_TARGET)_s1l.o  $(BSEC_OBJ) $(BLD_TARGET).o
261        $(LD) -Map $(basename $@).map $(LDFLAGS) $^ $(LDLIBS) -o $@
262
263clean : $(BLD_TARGET)_clean
264
265$(BLD_TARGET)_clean:
266        $(RM) -f $(BLD_TARGET).elf $(BLD_TARGET).bin $(BLD_TARGET).map $(BLD_OBJ) $(BLD_DEP) $(S1_OBJ) $(BLD_TARGET)_s1.o $(BLD_TARGET)_s1l.o $(BLD_TARGET).o
267
268$(BLD_TARGET)_s1.o : $(S1_OBJ) $(SHMOO_LIB)
269        $(LD) -r $(LFLAGS) $^ -o $@
270
271$(BLD_TARGET)_s1l.o : $(BLD_TARGET)_s1.o
272        $(OBJCOPY) -w -G __start -G key1 $^ $@
273
274$(BLD_TARGET).o : $(BLD_OBJ)
275        $(LD) -r $(LFLAGS) $^ -o $@
276
277-include $(BLD_DEP)
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