/***************************************************************************
 *     Copyright (c) 2003-2010, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *  THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 *  AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 *  EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * $brcm_Workfile: $
 * $brcm_Revision: $
 * $brcm_Date: $
 *
 * Module Description:
 *
 * Revision History:
 *
 * $brcm_Log: $
 * 
 *
 ***************************************************************************/
#include "bstd.h"
#include "berr.h"
#include "bdbg.h"
#include "bkni.h"
#if (BCHP_CHIP==7552) /* [JPF] */
#include "bchp_7552.h"
#include "bchp_common.h"
#include "bint_7552.h"
#include "bchp_sun_top_ctrl.h"
#include "bchp_aon_pin_ctrl.h"
#else
#include "bchp_7550.h"
#include "bchp_common.h"
#include "bint_7550.h"
#include "btnr_7550.h"
#include "brap.h"
#include "brap_img.h"
#endif

#if (CONFIG_ENABLE_SCM == 1)
#include "scm_low.h"
#endif
#include "gist.h"
#include "bcm_mips_defs.h"

#if (BCHP_CHIP!=7552) /* [JPF] */
#include "bchp_ds_eq.h"
#include "bchp_ds_pll.h"
#include "bchp_ds_qafe_if_0.h"
#include "bchp_ds_qdsafe_0.h"
#include "bchp_ds_tuner_anactl.h"
#include "bchp_ds_tuner.h"
#include "bchp_ds.h"
#include "bchp_ds_tuner_ref.h"
#include "bchp_clk.h"
#include "bchp_vcxo_ctl_config_fsm.h"
#include "bchp_vcxo_ctl_misc.h"
#include "bchp_memc_ddr23_aphy_ac_0.h"
#endif
#include "bchp_gio.h"
#include "bchp_hif_cpu_intr1.h"
#include "bchp_genet_0_ext.h"
#include "bchp_clkgen.h"

/* includes for HD DTA POWER CONFIGURATION */

#include "bchp_misc.h"
#include "bchp_usb_ctrl.h"
#include "bchp_aio_misc.h"
#include "bchp_sun_top_ctrl.h"
#include "cache_util.h"

#ifdef CONFIG_MRC
/* memory checker */
#include "bmrc.h"
#include "bmrc_monitor.h"
BMRC_Handle	mrc_handle;
BMRC_Monitor_Handle	mrc_monitor_handle;
#endif

#if	defined(ACB612) || defined(ACB615)
#include "bos.h"
#include "bchp_misc.h"
#include "bchp_ufe_afe.h"
#include "bchp_ds.h"
#ifdef OOB_TUNER_SUPPORT
#include "bchp_obadc.h"
#include "bchp_oob.h"
#endif
#include "bchp_sdadc.h"
#if 0
#include "bchp_hdmi_tx_phy.h"
#endif
static void gist_power_down_modules(BREG_Handle hReg);
#endif
#include "bchp_memc_arb_0.h"

BDBG_MODULE(gist);		/* Register software module with debug interface */
#ifdef BRAP /* [JPF] */
BRAP_AssociatedChanSettings     sDecodeAssChSettings;
BRAP_AssociatedChanSettings     sCompresseAssChSettings;
BRAP_DestinationHandle          s_hMaiDstHandle = NULL;
BRAP_DestinationHandle          s_hDacDstHandle = NULL;
BRAP_DestinationHandle          s_hSpdifDstHandle = NULL;
BRAP_ProcessingStageHandle	 	s_hBtscStageHandle = NULL;
void boutput_add_postprocessing(BRAP_ChannelHandle hRapCh);

void set_fm_deviation_value(int value);
#endif
void gist_flush_cache(const void *addr, size_t num);
static void gist_power_down_eth(BREG_Handle hReg);
#ifdef CONFIG_VSB
static void gist_config_vsb(BREG_Handle hReg);
#endif


#if (BCHP_CHIP==7552) /* [JPF] */
#ifdef ACB612	/* RLQ */

#ifdef CONFIG_AOV_SDRAM_1G/*128*/
//#define DEVICE_MEM_SIZE (111*1024*1024)	/* changed from 0x7600000 */
#define DEVICE_MEM_SIZE (90*1024*1024)	// 111MB->90MB   megakiss  
#else/*256*/
#define DEVICE_MEM_SIZE 0xD000000
#endif


#else
/* 256 MB DDR */
#define DEVICE_MEM_BASE 0x2000000
#define DEVICE_MEM_SIZE 0xD000000
#endif
#else
/* Defines for device heap. These may be better placed somewhere else later.
   Heap start at 10MB and goes to 128MB. This ONLY works on 128MB board */
#define DEVICE_MEM_BASE 0xa00000
#define DEVICE_MEM_SIZE 0x6200000
#endif
void *g_heap_ptr = NULL;
struct bhandle_store_t g_handles;

static BERR_Code NEXUS_Platform_P_InitPinmux(BREG_Handle hReg);
static uint32_t s_L1Mask[BINT_MAX_INTC_SIZE] = { 0,0,0,0};
#define NUM_L1_STATUS	((BCHP_HIF_CPU_INTR1_INTR_W2_STATUS - BCHP_HIF_CPU_INTR1_INTR_W0_STATUS)/4)

void bint_handler(void)
{
	int i;
	uint32_t bit,status,mask_status;
	for (i = 0; i <= NUM_L1_STATUS; ++i)
	{
		for (bit = 0; bit < 32; ++bit)
		{
			status = BREG_Read32(GetREG(),BCHP_HIF_CPU_INTR1_INTR_W0_STATUS + (i * 4));
			mask_status = BREG_Read32(GetREG(),BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS + (i * 4));
			if ((1UL << bit) & status & ~mask_status)
			{
				if (s_L1Mask[i]  & (1UL << bit))
				{
					BDBG_MSG(("%s:%d(%d,%d)\n",__FUNCTION__,__LINE__,i,bit));
	
					BINT_Isr(GetINT(),bit + (i * 32));
				}
				else
				{
//RLQ
#if 0
#ifdef ACB612
void CPUINT1_Isr_ex(int bit);
					if (BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT == bit && ((1UL << bit) & status)) {
						CPUINT1_Isr_ex(bit);
					}	
					else
#endif
#endif
					BDBG_ERR(("%s:%d(%d,%d)-NOT HANDLED\n",__FUNCTION__,__LINE__,i,bit));
				}
			}
		}
	}
}
#ifdef BRAP /* [JPF] */
/* Configure HDMI output port */
static void boutput_configure_hdmi_port(BRAP_Handle hRap, 
										BRAP_OutputPort port)
{
	BERR_Code errCode;
	BRAP_OutputPortConfig outputSettings;

	errCode = BRAP_GetDefaultOutputConfig(hRap, port, &outputSettings);
	BDBG_ASSERT(BERR_SUCCESS == errCode);
	/* Fill up output settings */
	outputSettings.eOutputPort = port;
	outputSettings.bCompressed = false;
	outputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
	outputSettings.uiOutputBitsPerSample = 24;
	outputSettings.uOutputPortSettings.sMaiMultiSettings.eMClkRate = BRAP_OP_MClkRate_e256Fs;
	errCode = BRAP_SetOutputConfig(hRap, &outputSettings);
	/* This should never fail */
	BDBG_ASSERT(BERR_SUCCESS == errCode);
}
/* Add output destinations for the decode association */
static void boutput_config_decode_outputs(void)
{
	BERR_Code err;
	BRAP_OutputPortDetails      sOpDetails;
	BRAP_OutputPortConfig sOutputSettings;
    BRAP_DstDetails             sDstDetails;
	int i;

	if (s_hDacDstHandle)
	{
		BRAP_RemoveDestination(g_handles.hDecodeAssociatedCh,s_hDacDstHandle);
	}
	if (s_hMaiDstHandle)
	{
		BRAP_RemoveDestination(g_handles.hDecodeAssociatedCh,s_hMaiDstHandle);
	}
	if (s_hSpdifDstHandle)
	{
		BRAP_RemoveDestination(g_handles.hDecodeAssociatedCh,s_hSpdifDstHandle);
	}
	
	for (i=0; i<BRAP_OutputChannelPair_eMax; i++)
	{
		sOpDetails.eOutput[i] = BRAP_OutputPort_eMax;
	}

	sOpDetails.eOutput[0] = BRAP_OutputPort_eDac0;
	sOpDetails.eAudioMode =BRAP_OutputMode_e2_0;
	sOpDetails.bLfeOn = false;
	sOpDetails.bDownmixedOpPort = false;

	err = BRAP_GetCurrentOutputConfig(GetRAP(), BRAP_OutputPort_eDac0, &sOutputSettings);
	if (err != BERR_SUCCESS)
	{
		BDBG_ERR(("Get Current Settings for DAC0 Output failed %d",err));
		return;
	}
	BDBG_MSG(("Default settings received for DAC0 Output"));

	/* Fill up output settings */
	sOutputSettings.eOutputPort = BRAP_OutputPort_eDac0;
	sOutputSettings.bCompressed = false;
	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
	//sOutputSettings.iDelay = 20;

	/* Configure output port */       
	err = BRAP_SetOutputConfig(GetRAP(), &sOutputSettings);
	if (err != BERR_SUCCESS)
	{
		BDBG_MSG(("Set DAC0 output configuration failed %d", err));
		return;
	}
	BDBG_ERR(("Set DAC0 output configuration done"));

	sDstDetails.eAudioDst = BRAP_AudioDst_eOutputPort;
	sDstDetails.uDstDetails.sOpDetails = sOpDetails;

	err = BRAP_AddDestination(g_handles.hDecodeAssociatedCh, &sDstDetails, &s_hDacDstHandle); 
	BDBG_ASSERT (BERR_SUCCESS == err);


	sOpDetails.eOutput[0] = BRAP_OutputPort_eMai;
	sOpDetails.eAudioMode =BRAP_OutputMode_e2_0;
	sOpDetails.bLfeOn = false;
	sOpDetails.bDownmixedOpPort = false;

	err = BRAP_GetCurrentOutputConfig(GetRAP(), BRAP_OutputPort_eMai, &sOutputSettings);
	if (err != BERR_SUCCESS)
	{
		BDBG_ERR(("Get Current Settings for HDMI Output failed %d",err));
		return;
	}
	BDBG_MSG(("Default settings received for HDMI Output"));

	/* Fill up output settings */
	sOutputSettings.eOutputPort = BRAP_OutputPort_eMai;
	sOutputSettings.bCompressed = false;
	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
	
	//sOutputSettings.iDelay = 20;
	err = BRAP_SetOutputConfig(GetRAP(), &sOutputSettings);
	if (err != BERR_SUCCESS)
	{
		BDBG_MSG(("Set HDMI output configuration failed %d", err));
		return;
	}
	BDBG_ERR(("Set HDMI output configuration done"));

	sDstDetails.eAudioDst = BRAP_AudioDst_eOutputPort;
	sDstDetails.uDstDetails.sOpDetails = sOpDetails;
#if 1
	err = BRAP_AddDestination(g_handles.hDecodeAssociatedCh, &sDstDetails, &s_hMaiDstHandle); 
	BDBG_ASSERT (BERR_SUCCESS == err);
#endif
	sOpDetails.eOutput[0] = BRAP_OutputPort_eSpdif;
	sOpDetails.eAudioMode =BRAP_OutputMode_e2_0;
	sOpDetails.bLfeOn = false;
	sOpDetails.bDownmixedOpPort = false;

	err = BRAP_GetCurrentOutputConfig(GetRAP(), BRAP_OutputPort_eSpdif, &sOutputSettings);
	if (err != BERR_SUCCESS)
	{
		BDBG_ERR(("Get Current Settings for SPDIF Output failed %d",err));
		return;
	}
	BDBG_MSG(("Default settings received for SPDIF Output"));

	/* Fill up output settings */
	sOutputSettings.eOutputPort = BRAP_OutputPort_eSpdif;
	sOutputSettings.bCompressed = false;
	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
	
	//sOutputSettings.iDelay = 20;
	err = BRAP_SetOutputConfig(GetRAP(), &sOutputSettings);
	if (err != BERR_SUCCESS)
	{
		BDBG_MSG(("Set HDMI output configuration failed %d", err));
		return;
	}
	BDBG_ERR(("Set SPDIF output configuration done (%d)", __LINE__));

	sDstDetails.eAudioDst = BRAP_AudioDst_eOutputPort;
	sDstDetails.uDstDetails.sOpDetails = sOpDetails;
#if 0
	err = BRAP_AddDestination(g_handles.hDecodeAssociatedCh, &sDstDetails, &s_hSpdifDstHandle); 
	BDBG_ASSERT (BERR_SUCCESS == err);
#endif
}

static void boutput_config_compress_outputs(void)
{
	BERR_Code err;
	BRAP_OutputPortDetails	sOpDetails;
	BRAP_OutputPortConfig	sOutputSettings;
	BRAP_DstDetails			sDstDetails;
	int i;
#if 0
	if (s_hMaiDstHandle)
	{
		BRAP_RemoveDestination(g_handles.hCompressedAssociatedCh, s_hMaiDstHandle);
	}
#endif
	for (i=0; i<BRAP_OutputChannelPair_eMax; i++)
	{
		sOpDetails.eOutput[i] = BRAP_OutputPort_eMax;
	}

	sOpDetails.eOutput[0] = BRAP_OutputPort_eMai;
	sOpDetails.eAudioMode = BRAP_OutputMode_e2_0; // don't care for compression
	sOpDetails.bLfeOn = false;
	sOpDetails.bDownmixedOpPort = false;

	err = BRAP_GetCurrentOutputConfig(GetRAP(), BRAP_OutputPort_eMai, &sOutputSettings);
	if (err != BERR_SUCCESS)
	{
		BDBG_ERR(("Get Current Settings for HDMI Output failed %d (%d)", err, __LINE__));
		return;
	}
	BDBG_MSG(("Default settings received for HDMI Output"));

	/* Fill up output settings */
	sOutputSettings.eOutputPort = BRAP_OutputPort_eMai;
	sOutputSettings.bCompressed = true;
	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;

	err = BRAP_SetOutputConfig(GetRAP(), &sOutputSettings);
	if (err != BERR_SUCCESS)
	{
		BDBG_MSG(("Set HDMI output configuration failed %d", err));
		return;
	}
	BDBG_ERR(("Set HDMI output configuration done"));
	
	sDstDetails.eAudioDst = BRAP_AudioDst_eOutputPort;
	sDstDetails.uDstDetails.sOpDetails = sOpDetails;

	err = BRAP_AddDestination(g_handles.hCompressedAssociatedCh, &sDstDetails, &s_hMaiDstHandle);
	BDBG_ASSERT(BERR_SUCCESS == err);
}

/* Configure all output ports for this board */
void boutput_configure(void)
{
	BERR_Code                ret = BERR_SUCCESS;
	BRAP_OutputPortConfig    sOutputSettings;
	BRAP_Handle             hRap = GetRAP();
	static bool configured = false;
	BDBG_ASSERT(hRap);

	if (configured)
	{
		BDBG_WRN(("boutput_configure already completed"));
		return;
	}
	BKNI_Memset(&sDecodeAssChSettings,0,sizeof(sDecodeAssChSettings));
	BKNI_Memset(&sCompresseAssChSettings,0,sizeof(sCompresseAssChSettings));

	boutput_configure_hdmi_port(hRap,BRAP_OutputPort_eMaiMulti0);
	boutput_configure_hdmi_port(hRap,BRAP_OutputPort_eMaiMulti1);
	boutput_configure_hdmi_port(hRap,BRAP_OutputPort_eMaiMulti2);
	boutput_configure_hdmi_port(hRap,BRAP_OutputPort_eMaiMulti3);
	BDBG_MSG(("MAI0-4 output configuration done"));     

	/* For the SPDIF output */
	ret = BRAP_GetDefaultOutputConfig  (hRap, BRAP_OutputPort_eSpdif, &sOutputSettings);
	BDBG_ASSERT(BERR_SUCCESS == ret);

	/* Fill up output settings */
	sOutputSettings.eOutputPort = BRAP_OutputPort_eSpdif;
	sOutputSettings.bCompressed = false;
	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
	sOutputSettings.uiOutputBitsPerSample = 24;
	sOutputSettings.uOutputPortSettings.sSpdifSettings.eMClkRate = BRAP_OP_MClkRate_e256Fs;	  /* Slect MClkRate for SPDIF */
	sOutputSettings.uOutputPortSettings.sSpdifSettings.ePll = BRAP_OP_Pll_ePll0;   /* Slect PLL0 for SPDIF */
#if 0 /*BRAP_INDEP_OP_DELAY_SUPPORTED*/
	sOutputSettings.bIndpDlyRqd = true;
	sOutputSettings.iDelay = 16;
#endif    

	/* Configure SPDIF */       
	ret = BRAP_SetOutputConfig(hRap, &sOutputSettings);
	BDBG_ASSERT(BERR_SUCCESS == ret);
	BDBG_MSG(("SPDIF output configuration done"));     

	/* For the HDMI output */
	ret = BRAP_GetDefaultOutputConfig  (hRap, BRAP_OutputPort_eMai, &sOutputSettings);
	BDBG_ASSERT(BERR_SUCCESS == ret);

	/* Fill up output settings */
	sOutputSettings.eOutputPort = BRAP_OutputPort_eMai;
	sOutputSettings.bCompressed = false;
	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
	sOutputSettings.uiOutputBitsPerSample = 24;
	sOutputSettings.uOutputPortSettings.sMaiSettings.eMClkRate = BRAP_OP_MClkRate_e256Fs;	 /* Slect MClkRate for MAI */
	sOutputSettings.uOutputPortSettings.sMaiSettings.eMaiMuxSelector = BRAP_OutputPort_eMai;
	sOutputSettings.uOutputPortSettings.sMaiSettings.eMaiAudioFormat = BRAP_OP_MaiAudioFormat_eSpdif2Channel;
//	sOutputSettings.uOutputPortSettings.sMaiSettings.ePll = BRAP_OP_Pll_ePll0;

	/* Configure MAI */       
	ret = BRAP_SetOutputConfig(hRap, &sOutputSettings);
	BDBG_ASSERT(BERR_SUCCESS == ret);
	BDBG_MSG(("MAI output configuration done"));     

	/* For DAC0 */
	ret = BRAP_GetDefaultOutputConfig  (hRap, BRAP_OutputPort_eDac0, &sOutputSettings);
	BDBG_ASSERT(BERR_SUCCESS == ret);

	/* Fill up output settings */
	sOutputSettings.eOutputPort = BRAP_OutputPort_eDac0;
	sOutputSettings.bCompressed = false;
	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
	sOutputSettings.uiOutputBitsPerSample = 24;
#if 0 /*BRAP_INDEP_OP_DELAY_SUPPORTED*/
	sOutputSettings.bIndpDlyRqd = true;
	sOutputSettings.iDelay = 16;
#endif    

	/* Configure the DAC output */
	ret = BRAP_SetOutputConfig(hRap, &sOutputSettings);
	BDBG_ASSERT(BERR_SUCCESS == ret);
	BDBG_MSG(("DAC 0 output configuration done"));     

	configured = true;
}
/* Configure all output ports for this board */
void boutput_add_decode_association(BRAP_ChannelHandle hRapCh)
{
	BERR_Code err;
	unsigned int i;

	BDBG_ASSERT(hRapCh);

	BKNI_EnterCriticalSection();
	if (g_handles.hDecodeAssociatedCh)
	{
		err = BRAP_DestroyAssociation(g_handles.hDecodeAssociatedCh);
		BDBG_ASSERT(BERR_SUCCESS == err);
		g_handles.hDecodeAssociatedCh = NULL;
	}
	for (i = 0; i < BRAP_MAX_ASSOCIATED_CHANNELS_IN_GRP; ++i)
	{
		if (sDecodeAssChSettings.sChDetail[i].hRapCh == NULL)
		{	
			sDecodeAssChSettings.sChDetail[i].hRapCh = hRapCh;
			break;
		}
	}
	err = BRAP_CreateAssociation(&(g_handles.hDecodeAssociatedCh), &sDecodeAssChSettings);
	BDBG_ASSERT(BERR_SUCCESS == err);
	BKNI_LeaveCriticalSection();
	boutput_config_decode_outputs();
	boutput_add_postprocessing(hRapCh);

    /* default is 1171, change to 1100 for the correct 25KHz full scale deviation */
    set_fm_deviation_value(1100);

	return;
}

void boutput_add_compress_association(BRAP_ChannelHandle hRapCh)
{
	BERR_Code err;
	unsigned int i;

	BDBG_ASSERT(hRapCh);
	BKNI_EnterCriticalSection();

	if (g_handles.hCompressedAssociatedCh)
	{
		err = BRAP_DestroyAssociation(g_handles.hCompressedAssociatedCh);
		BDBG_ASSERT(BERR_SUCCESS == err);
		g_handles.hCompressedAssociatedCh = NULL;
	}
	for (i = 0; i <BRAP_MAX_ASSOCIATED_CHANNELS_IN_GRP; ++i)
	{
		if (sCompresseAssChSettings.sChDetail[i].hRapCh == NULL)
		{
			sCompresseAssChSettings.sChDetail[i].hRapCh = hRapCh;
			break;
		}
	}
	err = BRAP_CreateAssociation(&(g_handles.hCompressedAssociatedCh), &sCompresseAssChSettings);
	BDBG_ASSERT(BERR_SUCCESS == err);
	BKNI_LeaveCriticalSection();
//	boutput_config_compress_outputs();
//	boutput_add_postprocessing(hRapCh);
	return;
}	

void boutput_remove_decode_mai_output(void)
{
    if (s_hMaiDstHandle)
    {
        BRAP_RemoveDestination(g_handles.hDecodeAssociatedCh,s_hMaiDstHandle);
    }
}

void boutput_remove_compress_mai_output(void)
{
	if (s_hMaiDstHandle)
	{
		BRAP_RemoveDestination(g_handles.hCompressedAssociatedCh,s_hMaiDstHandle);
	}
}
void boutput_add_compress_mai_output(void)
{
	boutput_config_compress_outputs();
}

void boutput_add_decode_mai_output(void)
{
	BERR_Code err;
	BRAP_OutputPortDetails	sOpDetails;
	BRAP_OutputPortConfig	sOutputSettings;
	BRAP_DstDetails			sDstDetails;
	int i;

	for (i=0; i<BRAP_OutputChannelPair_eMax; i++)
	{
		sOpDetails.eOutput[i] = BRAP_OutputPort_eMax;
	}

	sOpDetails.eOutput[0] = BRAP_OutputPort_eMai;
	sOpDetails.eAudioMode = BRAP_OutputMode_e2_0;
	sOpDetails.bLfeOn = false;
	sOpDetails.bDownmixedOpPort = false;
	err = BRAP_GetCurrentOutputConfig(GetRAP(), BRAP_OutputPort_eMai, &sOutputSettings);
	if (err != BERR_SUCCESS)
	{
		BDBG_ERR(("Get Current Settings for HDMI Output failed %d (%d)", err, __LINE__));
		return;
	}
	BDBG_MSG(("Defailt settings received for HDMI Output"));
	
	/* Fill up output settings */
	sOutputSettings.eOutputPort = BRAP_OutputPort_eMai;
	sOutputSettings.bCompressed = false;
	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;

	err = BRAP_SetOutputConfig(GetRAP(), &sOutputSettings);
	if (err != BERR_SUCCESS)
	{
		BDBG_ERR(("Set HDMI output configuration failed %d (%d)", err, __LINE__));
		return;
	}
	BDBG_ERR(("Set HDMI output configuration done"));
	sDstDetails.eAudioDst = BRAP_AudioDst_eOutputPort;
	sDstDetails.uDstDetails.sOpDetails = sOpDetails;
	err = BRAP_AddDestination(g_handles.hDecodeAssociatedCh, &sDstDetails, &s_hMaiDstHandle);
	if (err != BERR_SUCCESS)
	{
		BDBG_ERR(("Set AddDestination failed: %d(%d)", err, __LINE__));
		return;
	}
}
/* Configure all output ports for this board */
void boutput_remove_decode_association(BRAP_ChannelHandle hRapCh)
{
	BERR_Code err;
	int i,cnt;
	BRAP_AssociatedChanSettings tmpAssSettings;

	BDBG_ASSERT(hRapCh);
	BDBG_ASSERT(g_handles.hDecodeAssociatedCh);

	BKNI_EnterCriticalSection();
	cnt = 0;
	BKNI_Memset(&tmpAssSettings,0,sizeof(tmpAssSettings));
	for (i = 0; i < BRAP_MAX_ASSOCIATED_CHANNELS_IN_GRP; ++i)
	{
		if (sDecodeAssChSettings.sChDetail[i].hRapCh && (sDecodeAssChSettings.sChDetail[i].hRapCh != hRapCh))
		{
			tmpAssSettings.sChDetail[cnt].hRapCh = sDecodeAssChSettings.sChDetail[i].hRapCh;
			cnt++;
		}
		sDecodeAssChSettings.sChDetail[i].hRapCh = NULL;
	}
	BKNI_Memcpy(&sDecodeAssChSettings,&tmpAssSettings,sizeof(sDecodeAssChSettings));
	err = BRAP_DestroyAssociation(g_handles.hDecodeAssociatedCh);
	BDBG_ASSERT(BERR_SUCCESS == err);
	g_handles.hDecodeAssociatedCh = NULL;

	err = BRAP_CreateAssociation(&(g_handles.hDecodeAssociatedCh), &sDecodeAssChSettings);
	BDBG_ASSERT(BERR_SUCCESS == err);
	BKNI_LeaveCriticalSection();

	boutput_config_decode_outputs();
	return;
}
void boutput_remove_compress_association(BRAP_ChannelHandle hRapCh)
{
	BERR_Code err;
	int i,cnt;
	BRAP_AssociatedChanSettings tmpAssSettings;

	BDBG_ASSERT(hRapCh);
	BDBG_ASSERT(g_handles.hCompressedAssociatedCh);

	BKNI_EnterCriticalSection();
	cnt = 0;
	BKNI_Memset(&tmpAssSettings, 0, sizeof(tmpAssSettings));
	for (i = 0; i < BRAP_MAX_ASSOCIATED_CHANNELS_IN_GRP; ++i)
	{
		if (sCompresseAssChSettings.sChDetail[i].hRapCh && (sCompresseAssChSettings.sChDetail[i].hRapCh != hRapCh))
		{
			tmpAssSettings.sChDetail[cnt].hRapCh = sCompresseAssChSettings.sChDetail[i].hRapCh;
			cnt++;
		}
		sCompresseAssChSettings.sChDetail[i].hRapCh = NULL;
	}
	BKNI_Memcpy(&sCompresseAssChSettings,&tmpAssSettings,sizeof(sDecodeAssChSettings));
	err = BRAP_DestroyAssociation(g_handles.hCompressedAssociatedCh);
	BDBG_ASSERT(BERR_SUCCESS == err);
	g_handles.hCompressedAssociatedCh = NULL;

	err = BRAP_CreateAssociation(&(g_handles.hCompressedAssociatedCh), &sCompresseAssChSettings);
	BDBG_ASSERT(BERR_SUCCESS == err);
	BKNI_LeaveCriticalSection();

	boutput_config_compress_outputs();
	return;
}

void boutput_add_postprocessing(BRAP_ChannelHandle hRapCh)
{
	BRAP_ProcessingStageSettings sProcessingStageSettings;
	BRAP_ProcessingSettings sStgSettings;
	BERR_Code err;

	BDBG_ASSERT(hRapCh);
	BDBG_ASSERT(s_hDacDstHandle);

	if (s_hBtscStageHandle)
	{
		BRAP_DestroyProcessingStage(s_hBtscStageHandle);
		s_hBtscStageHandle = NULL;
	}
	err = BRAP_GetDefaultProcessingStageSettings( BRAP_ProcessingType_eBtsc, &sProcessingStageSettings );
	BDBG_ASSERT (BERR_SUCCESS == err);
	sProcessingStageSettings.uConfigParams.sBTSCParams.bUseDeEmphasizedSourceSignals = false;
	
	sProcessingStageSettings.uConfigParams.sBTSCParams.bSumChanFreqDevCtrl = true;               /*Default Enable: Used to Control FM Deviation of Sum Channel to 25Khz*/
	sProcessingStageSettings.uConfigParams.sBTSCParams.bDiffChanFreqDevCtrl = true;              /*Default Enable: Used to Control FM Deviation of Diff Channel to 50Khz*/
	sProcessingStageSettings.uConfigParams.sBTSCParams.bOpFreqDevCtrl = true;                    /*Default Enable: Used to Control FM Deviation of Final Output to 50Khz*/

	sProcessingStageSettings.uConfigParams.sBTSCParams.bFreqGeneration = false;                   /*Default Disable: Used to Generate Test Tones*/
	sProcessingStageSettings.uConfigParams.sBTSCParams.ui32Frequency = 0;                 /*Default 0 generates frequency sweep.  Programming to a fixed value generates tone*/
	sProcessingStageSettings.uConfigParams.sBTSCParams.ui32SRDCalibrationFactor = 1100;
    
	err = BRAP_CreateProcessingStage(GetRAP(),&sProcessingStageSettings, &s_hBtscStageHandle );
	BDBG_ASSERT (BERR_SUCCESS == err);
	err = BRAP_GetDefaultPostProcessingStages( &sStgSettings );
	BDBG_ASSERT (BERR_SUCCESS == err);
	sStgSettings.hAudProcessing[0] = s_hBtscStageHandle;

	err = BRAP_SetPostProcessingStages( s_hDacDstHandle, hRapCh, &sStgSettings );
	BDBG_ASSERT (BERR_SUCCESS == err);
}
void boutput_set_postprocessing_volume(int volume)
{
	BRAP_ProcessingStageSettings sProcessingStageSettings;
	BERR_Code err;

	BDBG_ASSERT(s_hBtscStageHandle);

	err = BRAP_GetCurrentProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
	BDBG_ASSERT (BERR_SUCCESS == err);

	BDBG_ERR(("boutput_set_postprocessing_volume = %d", volume));

	sProcessingStageSettings.uConfigParams.sBTSCParams.uiVolumeLevel = volume;
	sProcessingStageSettings.uConfigParams.sBTSCParams.bBTSCEnableFlag = true;
	sProcessingStageSettings.eAudioProcessing = BRAP_ProcessingType_eBtsc;

	err = BRAP_SetProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
	BDBG_ASSERT (BERR_SUCCESS == err);
}

int get_fm_deviation_value()
{
	BRAP_ProcessingStageSettings sProcessingStageSettings;
	BERR_Code err;

	if (!s_hBtscStageHandle)
		return 0;

	err = BRAP_GetCurrentProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
	BDBG_ASSERT (BERR_SUCCESS == err);

	return sProcessingStageSettings.uConfigParams.sBTSCParams.ui32SRDCalibrationFactor;
}
void set_fm_deviation_value(int value)
{
	BRAP_ProcessingStageSettings sProcessingStageSettings;
	BERR_Code err;

	if (!s_hBtscStageHandle)
		return;

	err = BRAP_GetCurrentProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
	BDBG_ASSERT (BERR_SUCCESS == err);

	BDBG_ERR(("set_fm_deviation_value = %d", value));

	sProcessingStageSettings.uConfigParams.sBTSCParams.ui32SRDCalibrationFactor = value;
	sProcessingStageSettings.eAudioProcessing = BRAP_ProcessingType_eBtsc;

	err = BRAP_SetProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
	BDBG_ASSERT (BERR_SUCCESS == err);
}


void boutput_set_postprocessing_deemphasized(bool enable)
{
	BRAP_ProcessingStageSettings sProcessingStageSettings;
	BERR_Code err;

	BDBG_ASSERT(s_hBtscStageHandle);

	err = BRAP_GetCurrentProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
	BDBG_ASSERT (BERR_SUCCESS == err);
	// Enabled by default but needs to be disabled in normal operations.
	sProcessingStageSettings.uConfigParams.sBTSCParams.bUseDeEmphasizedSourceSignals = enable;
	BDBG_ERR(("boutput_set_postprocessing_deemphasized = %d", enable));

	err = BRAP_SetProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
	BDBG_ASSERT (BERR_SUCCESS == err);
}

void boutput_set_postprocessing_preemphasized(bool enable)
{
	BRAP_ProcessingStageSettings sProcessingStageSettings;
	BERR_Code err;

	BDBG_ASSERT(s_hBtscStageHandle);

	err = BRAP_GetCurrentProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
	BDBG_ASSERT (BERR_SUCCESS == err);
	// Enabled by default but needs to be disabled in normal operations.
	sProcessingStageSettings.uConfigParams.sBTSCParams.bMainChannelPreEmphasisOn = enable;
	sProcessingStageSettings.uConfigParams.sBTSCParams.bDiffChannelPreEmphasisOn = enable;

	BDBG_ERR(("boutput_set_postprocessing_preemphasized = %d", enable));

	err = BRAP_SetProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
	BDBG_ASSERT (BERR_SUCCESS == err);
}


BERR_Code boutput_set_association_vol(BRAP_OutputPort eOpType, unsigned int iLVol, unsigned int iRVol)
{
    BERR_Code err = BERR_NOT_INITIALIZED;

	/* TODO current Mai only, will add other if needed */
    if ((BRAP_OutputPort_eMai == eOpType) && s_hMaiDstHandle)
    {
        err = BRAP_SetDestinationVolume(s_hMaiDstHandle, iLVol, iRVol);
    }
	else {
		BDBG_ERR(("null s_hMaiDstHandle"));
	}
	return err;
}

BERR_Code boutput_set_association_mute(BRAP_OutputPort eOpType, bool bMute)
{
    BERR_Code err = BERR_NOT_INITIALIZED;

    /* TODO current Mai only, will add other if needed */
    if ((BRAP_OutputPort_eMai == eOpType) && s_hMaiDstHandle)
    {
        err = BRAP_SetDestinationMute(s_hMaiDstHandle, bMute);
    }
    else {
        BDBG_ERR(("null s_hMaiDstHandle"));
    }
    return err;
}
#else
int get_fm_deviation_value()
{
		return 0;
}
void set_fm_deviation_value(int value)
{
}
#endif
void gist_init(void)
{
	BERR_Code berr;
	static BTMR_DefaultSettings tmr_settings;
	static BMEM_Settings mem_settings;
	static BMEM_Heap_Settings heap_settings;
	static BXPT_DefaultSettings xpt_settings;
	static BXPT_Rave_ChannelSettings raveSettings;
	static BXVD_Settings xvdSettings;
	static BXVD_ChannelSettings   xvdChannelSettings;
	static BXPT_PCR_DefSettings pcrSettings;
	int i;

	BREG_Open(&g_handles.hReg, (void*)BCM_PHYS_TO_KSEG1(BCHP_PHYSICAL_OFFSET), BCHP_REGISTER_END);
#if (BCHP_CHIP==7552) /* [JPF] */
	berr = BCHP_Open7552(&g_handles.hChp, GetREG());
	BDBG_ASSERT(BERR_SUCCESS == berr);
	
	berr = BINT_Open(&g_handles.hInt, GetREG(), BINT_7552_GetSettings());
#else
	berr = BCHP_Open7550(&g_handles.hChp, GetREG());
	BDBG_ASSERT(BERR_SUCCESS == berr);
	
	berr = BINT_Open(&g_handles.hInt, GetREG(), BINT_7550_GetSettings());
#endif
	BDBG_ASSERT(BERR_SUCCESS == berr);

	BINT_GetL1BitMask(GetINT(), s_L1Mask);
	for (i = 0; i <= NUM_L1_STATUS; ++i)
	{
		BREG_Write32(GetREG(),BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR + (i * 4),s_L1Mask[i]);
	}
	berr = BTMR_GetDefaultSettings(&tmr_settings);
	BDBG_ASSERT(BERR_SUCCESS == berr);

	berr = BTMR_Open(&g_handles.hTmr, GetCHP(), GetREG(), GetINT(), &tmr_settings);
	BDBG_ASSERT(BERR_SUCCESS == berr);
	
	berr = BMEM_GetDefaultSettings(&mem_settings);
	BDBG_ASSERT(BERR_SUCCESS == berr);

	berr = BMEM_Open(&g_handles.hMem, &mem_settings);
	BDBG_ASSERT(BERR_SUCCESS == berr);

	berr = BMEM_Heap_GetDefaultSettings(&heap_settings);
	BDBG_ASSERT(BERR_SUCCESS == berr);
#ifdef BCM_DEBUG
	heap_settings.eSafetyConfig = BMEM_SafetyConfig_eSafe;
#endif
	g_heap_ptr = (void *)BCM_PHYS_TO_KSEG1(BKNI_Malloc(DEVICE_MEM_SIZE));

	heap_settings.pCachedAddress = (void *)BCM_PHYS_TO_KSEG0(BCM_CPU_TO_PHYS(g_heap_ptr));
	heap_settings.flush = gist_flush_cache;
	heap_settings.flush_isr = gist_flush_cache;

	berr = BMEM_Heap_Create(GetMEM(), (void*)g_heap_ptr, BCM_CPU_TO_PHYS(g_heap_ptr), DEVICE_MEM_SIZE, &heap_settings, &g_handles.hHeap);
	BDBG_ASSERT(BERR_SUCCESS == berr);

#if 0
#ifdef CONFIG_MRC
	{
		BERR_Code rc;	
		static BMEM_MonitorInterface interface;
		BMRC_Settings mrcSettings;
		BMRC_Monitor_Settings monitorSettings;

		rc = BMRC_GetDefaultSettings(&mrcSettings);
		BDBG_ASSERT(!rc);
		rc = BMRC_Open(&mrc_handle, GetREG(), GetINT(), &mrcSettings);
		BDBG_ASSERT(!rc);
		BMRC_Monitor_GetDefaultSettings(&monitorSettings);
		BDBG_ASSERT(!rc);
		rc = BMRC_Monitor_Open(&mrc_monitor_handle, GetREG(), GetINT(), GetCHP(), mrc_handle, 0, 128 * 1024 * 1024, &monitorSettings);
		BDBG_ASSERT(!rc);
		rc = BMRC_Monitor_GetMemoryInterface(mrc_monitor_handle, &interface);
		BDBG_ASSERT(!rc);
		rc = BMEM_InstallMonitor(GetHEAP(), &interface);
		BDBG_ASSERT(!rc);
	}
#endif
#endif

#if	defined(ACB612) || defined(ACB615)
	{
		uint32_t reg;
		
		reg = 0x00182003;
		BREG_Write32(GetREG(), BCHP_MEMC_ARB_0_CLIENT_INFO_25, reg);
		reg = 0x00142001;
		BREG_Write32(GetREG(), BCHP_MEMC_ARB_0_CLIENT_INFO_53, reg);
		reg = 0x0011b000;
		BREG_Write32(GetREG(), BCHP_MEMC_ARB_0_CLIENT_INFO_61, reg);
		reg = 0x002f4007;
		BREG_Write32(GetREG(), BCHP_MEMC_ARB_0_CLIENT_INFO_74, reg);
		//reg = 0x00179001;
		//BREG_Write32(GetREG(), BCHP_MEMC_ARB_0_CLIENT_INFO_75, reg);
		reg = 0x001d7004;
		BREG_Write32(GetREG(), BCHP_MEMC_ARB_0_CLIENT_INFO_80, reg);
		/* MFD0 RTS change from 0x002F6007 */
		reg = 0x00238006;
		BREG_Write32(GetREG(), BCHP_MEMC_ARB_0_CLIENT_INFO_60, reg);
	}
#endif

#if (CONFIG_ENABLE_SCM == 1)
	/* this must be done before XPT initialization 
	   but after mem and reg initialization */
	berr = scml_decrypt();
	BDBG_ASSERT(BERR_SUCCESS == berr);
#endif
	berr = BXPT_GetDefaultSettings(&xpt_settings, GetCHP());
	BDBG_ASSERT(BERR_SUCCESS == berr);
	xpt_settings.BandwidthConfig.MaxInputRate[0] = 50000000;
#ifdef OOB_TUNER_SUPPORT
	xpt_settings.BandwidthConfig.MaxInputRate[OOB_TUNER_BAND] = 10000000;
#endif
	berr = BXPT_Open(&g_handles.hXpt, GetCHP(), GetREG(), GetHEAP(), GetINT(), &xpt_settings);
	BDBG_ASSERT(BERR_SUCCESS == berr);

	BXPT_PCR_GetChannelDefSettings(GetXPT(),0 , &pcrSettings);
	berr = BXPT_PCR_Open(GetXPT(), 0, &pcrSettings,&(g_handles.hDPCR));
	BDBG_ASSERT(BERR_SUCCESS == berr);

	berr = BXPT_SetParserDataSource(GetXPT(), 0, BXPT_DataSource_eInputBand, PARSER_BAND/*ADS input */);
	BDBG_ASSERT(BERR_SUCCESS == berr);
	
	berr = BXPT_SetParserEnable(GetXPT(), 0, true);
	BDBG_ASSERT(BERR_SUCCESS == berr);
	
#ifdef OOB_TUNER_SUPPORT
	/* use PID parser 1 for OOB CA/SI... data, NOTE that OOB_IB and OOB_TUNER_BAND are defined in makefile */
	berr = BXPT_SetParserDataSource(GetXPT(), OOB_TUNER_BAND, BXPT_DataSource_eInputBand, OOB_IB);
	BDBG_ASSERT(BERR_SUCCESS == berr);
	
	berr = BXPT_SetParserEnable(GetXPT(), OOB_TUNER_BAND, true);
	BDBG_ASSERT(BERR_SUCCESS == berr);
#endif

	berr = BXPT_Rave_GetChannelDefaultSettings(GetXPT(),0,&raveSettings);
	BDBG_ASSERT(BERR_SUCCESS == berr);
	
	
	berr = BXPT_Rave_OpenChannel(GetXPT(),&g_handles.hRave,0, &raveSettings);
	BDBG_ASSERT(BERR_SUCCESS == berr);
	

	NEXUS_Platform_P_InitPinmux(GetREG());

#if	defined(ACB612) || defined(ACB615)
	gist_power_down_modules(GetREG());
#endif

#ifndef CONFIG_LWIP_TEST
	gist_power_down_eth(GetREG());
#endif

#ifdef CONFIG_VSB
    gist_config_vsb(GetREG());
#endif

	berr = BI2C_Open( &(g_handles.hI2c),GetCHP(), GetREG(), GetINT(), (BI2C_Settings *)NULL );
	BDBG_ASSERT(BERR_SUCCESS == berr);
	

	/* Open the decoder channel and hook up interrupts before opening video windows */
	BXVD_GetDefaultSettings(&xvdSettings);

	berr = BXVD_Open(&(g_handles.hXvd),GetCHP(),GetREG(),NULL,GetHEAP(),GetINT(),&xvdSettings);
	BDBG_ASSERT(berr == BERR_SUCCESS);

	BXVD_GetChannelDefaultSettings(g_handles.hXvd, 0, &xvdChannelSettings);
	berr= BXVD_OpenChannel(g_handles.hXvd,&(g_handles.hXvdCh),0,&xvdChannelSettings);
	BDBG_ASSERT(berr == BERR_SUCCESS);

	berr = BGIO_Open(&g_handles.hGio, GetCHP(), GetREG());
	BDBG_ASSERT(BERR_SUCCESS == berr);
}

#if	defined(ACB612) || defined(ACB615)
static void gist_power_down_modules(BREG_Handle hReg)
{
	uint32_t reg;

	/* power down USB 0 and 1 */
	reg = BREG_Read32(hReg,BCHP_USB_CTRL_UTMI_CTL_1);
	reg &= ~(BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK |
			 BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK);
	BREG_Write32 (hReg, BCHP_USB_CTRL_UTMI_CTL_1, reg);

	reg = BREG_Read32(hReg,BCHP_USB_CTRL_PLL_CTL);
	reg &= ~(BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK
			);
	reg |= (BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK
		   );
	BREG_Write32 (hReg, BCHP_USB_CTRL_PLL_CTL, reg);

	reg = BREG_Read32(hReg,BCHP_CLKGEN_USB_CLOCK_DISABLE);
	reg |= (BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK
		   );
	BREG_Write32 (hReg, BCHP_CLKGEN_USB_CLOCK_DISABLE, reg);

	reg = BREG_Read32(hReg,BCHP_CLKGEN_USB_CLOCK_ENABLE);
	reg &= ~(BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK |
			 BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK
			);
	BREG_Write32 (hReg, BCHP_CLKGEN_USB_CLOCK_ENABLE, reg);

	/* some registers can be set only in atomic manner */
	/* smart card 0 and 1 */
	reg = BREG_Read32(hReg,BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE);
	reg |= (BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK |
			BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK
		   );
	BREG_AtomicUpdate32 (hReg, BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE, reg, reg);

	reg = BREG_Read32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0);
	reg |= (BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK |
			BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK);
	/* need to be atomic */
	BREG_AtomicUpdate32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0, reg, reg);

	reg = BREG_Read32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1);
	reg |= (BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK |
			BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK);
	/* need to be atomic */
	BREG_AtomicUpdate32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1, reg, reg);

	/* PLL channel2 - 184 MHz TS clock */
	//reg = BREG_Read32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2);
	//reg |= (BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK);
	//BREG_Write32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2, reg);
	
	//ƯÁ¤ stream¿¡¼­ audio tick-noise patch code. KHW140507
	/*RLQ, increase audio DSP frequency for handling higher bit rate AC3 audio */
	reg = BREG_Read32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3);
	reg &= ~BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK;
	/* change from default 0x32 to 8 */
	reg |= (8L << BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT);
	BREG_Write32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3, reg);
	
	/* power down SYS1 PLL output channel5 - 225MHz TS clock */
	reg = BREG_Read32(hReg, BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5);
	reg |= (BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK
			);
	//BREG_Write32(hReg, BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5, reg);

	reg = BREG_Read32(hReg, BCHP_CLKGEN_PAD_CLOCK_DISABLE);
	reg |= (BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_MASK
		   );
	//BREG_Write32(hReg, BCHP_CLKGEN_PAD_CLOCK_DISABLE, reg);

/* ACB615 has HDMI output so don't power the module if for ACB615 build */
#ifndef ACB615
	/* DVP HDMI */
	reg = BREG_Read32(hReg, BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3);
	reg |= (BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK
		   );
	BREG_Write32(hReg, BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3, reg);

#if 0
	reg = BREG_Read32(hReg, BCHP_HDMI_TX_PHY_POWERDOWN_CTL);
	reg |= (BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_0_PWRDN_MASK |
			BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_1_PWRDN_MASK |
			BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_2_PWRDN_MASK |
			BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_CK_PWRDN_MASK |
			BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_RNDGEN_PWRDN_MASK |
			BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_PLL_PWRDN_MASK |
			BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_BIAS_PWRDN_MASK |
			BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_PHY_PWRDN_MASK
		   );
	BREG_Write32(hReg, BCHP_HDMI_TX_PHY_POWERDOWN_CTL, reg);
#endif

	reg = BREG_Read32(hReg, BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE);
	reg |= (BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK
		   );
	BREG_Write32(hReg, BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE, reg);

	reg = BREG_Read32(hReg, BCHP_CLKGEN_DVP_HT_ENABLE);
	reg &= ~(BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK 
			);
	BREG_AtomicUpdate32(hReg, BCHP_CLKGEN_DVP_HT_ENABLE, reg, reg);

	reg = BREG_Read32(hReg, BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE);
	reg &= ~(BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK |
			 BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK |
			 BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK |
			 BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK
			);
	BREG_AtomicUpdate32(hReg, BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE, reg, reg);
#endif

	/* DAC */
	reg = BREG_Read32(hReg, BCHP_MISC_DAC_CTRL_0);
	reg |= (BCHP_MISC_DAC_CTRL_0_DAC1_PWRDN_MASK |
			BCHP_MISC_DAC_CTRL_0_DAC2_PWRDN_MASK | 
			BCHP_MISC_DAC_CTRL_0_DAC3_PWRDN_MASK
		   );
	BREG_Write32(hReg, BCHP_MISC_DAC_CTRL_0, reg);

#if 0
	/* VEC */
	reg = BREG_Read32(hReg, BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE);
	reg &= ~(BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_MASK |
			 BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_MASK
			);
	BREG_Write32(hReg, BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE, reg);
#endif

	/* SECTOP */
	reg = BREG_Read32(hReg, BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE);
	reg &= ~(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK
			 );
	BREG_AtomicUpdate32(hReg, BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE, reg, reg);

#if BCHP_VER >= BCHP_VER_B0
	/* power off tuner daisy output */
	reg = BREG_Read32(hReg, BCHP_UFE_AFE_TNR0_PWRUP_01);
	reg &= ~(BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DAISY_VHF_MASK |
			 BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DAISY_UHF_MASK |
			 BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LT_MASK |
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_SDADC_REG1p0_MASK |		/* SDADC */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_DAC_LPF_pwrup_RFAGC_MASK |   	/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_RFDPD_pwrup_RFAGC_MASK |     	/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_BB2DPD_pwrup_RFAGC_MASK |		/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_BB1DPD_pwrup_RFAGC_MASK |		/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LNAAGC_MASK |			/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DAC12B_MASK |			/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_ADC6B_MASK |			/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_UHF_incom_MASK |		/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_UHF_BUF_MASK |			/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_REG1p0_MASK |			/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DCO_MASK |				/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DPM_MASK |				/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DPM_LOBUF_REG_MASK |	/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LPF_Res_MASK |			/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LPF_Q_MASK |			/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LPF_I_MASK |			/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_FGA_MASK |				/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_MIXER_MASK |			/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_TRKFIL_BUF_MASK |		/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_TRKFIL_MASK |			/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_RFVGA_MASK |			/* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_BIAS_MASK 				/* tuner 0 */
			 );
#ifdef CONFIG_ISDB
    reg = BREG_Read32(hReg, BCHP_UFE_AFE_TNR0_PWRUP_01);
    reg |= (BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DAISY_VHF_MASK |
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DAISY_UHF_MASK |
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LT_MASK |
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_SDADC_REG1p0_MASK |     /* SDADC */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_DAC_LPF_pwrup_RFAGC_MASK |    /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_RFDPD_pwrup_RFAGC_MASK |      /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_BB2DPD_pwrup_RFAGC_MASK |     /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_BB1DPD_pwrup_RFAGC_MASK |     /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LNAAGC_MASK |           /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DAC12B_MASK |           /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_ADC6B_MASK |            /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_UHF_incom_MASK |        /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_UHF_BUF_MASK |          /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_REG1p0_MASK |           /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DCO_MASK |              /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DPM_MASK |              /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DPM_LOBUF_REG_MASK |    /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LPF_Res_MASK |          /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LPF_Q_MASK |            /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LPF_I_MASK |            /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_FGA_MASK |              /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_MIXER_MASK |            /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_TRKFIL_BUF_MASK |       /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_TRKFIL_MASK |           /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_RFVGA_MASK |            /* tuner 0 */
             BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_BIAS_MASK               /* tuner 0 */
             );
#endif
	BREG_Write32(hReg, BCHP_UFE_AFE_TNR0_PWRUP_01, reg);

#endif	/* B0 */

	/* power off THD clocks */
	reg = BREG_Read32(hReg, BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE);
	reg &= ~(BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_SCB_CLOCK_ENABLE_MASK |
			 BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_216_CLOCK_ENABLE_MASK |
			 BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_108_CLOCK_ENABLE_MASK
			 );
#ifdef CONFIG_ISDB
	/* power on THD clocks for IDSB-T */
	reg = BREG_Read32(hReg, BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE);
	reg |= (BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_SCB_CLOCK_ENABLE_MASK |
			BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_216_CLOCK_ENABLE_MASK |
			BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_108_CLOCK_ENABLE_MASK
		   );
#endif
	BREG_Write32(hReg, BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE, reg);

	/* set M2MC 216 MHz */
	reg = BREG_Read32(hReg, BCHP_CLKGEN_INTERNAL_MUX_SELECT);
	reg = 0;
	BREG_Write32(hReg, BCHP_CLKGEN_INTERNAL_MUX_SELECT, reg);

	/* power down all internal DS clocks */
#if 0
	reg = BREG_Read32(hReg,BCHP_DS_PD);
	reg = 0xffffffff;
	BREG_Write32 (hReg, BCHP_DS_PD, reg);
#endif

#ifdef OOB_TUNER_SUPPORT
	/* power down UFE_OBADC */
#if BCHP_VER >= BCHP_VER_B0
	reg = BREG_Read32(hReg,BCHP_OBADC_CNTL3);
	reg &= ~(BCHP_OBADC_CNTL3_PWRUP_MASK
			);
	BREG_Write32 (hReg, BCHP_OBADC_CNTL3, reg);
#endif
#endif

	/* power down UFE_SDADC */
	reg = BREG_Read32(hReg,BCHP_SDADC_CTRL_PWRUP);
	reg = 0;
	BREG_Write32 (hReg, BCHP_SDADC_CTRL_PWRUP, reg);

	/* power down tuner 0 */
	reg = BREG_Read32(hReg, BCHP_UFE_AFE_TNR_PWRUP_01);
	reg &= ~(BCHP_UFE_AFE_TNR_PWRUP_01_i_pwrup_ADCBUF_MASK |
			BCHP_UFE_AFE_TNR_PWRUP_01_REF_OUTDIV_PWRUP_MASK |
			BCHP_UFE_AFE_TNR_PWRUP_01_REF_OUTCML_PWRUP_MASK |
			BCHP_UFE_AFE_TNR_PWRUP_01_REF_OUTCMOS_PWRUP_MASK |
			BCHP_UFE_AFE_TNR_PWRUP_01_REF_IGEN_PWRUP_MASK |
			BCHP_UFE_AFE_TNR_PWRUP_01_REF_mux_PWRUP_MASK |
			BCHP_UFE_AFE_TNR_PWRUP_01_REF_UGB_PWRUP_MASK |
			BCHP_UFE_AFE_TNR_PWRUP_01_REF_DIV_refbuf_PWRUP_MASK |
			BCHP_UFE_AFE_TNR_PWRUP_01_REF_fbreg_PWRUP_MASK |
			BCHP_UFE_AFE_TNR_PWRUP_01_REF_VCO_PWRUP_MASK |
			BCHP_UFE_AFE_TNR_PWRUP_01_REF_REGQPPFD_PWRUP_MASK |
			BCHP_UFE_AFE_TNR_PWRUP_01_REF_QP_PWRUP_MASK |
			BCHP_UFE_AFE_TNR_PWRUP_01_REF_bgp_receiver_pup_MASK |
			BCHP_UFE_AFE_TNR_PWRUP_01_REF_POSTDIV_master_PWRUP_MASK |
			BCHP_UFE_AFE_TNR_PWRUP_01_REF_PLL_master_PWRUP_MASK
			);
#ifdef CONFIG_ISDB
    reg |= (BCHP_UFE_AFE_TNR_PWRUP_01_i_pwrup_ADCBUF_MASK |
            BCHP_UFE_AFE_TNR_PWRUP_01_REF_OUTDIV_PWRUP_MASK |
            BCHP_UFE_AFE_TNR_PWRUP_01_REF_OUTCML_PWRUP_MASK |
            BCHP_UFE_AFE_TNR_PWRUP_01_REF_OUTCMOS_PWRUP_MASK |
            BCHP_UFE_AFE_TNR_PWRUP_01_REF_IGEN_PWRUP_MASK |
            BCHP_UFE_AFE_TNR_PWRUP_01_REF_mux_PWRUP_MASK |
            BCHP_UFE_AFE_TNR_PWRUP_01_REF_UGB_PWRUP_MASK |
            BCHP_UFE_AFE_TNR_PWRUP_01_REF_DIV_refbuf_PWRUP_MASK |
            BCHP_UFE_AFE_TNR_PWRUP_01_REF_fbreg_PWRUP_MASK |
            BCHP_UFE_AFE_TNR_PWRUP_01_REF_VCO_PWRUP_MASK |
            BCHP_UFE_AFE_TNR_PWRUP_01_REF_REGQPPFD_PWRUP_MASK |
            BCHP_UFE_AFE_TNR_PWRUP_01_REF_QP_PWRUP_MASK |
            BCHP_UFE_AFE_TNR_PWRUP_01_REF_bgp_receiver_pup_MASK |
            BCHP_UFE_AFE_TNR_PWRUP_01_REF_POSTDIV_master_PWRUP_MASK |
            BCHP_UFE_AFE_TNR_PWRUP_01_REF_PLL_master_PWRUP_MASK
            );
#endif
	BREG_Write32(hReg, BCHP_UFE_AFE_TNR_PWRUP_01, reg);

	reg = BREG_Read32(hReg, BCHP_UFE_AFE_TNR0_PWRUP_02);
	reg = 0;
#ifdef CONFIG_ISDB
	reg = 0xffffffff;
#endif
	BREG_Write32(hReg, BCHP_UFE_AFE_TNR0_PWRUP_02, reg);

#ifdef OOB_TUNER_SUPPORT
	/* OOB can't power down */
#if 0
	reg = BREG_Read32(hReg,BCHP_OOB_CTRL2);
	reg &= ~(BCHP_OOB_CTRL2_OBPWR_MASK
			);
	BREG_Write32 (hReg, BCHP_OOB_CTRL2, reg);
#endif
#endif
}
#endif

static void gist_power_down_eth(BREG_Handle hReg)
{
	uint32_t reg;

	/* Power down phy */
	reg = BREG_Read32(hReg,BCHP_GENET_0_EXT_PWR_MGNT);
	reg |= (BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_phy_en_MASK | 
			BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_phy_rd_MASK |
			BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_phy_sd_MASK |
			BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_phy_rx_MASK |
			BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_phy_tx_MASK |
			BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_dll_MASK |
			BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_bias_MASK |
			BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_phy_MASK);
	BREG_Write32 (hReg, BCHP_GENET_0_EXT_PWR_MGNT, reg);

	/* SYS1 PLL */
	reg = BREG_Read32(hReg, BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2);
	reg |= (BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK |
			BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK);
	BREG_Write32(hReg, BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2, reg);

	/* Power down GENET0 */
	reg = BREG_Read32(hReg,BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE);
	reg &=	~(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK |
			BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK |
			BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK |
			BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK |
			BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK |
			BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK |
			BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK
			);
	BREG_Write32 (hReg, BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE, reg);

	reg = BREG_Read32(hReg,BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE);
	reg &=	~(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK |
			BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK |
			BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK
			);
	BREG_Write32 (hReg, BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, reg);

	reg = BREG_Read32(hReg,BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE);
	reg &=  ~(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK |
			BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK
			);
	BREG_Write32 (hReg, BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE, reg);

	reg = BREG_Read32(hReg,BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0);
	reg &=   ~(BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK
			);
	BREG_Write32 (hReg, BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0, reg);
}

#ifdef CONFIG_VSB
static void gist_config_vsb(BREG_Handle hReg)
{
	uint32_t reg;

#if 0
	/* PKT 2 */
	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12);
	reg &= ~(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_MASK | 
			BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_MASK |
			BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_MASK |
			BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_MASK |
			BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_MASK );
	reg |= (BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PKT2_CLK << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SHIFT) |
		(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PKT2_DATA << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SHIFT) |
		(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PKT2_SYNC << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SHIFT) |
		(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT2_VALID << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SHIFT) |
		(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PKT2_ERROR << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SHIFT);
	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12, reg);

	/* BSC 1 */
	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16);
	reg &= ~(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_MASK | 
			BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_MASK);
	reg |= (BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_BSC_M1_SCL << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SHIFT) |
		(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_BSC_M1_SDA << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SHIFT);
	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16, reg);
#endif

	/* 3520 External IRQ0 */
	reg = BREG_Read32(hReg,BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0);
	reg &= ~(BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK);
	reg |= (BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQ0 << BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT);
	BREG_Write32 (hReg, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0, reg);
}
#endif

/***************************************************************************
Summary:
Configure pin muxes for the 97550 reference platform
Description:
The core module must be initialized for this to be called
 ***************************************************************************/
#ifdef NEXUS_HAS_DVB_CI
#undef NEXUS_HAS_DVB_CI
#endif

#include "bchp_gio_aon.h"

static BERR_Code NEXUS_Platform_P_InitPinmux(BREG_Handle hReg)
{
	uint32_t reg;

	//sgpio00 , sgpio01 output mode
	reg = BREG_Read32(hReg,BCHP_GIO_AON_IODIR_EXT);
	
	reg &= ~(BCHP_MASK(GIO_AON_IODIR_EXT,iodir));
	reg |= (BCHP_FIELD_DATA(GIO_AON_IODIR_EXT,iodir,0));

	BREG_Write32 (hReg, BCHP_GIO_AON_IODIR_EXT, reg);

	
	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6
	 * GPIO_46    : POD2CHIP_MCLKI
	 * GPIO_47    : POD2CHIP_MDI0
	 * GPIO_48    : POD2CHIP_MDI1
	 * GPIO_49    : POD2CHIP_MDI2
	 * GPIO_50    : POD2CHIP_MDI3
	 * GPIO_51    : POD2CHIP_MDI4
	 * GPIO_52    : POD2CHIP_MDI5
	 */

	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6);

	reg &= ~(
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_46) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_47) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_48) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_49) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_50) |		
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_51) |		
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_52) 
			);
#if NEXUS_HAS_DVB_CI
	reg |=  BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_46, 1) |  /* POD2CHIP_MCLKI */
#else
		reg |=  BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_46, 3) |  /* EBI Addr 14 */
#endif
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_47, 1) |      /* POD2CHIP_MDI0 */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_48, 1) |      /* POD2CHIP_MDI1 */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_49, 1) |      /* POD2CHIP_MDI2 */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_50, 1) |      /* POD2CHIP_MDI3 */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_51, 1) |      /* POD2CHIP_MDI4 */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_52, 1) ;      /* POD2CHIP_MDI5 */        

	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6, reg);

	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7
	 * GPIO_53    : POD2CHIP_MDI6
	 * GPIO_54    : POD2CHIP_MDI7
	 * GPIO_55    : POD2CHIP_MISTRT
	 * GPIO_56    : POD2CHIP_MIVAL
	 * GPIO_57    : CHIP2POD_MCLKO
	 * GPIO_58    : CHIP2POD_MDO0
	 * GPIO_59    : CHIP2POD_MDO1
	 * GPIO_60    : CHIP2POD_MDO2
	 */

	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7);

	reg &= ~(
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_53) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_54) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_55) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_56) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_57) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_58) |		
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_59) |		
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_60) 				
			);

	reg |=  BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_53, 1) |  /* POD2CHIP_MDI6 */        
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_54, 1) |      /* POD2CHIP_MDI7 */        
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_55, 1) |      /* POD2CHIP_MISTRT */        
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_56, 1) |      /* POD2CHIP_MIVAL */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_57, 1) |      /* CHIP2POD_MCLKO */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_58, 1) |      /* CHIP2POD_MDO0 */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_59, 1) |      /* CHIP2POD_MDO1 */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_60, 1) ;      /* CHIP2POD_MDO2 */        

	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7, reg);

	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8
	 * GPIO_61    : CHIP2POD_MDO3
	 * GPIO_62    : CHIP2POD_MDO4
	 * GPIO_63    : CHIP2POD_MDO5
	 * GPIO_64    : CHIP2POD_MDO6
	 * GPIO_65    : CHIP2POD_MDO7
	 * GPIO_66    : CHIP2POD_MOSTRT
	 * GPIO_67    : CHIP2POD_MOVAL
	 * GPIO_68    : EBI_ADDR13
	 */

	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8);

	reg &= ~(
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_61) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_62) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_63) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_64) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_65) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_66) |		
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_67) |		
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_68) 
			);

	reg |=  BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_61, 1) |  /* CHIP2POD_MDO3 */        
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_62, 1) |      /* CHIP2POD_MDO4 */        
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_63, 1) |      /* CHIP2POD_MDO5 */        
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_64, 1) |      /* CHIP2POD_MDO6 */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_65, 1) |      /* CHIP2POD_MDO7 */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_66, 1) |      /* CHIP2POD_MOSTRT */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_67, 1) |      /* CHIP2POD_MOVAL */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_68, 3) ;      /* EBI Addr 13 */        

	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8, reg);

	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9
	 * GPIO_69    : EBI_ADDR12
	 * GPIO_70    : EBI_ADDR2
	 * GPIO_71    : EBI_ADDR1
	 * GPIO_72    : EBI_ADDR0
	 * GPIO_73    : MPOD_M_SDI
	 * GPIO_74    : RMX0_CLK
	 * GPIO_75    : RMX0_DATA
	 * GPIO_76    : RMX0_SYNC
	 */

	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9);

	reg &= ~(
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_69) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_70) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_71) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_72) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_73) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_74) |		
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_75) |		
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_76) 				
			);

	reg |=  BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_69, 3) |  /* EBI Addr 13 */        
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_70, 2) |      /* EBI Addr 2 */        
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_71, 2) |      /* EBI Addr 1 */        
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_72, 2) |      /* EBI Addr 0 */
#if NEXUS_HAS_DVB_CI
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_73, 1) ;      /* MPOD_M_SDI */
#else
	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_73, 1) |      /* MPOD_M_SDI */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_74, 1) |      /* RMX0_CLK */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_75, 1) |      /* RMX0_DATA */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_76, 1) ;      /* RMX0_SYNC */        
#endif

	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9, reg);

	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10
	 * GPIO_77    : RMX0_VALID
	 * GPIO_78    : RMX0_PAUSE
	 * GPIO_79    : SC0_VCC
	 * GPIO_80    : SC0_CLK
	 * GPIO_81    : SC0_RST
	 * GPIO_82    : SC0_IO
	 * GPIO_83    : SC0_PRES
	 * GPIO_84    : GPIO
	 */

	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10);

	reg &= ~(
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_77) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_78) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_79) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_80) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_81) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_82) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_83) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_84) 
			);

	reg |=  
#if !NEXUS_HAS_DVB_CI
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_77, 1) |  /* RMX0_VALID */        
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_78, 1) |      /* RMX0_PAUSE */    
#endif
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_79, 1) |      /* SC0_VCC */        
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_80, 1) |      /* SC0_CLK */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_81, 1) |      /* SC0_RST */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_82, 1) |      /* SC0_IO */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_83, 1) |      /* SC0_PRES */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_84, 0) ;      /* GPIO */

	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10, reg);

	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11
	 * GPIO_85    : GPIO
	 * GPIO_86    : SC_VPP
	 * GPIO_87    : UART_TX0
	 * GPIO_88    : UART_RX0
	 * GPIO_89    : ALT_TP_OUT_01
	 * GPIO_90    : ALT_TP_IN_01
	 * GPIO_91    : ALT_TP_OUT_02
	 * GPIO_92    : ALT_TP_IN_02
	 */

	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11);

	reg &= ~(
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_85) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_86) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_87) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_88) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_89) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_90) |		
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_91) |		
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_92) 
			);

	reg |=  BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_85, 0) |  /* GPIO */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_86, 1) |      /* SC_VPP */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_87, 2) |      /* UART_TX0 */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_88, 2) |      /* UART_RX0 */
#if NEXUS_HAS_DVB_CI
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_89, 4) |      /* POD_EBI_RDB */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_90, 4) |      /* POD_EBI_WE0B */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_91, 4) |      /* POD_EBI_DSB */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_92, 4) ;      /* POD2CHIP_MCLKI */  
#else
	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_89, 3) |      /* ALT_TP_OUT_01 */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_90, 3) |      /* ALT_TP_IN_01 */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_91, 3) |      /* ALT_TP_OUT_02 */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_92, 3) ;      /* ALT_TP_IN_02 */  
#endif


	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11, reg);

	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12
	 * GPIO_93    : SF_HOLDB
	 * GPIO_94    : SF_WPB
	 * GPIO_96    : PKT2_CLK
	 * GPIO_97     : PKT2_DATA
	 * GPIO_98     : PKT2_SYNC
	 * GPIO_99     : PKT2_VALID
	 * GPIO_100    : PKT2_ERROR
	 * GPIO_101    : default
	 */

	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12);

	reg &= ~(
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_93) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_94) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_96) |	
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_97) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_98) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_99) |		
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_100)
			);

	reg |=  BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_93, 1) | /* SF_HOLDB */ 
#if NEXUS_HAS_DVB_CI
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_94, 1);     /* SF_WPB */
#else
	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_94, 1) |     /* SF_WPB */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_96, 1) |     /* PKT2_CLK */            
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_97, 1) |     /* PKT2_DATA */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_98, 1) |     /* PKT2_SYNC */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_99, 1) |     /* PKT2_VALID */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_100, 1);     /* PKT2_ERROR */
#endif

	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12, reg);

	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13
	 * GPIO_102...GPIO_109: default
	 * GPIO_110: default EBI 
	 */

	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14
	 * GPIO_111...GPIO_118: default EBI 
	 */

	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15
	 * GPIO_123    : RGMII_MDC 
	 * GPIO_124    : RGMII_MDIO 
	 * SGPIO_00    : BSC_M0_SCL 
	 * SGPIO_01    : BSC_M0_SDA 
	 */

	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15);

	reg &= ~(
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_15, gpio_123) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_15, gpio_124) |		
#if BCHP_VER >= BCHP_VER_B0
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_02) |		
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_03) 
#else		
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_00) |		
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_01) 
#endif		
			);

	reg |=  BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_15, gpio_123, 1) |      /* RGMII_MDC */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_15, gpio_124, 1) |      /* RGMII_MDIO */
#if BCHP_VER >= BCHP_VER_B0
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_02, 1) |      /* BSC_M1_SCL */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_03, 1) ;      /* BSC_M1_SDA */   
#else
	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_00, 1) |      /* BSC_M0_SCL */
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_01, 1) ;      /* BSC_M0_SDA */        
#endif
	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15, reg);

#if BCHP_VER == BCHP_VER_A0
	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16
	 * SGPIO_02    : BSC_M1_SCL 
	 * SGPIO_03    : BSC_M1_SDA 
	 */

	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16);

	reg &= ~(
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_16, sgpio_02) |
			BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_16, sgpio_03)		
			);

	reg |=  BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_16, sgpio_02, 1) |  /* BSC_M1_SCL */        
		BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_16, sgpio_03, 1);       /* BSC_M1_SDA */            

	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16, reg);
#endif

	/* BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0
	 * AON_IR_IN0     : AON_IR_IN0(0)
	 * AON_S3_STANDBYB: AON_S3_STANDBYB(0)
	 * AON_HDMI_HTPLG : AON_HDMI_HTPLG(0)
	 * AON_GPIO_00    : AUD_SPDIF(1)
	 * AON_GPIO_01    : ENET_LINK(1)
	 * AON_GPIO_03    : LED_OUT(1)
	 * AON_GPIO_04    : I2S_CLK0_OUT(3)
	 * AON_GPIO_05    : I2S_DATA0_OUT(3)
	 */

	reg = BREG_Read32(hReg,BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0);

	reg &=~(
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_ir_in0 ) |
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_s3_standbyb ) |
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_hdmi_htplg ) |		
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_00 ) |
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_01 ) |
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_03 ) |
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_04 ) |
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_05 ) 
		   );

	reg |=( 
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_ir_in0, 0 ) |      /* AON_IR_IN0 */
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_s3_standbyb, 0 ) | /* AON_S3_STANDBYB */
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_hdmi_htplg, 0 ) | /* AON_HDMI_HTPLG */
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_00, 1 ) |     /* AUD_SPDIF */
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_01, 1 ) |     /* ENET_LINK */
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_03, 1 ) |     /* LED_OUT */
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_04, 3 ) |     /* I2S_CLK0_OUT */
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_05, 3 )       /* I2S_DATA0_OUT */
		  );

	BREG_Write32 (hReg, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0, reg);

	/* BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1
	 * AON_GPIO_06    : I2S_LR0_OUT(3)
	 * AON_GPIO_07    : CODEC_SDI(3)
	 * AON_GPIO_09    : CODEC_SCLK(3)
	 * AON_GPIO_10    : CODEC_SDO(3)
	 * AON_GPIO_11    : CODEC_MCLK(3)
	 */

	reg = BREG_Read32(hReg,BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1);

	reg &=~(
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_06 ) |
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_07 ) |
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_09 ) |
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_10 ) |
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_11 ) 
		   );

	reg |=( 
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_06, 3 ) |  /* I2S_LR0_OUT */
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_07, 3 ) |  /* CODEC_SDI */
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_09, 3 ) |  /* CODEC_SCLK */
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_10, 3 ) |  /* CODEC_SDO */
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_11, 3 )   /* CODEC_MCLK */
		  );

	BREG_Write32 (hReg, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1, reg);

	/* BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2
	 * AON_SGPIO_00   : BSC_M3_SCL(1)
	 */

	reg = BREG_Read32(hReg,BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2);

	if (1 /* (platformStatus.chipId == 0x7574) */)
	{
		/* AON_GPIO_20 is used for RFM switch on 7574 board, no SDIO interface */
		reg &=~(
				BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_2, aon_gpio_20 ) |
				BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_2, aon_sgpio_00 )
			   );
		reg |=(
				BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_2, aon_gpio_20, 0 ) |  /* AON_GPIO */
				BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_2, aon_sgpio_00,0 )    /* BSC_M3_SCL */
			  );
	}
	else
	{
		reg &=~(
				BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_2, aon_sgpio_00 )
			   );
		reg |=( 
				BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_2, aon_sgpio_00,1 )    /* BSC_M3_SCL */
			  );
	}

	BREG_Write32 (hReg, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2, reg);

	/* BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3
	 * AON_SGPIO_01   : BSC_M3_SDA(1)
	 */

	reg = BREG_Read32(hReg,BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3);

	reg &=~(
#if BCHP_VER >= BCHP_VER_B0
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_3, aon_sgpio_01 ) |		
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_3, sgpio_00) |
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_3, sgpio_01)
#else			
			BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_3, aon_sgpio_01 ) 
#endif		
		   );

	reg |=( 
#if BCHP_VER >= BCHP_VER_B0
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_3, aon_sgpio_01,0 ) |  /* BSC_M3_SDA */
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_3, sgpio_00,0 ) |		 /* BSC_M0_SCL */
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_3, sgpio_01,0 )		 /* BSC_M0_SDA */
#else			
			BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_3, aon_sgpio_01,1 )    /* BSC_M3_SDA */
#endif		
		  );

	BREG_Write32 (hReg, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3, reg);

	/* Configure the AVD UARTS to debug mode.  AVD0_OL -> UART1, AVD1_OL -> UART2. */
	reg = BREG_Read32(hReg, BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL);
	reg &= ~(BCHP_MASK(SUN_TOP_CTRL_UART_ROUTER_SEL, port_2_cpu_sel) | BCHP_MASK(SUN_TOP_CTRL_UART_ROUTER_SEL, port_1_cpu_sel));
	reg |= BCHP_FIELD_ENUM(SUN_TOP_CTRL_UART_ROUTER_SEL, port_2_cpu_sel, AVD0_OL);
	reg |= BCHP_FIELD_ENUM(SUN_TOP_CTRL_UART_ROUTER_SEL, port_1_cpu_sel, AVD0_IL);
	BREG_Write32(hReg,BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL,reg);

	reg = BREG_Read32(hReg, BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL);
	reg &= ~(BCHP_MASK(SUN_TOP_CTRL_TEST_PORT_CTRL, encoded_tp_enable));
	reg |= BCHP_FIELD_DATA(SUN_TOP_CTRL_TEST_PORT_CTRL,encoded_tp_enable, BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS);
	BREG_Write32(hReg, BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL, reg);

	/* Configure the Input Band source select options */
	/* DS->IB1; PKT2->IB2 */
	reg = BREG_Read32(hReg, BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0);
#if BCHP_VER >= BCHP_VER_B0	
	reg &= ~(BCHP_MASK(SUN_TOP_CTRL_GENERAL_CTRL_0, general_ctrl0_1));
	reg |= BCHP_FIELD_DATA(SUN_TOP_CTRL_GENERAL_CTRL_0,general_ctrl0_1, 1); /* PKT2 */
#else
	reg &= ~(BCHP_MASK(SUN_TOP_CTRL_GENERAL_CTRL_0, ib2_source));
	reg |= BCHP_FIELD_DATA(SUN_TOP_CTRL_GENERAL_CTRL_0,ib2_source, 1); /* PKT2 */
#endif
	BREG_Write32(hReg, BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0, reg);

	return BERR_SUCCESS;
}

BERR_Code gist_rap_open(uint32_t scm_id, scm_callback_t * scm_cb)
{
#if (BCHP_CHIP!=7552) /* [JPF] */
	BERR_Code berr;
	static BRAP_Settings rapSettings;

	/* Get the default RAP device settings */
	berr = BRAP_GetDefaultSettings(&rapSettings);
	BDBG_ASSERT(berr == BERR_SUCCESS);

	/* Allocate device memory for Raptor and fill up sRapSettings */
	rapSettings.bExtDeviceMem = false;
	rapSettings.pImgInterface = &BRAP_IMG_Interface;
	rapSettings.pImgContext = BRAP_IMG_Context;
	rapSettings.bIndOpVolCtrl = false;

	if(0 != scm_id){
		rapSettings.sScmSettings.bSCMEnabled = true;
	}else{
		rapSettings.sScmSettings.bSCMEnabled = false;
	}
	rapSettings.sScmSettings.ui32CaSystemId = scm_id;
	rapSettings.sScmSettings.pfCallbackOtpProgramming = scm_cb;

	/* Delay 300ms to avoid audio pop in BTSC output on startup on 97572 */
	BKNI_Sleep(400);

	berr = BRAP_Open(&(g_handles.hRap), GetCHP(), GetREG(), GetHEAP(), GetINT(), GetTMR(), &rapSettings);
	if(BERR_SUCCESS == berr){
		boutput_configure(); /* Configure audio outputs */
	}
	return berr;
#else
	return BERR_SUCCESS;
#endif
}

#include "bfdb.h"
#include "bspi_flash.h"
void gist_read_ca_info(uint32_t *scm_id)
{
#define FLASH_PAGE_SIZE 0x100
#define FLASH_SECTOR_SIZE	0x10000
#define FLASH_DB_SIZE 0x40000
#define FLASH_DB_OFFSET (0x400000 - FLASH_DB_SIZE)
#define MEM_DB_OFFSET 0
#define MEM_DB_SIZE FLASH_DB_SIZE

#define DB_CA_SYSTEM_ID	2 /* coming from bapp_settings.h */

	bfdb_err dberr;
	struct bfdb_settings dbset;
	bspi_settings_t spi_settings;
	bresult rc;
	bfdb_handle db;
	unsigned char db_data[12]; /* read until  EMM_Provider_ID */

	*scm_id = 0x4749;
	rc = bspi_identify(&spi_settings);
	BDBG_ASSERT(rc == b_ok);

	dbset.page_size = FLASH_PAGE_SIZE;
	dbset.sector_size = spi_settings.sector_size;
	dbset.db_offset = FLASH_DB_OFFSET;
	dbset.db_size = FLASH_DB_SIZE;

	dberr = bfdb_open(&dbset, &db);
	if(BFDB_OK != dberr){
		goto ExitFunc;
	}

	dberr = bfdb_rewind(db, DB_CA_SYSTEM_ID);
	if (BFDB_OK == dberr) {
		dberr = bfdb_get(db, db_data, 12);
		if (BFDB_OK != dberr) {
			BDBG_ERR(("Error:%d line:%d\n", dberr, __LINE__));
			goto ExitFunc;
		}
	}

	*scm_id = (db_data[9]<<8) | db_data[8];

ExitFunc:
	if (db) {
		bfds_close(db->store);
	}
	if (*scm_id != 0xe11 && *scm_id != 0x4749) 
		*scm_id = 0x4749;
}

void gist_flush_cache(const void *addr, size_t num)
{
	flush_dcache((unsigned long)addr, (unsigned long)((unsigned char *)addr+num));
}