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gist.c @ 2

Last change on this file since 2 was 2, checked in by phkim, 11 years ago

1.phkim

revision copy newcon3sk r27

Property svn:executable set to *

File size: 70.8 KB

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1	/***************************************************************************
2	* Copyright (c) 2003-2010, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: $
11	* $brcm_Revision: $
12	* $brcm_Date: $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: $
19	*
20	*
21	***************************************************************************/
22	#include "bstd.h"
23	#include "berr.h"
24	#include "bdbg.h"
25	#include "bkni.h"
26	#if (BCHP_CHIP==7552) /* [JPF] */
27	#include "bchp_7552.h"
28	#include "bchp_common.h"
29	#include "bint_7552.h"
30	#include "bchp_sun_top_ctrl.h"
31	#include "bchp_aon_pin_ctrl.h"
32	#else
33	#include "bchp_7550.h"
34	#include "bchp_common.h"
35	#include "bint_7550.h"
36	#include "btnr_7550.h"
37	#include "brap.h"
38	#include "brap_img.h"
39	#endif
40
41	#if (CONFIG_ENABLE_SCM == 1)
42	#include "scm_low.h"
43	#endif
44	#include "gist.h"
45	#include "bcm_mips_defs.h"
46
47	#if (BCHP_CHIP!=7552) /* [JPF] */
48	#include "bchp_ds_eq.h"
49	#include "bchp_ds_pll.h"
50	#include "bchp_ds_qafe_if_0.h"
51	#include "bchp_ds_qdsafe_0.h"
52	#include "bchp_ds_tuner_anactl.h"
53	#include "bchp_ds_tuner.h"
54	#include "bchp_ds.h"
55	#include "bchp_ds_tuner_ref.h"
56	#include "bchp_clk.h"
57	#include "bchp_vcxo_ctl_config_fsm.h"
58	#include "bchp_vcxo_ctl_misc.h"
59	#include "bchp_memc_ddr23_aphy_ac_0.h"
60	#endif
61	#include "bchp_gio.h"
62	#include "bchp_hif_cpu_intr1.h"
63	#include "bchp_genet_0_ext.h"
64	#include "bchp_clkgen.h"
65
66	/* includes for HD DTA POWER CONFIGURATION */
67
68	#include "bchp_misc.h"
69	#include "bchp_usb_ctrl.h"
70	#include "bchp_aio_misc.h"
71	#include "bchp_sun_top_ctrl.h"
72	#include "cache_util.h"
73
74	#ifdef CONFIG_MRC
75	/* memory checker */
76	#include "bmrc.h"
77	#include "bmrc_monitor.h"
78	BMRC_Handle mrc_handle;
79	BMRC_Monitor_Handle mrc_monitor_handle;
80	#endif
81
82	#if defined(ACB612) \|\| defined(ACB615)
83	#include "bos.h"
84	#include "bchp_misc.h"
85	#include "bchp_ufe_afe.h"
86	#include "bchp_ds.h"
87	#ifdef OOB_TUNER_SUPPORT
88	#include "bchp_obadc.h"
89	#include "bchp_oob.h"
90	#endif
91	#include "bchp_sdadc.h"
92	#if 0
93	#include "bchp_hdmi_tx_phy.h"
94	#endif
95	static void gist_power_down_modules(BREG_Handle hReg);
96	#endif
97	#include "bchp_memc_arb_0.h"
98
99	BDBG_MODULE(gist); /* Register software module with debug interface */
100	#ifdef BRAP /* [JPF] */
101	BRAP_AssociatedChanSettings sDecodeAssChSettings;
102	BRAP_AssociatedChanSettings sCompresseAssChSettings;
103	BRAP_DestinationHandle s_hMaiDstHandle = NULL;
104	BRAP_DestinationHandle s_hDacDstHandle = NULL;
105	BRAP_DestinationHandle s_hSpdifDstHandle = NULL;
106	BRAP_ProcessingStageHandle s_hBtscStageHandle = NULL;
107	void boutput_add_postprocessing(BRAP_ChannelHandle hRapCh);
108
109	void set_fm_deviation_value(int value);
110	#endif
111	void gist_flush_cache(const void *addr, size_t num);
112	static void gist_power_down_eth(BREG_Handle hReg);
113	#ifdef CONFIG_VSB
114	static void gist_config_vsb(BREG_Handle hReg);
115	#endif
116
117
118	#if (BCHP_CHIP==7552) /* [JPF] */
119	#ifdef ACB612 /* RLQ */
120
121	#ifdef CONFIG_AOV_SDRAM_1G/128/
122	//#define DEVICE_MEM_SIZE (11110241024) /* changed from 0x7600000 */
123	#define DEVICE_MEM_SIZE (9010241024) // 111MB->90MB megakiss
124	#else/256/
125	#define DEVICE_MEM_SIZE 0xD000000
126	#endif
127
128
129	#else
130	/* 256 MB DDR */
131	#define DEVICE_MEM_BASE 0x2000000
132	#define DEVICE_MEM_SIZE 0xD000000
133	#endif
134	#else
135	/* Defines for device heap. These may be better placed somewhere else later.
136	Heap start at 10MB and goes to 128MB. This ONLY works on 128MB board */
137	#define DEVICE_MEM_BASE 0xa00000
138	#define DEVICE_MEM_SIZE 0x6200000
139	#endif
140	void *g_heap_ptr = NULL;
141	struct bhandle_store_t g_handles;
142
143	static BERR_Code NEXUS_Platform_P_InitPinmux(BREG_Handle hReg);
144	static uint32_t s_L1Mask[BINT_MAX_INTC_SIZE] = { 0,0,0,0};
145	#define NUM_L1_STATUS ((BCHP_HIF_CPU_INTR1_INTR_W2_STATUS - BCHP_HIF_CPU_INTR1_INTR_W0_STATUS)/4)
146
147	void bint_handler(void)
148	{
149	int i;
150	uint32_t bit,status,mask_status;
151	for (i = 0; i <= NUM_L1_STATUS; ++i)
152	{
153	for (bit = 0; bit < 32; ++bit)
154	{
155	status = BREG_Read32(GetREG(),BCHP_HIF_CPU_INTR1_INTR_W0_STATUS + (i * 4));
156	mask_status = BREG_Read32(GetREG(),BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS + (i * 4));
157	if ((1UL << bit) & status & ~mask_status)
158	{
159	if (s_L1Mask[i] & (1UL << bit))
160	{
161	BDBG_MSG(("%s:%d(%d,%d)\n",__FUNCTION__,__LINE__,i,bit));
162
163	BINT_Isr(GetINT(),bit + (i * 32));
164	}
165	else
166	{
167	//RLQ
168	#if 0
169	#ifdef ACB612
170	void CPUINT1_Isr_ex(int bit);
171	if (BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT == bit && ((1UL << bit) & status)) {
172	CPUINT1_Isr_ex(bit);
173	}
174	else
175	#endif
176	#endif
177	BDBG_ERR(("%s:%d(%d,%d)-NOT HANDLED\n",__FUNCTION__,__LINE__,i,bit));
178	}
179	}
180	}
181	}
182	}
183	#ifdef BRAP /* [JPF] */
184	/* Configure HDMI output port */
185	static void boutput_configure_hdmi_port(BRAP_Handle hRap,
186	BRAP_OutputPort port)
187	{
188	BERR_Code errCode;
189	BRAP_OutputPortConfig outputSettings;
190
191	errCode = BRAP_GetDefaultOutputConfig(hRap, port, &outputSettings);
192	BDBG_ASSERT(BERR_SUCCESS == errCode);
193	/* Fill up output settings */
194	outputSettings.eOutputPort = port;
195	outputSettings.bCompressed = false;
196	outputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
197	outputSettings.uiOutputBitsPerSample = 24;
198	outputSettings.uOutputPortSettings.sMaiMultiSettings.eMClkRate = BRAP_OP_MClkRate_e256Fs;
199	errCode = BRAP_SetOutputConfig(hRap, &outputSettings);
200	/* This should never fail */
201	BDBG_ASSERT(BERR_SUCCESS == errCode);
202	}
203	/* Add output destinations for the decode association */
204	static void boutput_config_decode_outputs(void)
205	{
206	BERR_Code err;
207	BRAP_OutputPortDetails sOpDetails;
208	BRAP_OutputPortConfig sOutputSettings;
209	BRAP_DstDetails sDstDetails;
210	int i;
211
212	if (s_hDacDstHandle)
213	{
214	BRAP_RemoveDestination(g_handles.hDecodeAssociatedCh,s_hDacDstHandle);
215	}
216	if (s_hMaiDstHandle)
217	{
218	BRAP_RemoveDestination(g_handles.hDecodeAssociatedCh,s_hMaiDstHandle);
219	}
220	if (s_hSpdifDstHandle)
221	{
222	BRAP_RemoveDestination(g_handles.hDecodeAssociatedCh,s_hSpdifDstHandle);
223	}
224
225	for (i=0; i<BRAP_OutputChannelPair_eMax; i++)
226	{
227	sOpDetails.eOutput[i] = BRAP_OutputPort_eMax;
228	}
229
230	sOpDetails.eOutput[0] = BRAP_OutputPort_eDac0;
231	sOpDetails.eAudioMode =BRAP_OutputMode_e2_0;
232	sOpDetails.bLfeOn = false;
233	sOpDetails.bDownmixedOpPort = false;
234
235	err = BRAP_GetCurrentOutputConfig(GetRAP(), BRAP_OutputPort_eDac0, &sOutputSettings);
236	if (err != BERR_SUCCESS)
237	{
238	BDBG_ERR(("Get Current Settings for DAC0 Output failed %d",err));
239	return;
240	}
241	BDBG_MSG(("Default settings received for DAC0 Output"));
242
243	/* Fill up output settings */
244	sOutputSettings.eOutputPort = BRAP_OutputPort_eDac0;
245	sOutputSettings.bCompressed = false;
246	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
247	//sOutputSettings.iDelay = 20;
248
249	/* Configure output port */
250	err = BRAP_SetOutputConfig(GetRAP(), &sOutputSettings);
251	if (err != BERR_SUCCESS)
252	{
253	BDBG_MSG(("Set DAC0 output configuration failed %d", err));
254	return;
255	}
256	BDBG_ERR(("Set DAC0 output configuration done"));
257
258	sDstDetails.eAudioDst = BRAP_AudioDst_eOutputPort;
259	sDstDetails.uDstDetails.sOpDetails = sOpDetails;
260
261	err = BRAP_AddDestination(g_handles.hDecodeAssociatedCh, &sDstDetails, &s_hDacDstHandle);
262	BDBG_ASSERT (BERR_SUCCESS == err);
263
264
265	sOpDetails.eOutput[0] = BRAP_OutputPort_eMai;
266	sOpDetails.eAudioMode =BRAP_OutputMode_e2_0;
267	sOpDetails.bLfeOn = false;
268	sOpDetails.bDownmixedOpPort = false;
269
270	err = BRAP_GetCurrentOutputConfig(GetRAP(), BRAP_OutputPort_eMai, &sOutputSettings);
271	if (err != BERR_SUCCESS)
272	{
273	BDBG_ERR(("Get Current Settings for HDMI Output failed %d",err));
274	return;
275	}
276	BDBG_MSG(("Default settings received for HDMI Output"));
277
278	/* Fill up output settings */
279	sOutputSettings.eOutputPort = BRAP_OutputPort_eMai;
280	sOutputSettings.bCompressed = false;
281	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
282
283	//sOutputSettings.iDelay = 20;
284	err = BRAP_SetOutputConfig(GetRAP(), &sOutputSettings);
285	if (err != BERR_SUCCESS)
286	{
287	BDBG_MSG(("Set HDMI output configuration failed %d", err));
288	return;
289	}
290	BDBG_ERR(("Set HDMI output configuration done"));
291
292	sDstDetails.eAudioDst = BRAP_AudioDst_eOutputPort;
293	sDstDetails.uDstDetails.sOpDetails = sOpDetails;
294	#if 1
295	err = BRAP_AddDestination(g_handles.hDecodeAssociatedCh, &sDstDetails, &s_hMaiDstHandle);
296	BDBG_ASSERT (BERR_SUCCESS == err);
297	#endif
298	sOpDetails.eOutput[0] = BRAP_OutputPort_eSpdif;
299	sOpDetails.eAudioMode =BRAP_OutputMode_e2_0;
300	sOpDetails.bLfeOn = false;
301	sOpDetails.bDownmixedOpPort = false;
302
303	err = BRAP_GetCurrentOutputConfig(GetRAP(), BRAP_OutputPort_eSpdif, &sOutputSettings);
304	if (err != BERR_SUCCESS)
305	{
306	BDBG_ERR(("Get Current Settings for SPDIF Output failed %d",err));
307	return;
308	}
309	BDBG_MSG(("Default settings received for SPDIF Output"));
310
311	/* Fill up output settings */
312	sOutputSettings.eOutputPort = BRAP_OutputPort_eSpdif;
313	sOutputSettings.bCompressed = false;
314	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
315
316	//sOutputSettings.iDelay = 20;
317	err = BRAP_SetOutputConfig(GetRAP(), &sOutputSettings);
318	if (err != BERR_SUCCESS)
319	{
320	BDBG_MSG(("Set HDMI output configuration failed %d", err));
321	return;
322	}
323	BDBG_ERR(("Set SPDIF output configuration done (%d)", __LINE__));
324
325	sDstDetails.eAudioDst = BRAP_AudioDst_eOutputPort;
326	sDstDetails.uDstDetails.sOpDetails = sOpDetails;
327	#if 0
328	err = BRAP_AddDestination(g_handles.hDecodeAssociatedCh, &sDstDetails, &s_hSpdifDstHandle);
329	BDBG_ASSERT (BERR_SUCCESS == err);
330	#endif
331	}
332
333	static void boutput_config_compress_outputs(void)
334	{
335	BERR_Code err;
336	BRAP_OutputPortDetails sOpDetails;
337	BRAP_OutputPortConfig sOutputSettings;
338	BRAP_DstDetails sDstDetails;
339	int i;
340	#if 0
341	if (s_hMaiDstHandle)
342	{
343	BRAP_RemoveDestination(g_handles.hCompressedAssociatedCh, s_hMaiDstHandle);
344	}
345	#endif
346	for (i=0; i<BRAP_OutputChannelPair_eMax; i++)
347	{
348	sOpDetails.eOutput[i] = BRAP_OutputPort_eMax;
349	}
350
351	sOpDetails.eOutput[0] = BRAP_OutputPort_eMai;
352	sOpDetails.eAudioMode = BRAP_OutputMode_e2_0; // don't care for compression
353	sOpDetails.bLfeOn = false;
354	sOpDetails.bDownmixedOpPort = false;
355
356	err = BRAP_GetCurrentOutputConfig(GetRAP(), BRAP_OutputPort_eMai, &sOutputSettings);
357	if (err != BERR_SUCCESS)
358	{
359	BDBG_ERR(("Get Current Settings for HDMI Output failed %d (%d)", err, __LINE__));
360	return;
361	}
362	BDBG_MSG(("Default settings received for HDMI Output"));
363
364	/* Fill up output settings */
365	sOutputSettings.eOutputPort = BRAP_OutputPort_eMai;
366	sOutputSettings.bCompressed = true;
367	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
368
369	err = BRAP_SetOutputConfig(GetRAP(), &sOutputSettings);
370	if (err != BERR_SUCCESS)
371	{
372	BDBG_MSG(("Set HDMI output configuration failed %d", err));
373	return;
374	}
375	BDBG_ERR(("Set HDMI output configuration done"));
376
377	sDstDetails.eAudioDst = BRAP_AudioDst_eOutputPort;
378	sDstDetails.uDstDetails.sOpDetails = sOpDetails;
379
380	err = BRAP_AddDestination(g_handles.hCompressedAssociatedCh, &sDstDetails, &s_hMaiDstHandle);
381	BDBG_ASSERT(BERR_SUCCESS == err);
382	}
383
384	/* Configure all output ports for this board */
385	void boutput_configure(void)
386	{
387	BERR_Code ret = BERR_SUCCESS;
388	BRAP_OutputPortConfig sOutputSettings;
389	BRAP_Handle hRap = GetRAP();
390	static bool configured = false;
391	BDBG_ASSERT(hRap);
392
393	if (configured)
394	{
395	BDBG_WRN(("boutput_configure already completed"));
396	return;
397	}
398	BKNI_Memset(&sDecodeAssChSettings,0,sizeof(sDecodeAssChSettings));
399	BKNI_Memset(&sCompresseAssChSettings,0,sizeof(sCompresseAssChSettings));
400
401	boutput_configure_hdmi_port(hRap,BRAP_OutputPort_eMaiMulti0);
402	boutput_configure_hdmi_port(hRap,BRAP_OutputPort_eMaiMulti1);
403	boutput_configure_hdmi_port(hRap,BRAP_OutputPort_eMaiMulti2);
404	boutput_configure_hdmi_port(hRap,BRAP_OutputPort_eMaiMulti3);
405	BDBG_MSG(("MAI0-4 output configuration done"));
406
407	/* For the SPDIF output */
408	ret = BRAP_GetDefaultOutputConfig (hRap, BRAP_OutputPort_eSpdif, &sOutputSettings);
409	BDBG_ASSERT(BERR_SUCCESS == ret);
410
411	/* Fill up output settings */
412	sOutputSettings.eOutputPort = BRAP_OutputPort_eSpdif;
413	sOutputSettings.bCompressed = false;
414	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
415	sOutputSettings.uiOutputBitsPerSample = 24;
416	sOutputSettings.uOutputPortSettings.sSpdifSettings.eMClkRate = BRAP_OP_MClkRate_e256Fs; /* Slect MClkRate for SPDIF */
417	sOutputSettings.uOutputPortSettings.sSpdifSettings.ePll = BRAP_OP_Pll_ePll0; /* Slect PLL0 for SPDIF */
418	#if 0 /BRAP_INDEP_OP_DELAY_SUPPORTED/
419	sOutputSettings.bIndpDlyRqd = true;
420	sOutputSettings.iDelay = 16;
421	#endif
422
423	/* Configure SPDIF */
424	ret = BRAP_SetOutputConfig(hRap, &sOutputSettings);
425	BDBG_ASSERT(BERR_SUCCESS == ret);
426	BDBG_MSG(("SPDIF output configuration done"));
427
428	/* For the HDMI output */
429	ret = BRAP_GetDefaultOutputConfig (hRap, BRAP_OutputPort_eMai, &sOutputSettings);
430	BDBG_ASSERT(BERR_SUCCESS == ret);
431
432	/* Fill up output settings */
433	sOutputSettings.eOutputPort = BRAP_OutputPort_eMai;
434	sOutputSettings.bCompressed = false;
435	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
436	sOutputSettings.uiOutputBitsPerSample = 24;
437	sOutputSettings.uOutputPortSettings.sMaiSettings.eMClkRate = BRAP_OP_MClkRate_e256Fs; /* Slect MClkRate for MAI */
438	sOutputSettings.uOutputPortSettings.sMaiSettings.eMaiMuxSelector = BRAP_OutputPort_eMai;
439	sOutputSettings.uOutputPortSettings.sMaiSettings.eMaiAudioFormat = BRAP_OP_MaiAudioFormat_eSpdif2Channel;
440	// sOutputSettings.uOutputPortSettings.sMaiSettings.ePll = BRAP_OP_Pll_ePll0;
441
442	/* Configure MAI */
443	ret = BRAP_SetOutputConfig(hRap, &sOutputSettings);
444	BDBG_ASSERT(BERR_SUCCESS == ret);
445	BDBG_MSG(("MAI output configuration done"));
446
447	/* For DAC0 */
448	ret = BRAP_GetDefaultOutputConfig (hRap, BRAP_OutputPort_eDac0, &sOutputSettings);
449	BDBG_ASSERT(BERR_SUCCESS == ret);
450
451	/* Fill up output settings */
452	sOutputSettings.eOutputPort = BRAP_OutputPort_eDac0;
453	sOutputSettings.bCompressed = false;
454	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
455	sOutputSettings.uiOutputBitsPerSample = 24;
456	#if 0 /BRAP_INDEP_OP_DELAY_SUPPORTED/
457	sOutputSettings.bIndpDlyRqd = true;
458	sOutputSettings.iDelay = 16;
459	#endif
460
461	/* Configure the DAC output */
462	ret = BRAP_SetOutputConfig(hRap, &sOutputSettings);
463	BDBG_ASSERT(BERR_SUCCESS == ret);
464	BDBG_MSG(("DAC 0 output configuration done"));
465
466	configured = true;
467	}
468	/* Configure all output ports for this board */
469	void boutput_add_decode_association(BRAP_ChannelHandle hRapCh)
470	{
471	BERR_Code err;
472	unsigned int i;
473
474	BDBG_ASSERT(hRapCh);
475
476	BKNI_EnterCriticalSection();
477	if (g_handles.hDecodeAssociatedCh)
478	{
479	err = BRAP_DestroyAssociation(g_handles.hDecodeAssociatedCh);
480	BDBG_ASSERT(BERR_SUCCESS == err);
481	g_handles.hDecodeAssociatedCh = NULL;
482	}
483	for (i = 0; i < BRAP_MAX_ASSOCIATED_CHANNELS_IN_GRP; ++i)
484	{
485	if (sDecodeAssChSettings.sChDetail[i].hRapCh == NULL)
486	{
487	sDecodeAssChSettings.sChDetail[i].hRapCh = hRapCh;
488	break;
489	}
490	}
491	err = BRAP_CreateAssociation(&(g_handles.hDecodeAssociatedCh), &sDecodeAssChSettings);
492	BDBG_ASSERT(BERR_SUCCESS == err);
493	BKNI_LeaveCriticalSection();
494	boutput_config_decode_outputs();
495	boutput_add_postprocessing(hRapCh);
496
497	/* default is 1171, change to 1100 for the correct 25KHz full scale deviation */
498	set_fm_deviation_value(1100);
499
500	return;
501	}
502
503	void boutput_add_compress_association(BRAP_ChannelHandle hRapCh)
504	{
505	BERR_Code err;
506	unsigned int i;
507
508	BDBG_ASSERT(hRapCh);
509	BKNI_EnterCriticalSection();
510
511	if (g_handles.hCompressedAssociatedCh)
512	{
513	err = BRAP_DestroyAssociation(g_handles.hCompressedAssociatedCh);
514	BDBG_ASSERT(BERR_SUCCESS == err);
515	g_handles.hCompressedAssociatedCh = NULL;
516	}
517	for (i = 0; i <BRAP_MAX_ASSOCIATED_CHANNELS_IN_GRP; ++i)
518	{
519	if (sCompresseAssChSettings.sChDetail[i].hRapCh == NULL)
520	{
521	sCompresseAssChSettings.sChDetail[i].hRapCh = hRapCh;
522	break;
523	}
524	}
525	err = BRAP_CreateAssociation(&(g_handles.hCompressedAssociatedCh), &sCompresseAssChSettings);
526	BDBG_ASSERT(BERR_SUCCESS == err);
527	BKNI_LeaveCriticalSection();
528	// boutput_config_compress_outputs();
529	// boutput_add_postprocessing(hRapCh);
530	return;
531	}
532
533	void boutput_remove_decode_mai_output(void)
534	{
535	if (s_hMaiDstHandle)
536	{
537	BRAP_RemoveDestination(g_handles.hDecodeAssociatedCh,s_hMaiDstHandle);
538	}
539	}
540
541	void boutput_remove_compress_mai_output(void)
542	{
543	if (s_hMaiDstHandle)
544	{
545	BRAP_RemoveDestination(g_handles.hCompressedAssociatedCh,s_hMaiDstHandle);
546	}
547	}
548	void boutput_add_compress_mai_output(void)
549	{
550	boutput_config_compress_outputs();
551	}
552
553	void boutput_add_decode_mai_output(void)
554	{
555	BERR_Code err;
556	BRAP_OutputPortDetails sOpDetails;
557	BRAP_OutputPortConfig sOutputSettings;
558	BRAP_DstDetails sDstDetails;
559	int i;
560
561	for (i=0; i<BRAP_OutputChannelPair_eMax; i++)
562	{
563	sOpDetails.eOutput[i] = BRAP_OutputPort_eMax;
564	}
565
566	sOpDetails.eOutput[0] = BRAP_OutputPort_eMai;
567	sOpDetails.eAudioMode = BRAP_OutputMode_e2_0;
568	sOpDetails.bLfeOn = false;
569	sOpDetails.bDownmixedOpPort = false;
570	err = BRAP_GetCurrentOutputConfig(GetRAP(), BRAP_OutputPort_eMai, &sOutputSettings);
571	if (err != BERR_SUCCESS)
572	{
573	BDBG_ERR(("Get Current Settings for HDMI Output failed %d (%d)", err, __LINE__));
574	return;
575	}
576	BDBG_MSG(("Defailt settings received for HDMI Output"));
577
578	/* Fill up output settings */
579	sOutputSettings.eOutputPort = BRAP_OutputPort_eMai;
580	sOutputSettings.bCompressed = false;
581	sOutputSettings.eOutputSR = BAVC_AudioSamplingRate_e48k;
582
583	err = BRAP_SetOutputConfig(GetRAP(), &sOutputSettings);
584	if (err != BERR_SUCCESS)
585	{
586	BDBG_ERR(("Set HDMI output configuration failed %d (%d)", err, __LINE__));
587	return;
588	}
589	BDBG_ERR(("Set HDMI output configuration done"));
590	sDstDetails.eAudioDst = BRAP_AudioDst_eOutputPort;
591	sDstDetails.uDstDetails.sOpDetails = sOpDetails;
592	err = BRAP_AddDestination(g_handles.hDecodeAssociatedCh, &sDstDetails, &s_hMaiDstHandle);
593	if (err != BERR_SUCCESS)
594	{
595	BDBG_ERR(("Set AddDestination failed: %d(%d)", err, __LINE__));
596	return;
597	}
598	}
599	/* Configure all output ports for this board */
600	void boutput_remove_decode_association(BRAP_ChannelHandle hRapCh)
601	{
602	BERR_Code err;
603	int i,cnt;
604	BRAP_AssociatedChanSettings tmpAssSettings;
605
606	BDBG_ASSERT(hRapCh);
607	BDBG_ASSERT(g_handles.hDecodeAssociatedCh);
608
609	BKNI_EnterCriticalSection();
610	cnt = 0;
611	BKNI_Memset(&tmpAssSettings,0,sizeof(tmpAssSettings));
612	for (i = 0; i < BRAP_MAX_ASSOCIATED_CHANNELS_IN_GRP; ++i)
613	{
614	if (sDecodeAssChSettings.sChDetail[i].hRapCh && (sDecodeAssChSettings.sChDetail[i].hRapCh != hRapCh))
615	{
616	tmpAssSettings.sChDetail[cnt].hRapCh = sDecodeAssChSettings.sChDetail[i].hRapCh;
617	cnt++;
618	}
619	sDecodeAssChSettings.sChDetail[i].hRapCh = NULL;
620	}
621	BKNI_Memcpy(&sDecodeAssChSettings,&tmpAssSettings,sizeof(sDecodeAssChSettings));
622	err = BRAP_DestroyAssociation(g_handles.hDecodeAssociatedCh);
623	BDBG_ASSERT(BERR_SUCCESS == err);
624	g_handles.hDecodeAssociatedCh = NULL;
625
626	err = BRAP_CreateAssociation(&(g_handles.hDecodeAssociatedCh), &sDecodeAssChSettings);
627	BDBG_ASSERT(BERR_SUCCESS == err);
628	BKNI_LeaveCriticalSection();
629
630	boutput_config_decode_outputs();
631	return;
632	}
633	void boutput_remove_compress_association(BRAP_ChannelHandle hRapCh)
634	{
635	BERR_Code err;
636	int i,cnt;
637	BRAP_AssociatedChanSettings tmpAssSettings;
638
639	BDBG_ASSERT(hRapCh);
640	BDBG_ASSERT(g_handles.hCompressedAssociatedCh);
641
642	BKNI_EnterCriticalSection();
643	cnt = 0;
644	BKNI_Memset(&tmpAssSettings, 0, sizeof(tmpAssSettings));
645	for (i = 0; i < BRAP_MAX_ASSOCIATED_CHANNELS_IN_GRP; ++i)
646	{
647	if (sCompresseAssChSettings.sChDetail[i].hRapCh && (sCompresseAssChSettings.sChDetail[i].hRapCh != hRapCh))
648	{
649	tmpAssSettings.sChDetail[cnt].hRapCh = sCompresseAssChSettings.sChDetail[i].hRapCh;
650	cnt++;
651	}
652	sCompresseAssChSettings.sChDetail[i].hRapCh = NULL;
653	}
654	BKNI_Memcpy(&sCompresseAssChSettings,&tmpAssSettings,sizeof(sDecodeAssChSettings));
655	err = BRAP_DestroyAssociation(g_handles.hCompressedAssociatedCh);
656	BDBG_ASSERT(BERR_SUCCESS == err);
657	g_handles.hCompressedAssociatedCh = NULL;
658
659	err = BRAP_CreateAssociation(&(g_handles.hCompressedAssociatedCh), &sCompresseAssChSettings);
660	BDBG_ASSERT(BERR_SUCCESS == err);
661	BKNI_LeaveCriticalSection();
662
663	boutput_config_compress_outputs();
664	return;
665	}
666
667	void boutput_add_postprocessing(BRAP_ChannelHandle hRapCh)
668	{
669	BRAP_ProcessingStageSettings sProcessingStageSettings;
670	BRAP_ProcessingSettings sStgSettings;
671	BERR_Code err;
672
673	BDBG_ASSERT(hRapCh);
674	BDBG_ASSERT(s_hDacDstHandle);
675
676	if (s_hBtscStageHandle)
677	{
678	BRAP_DestroyProcessingStage(s_hBtscStageHandle);
679	s_hBtscStageHandle = NULL;
680	}
681	err = BRAP_GetDefaultProcessingStageSettings( BRAP_ProcessingType_eBtsc, &sProcessingStageSettings );
682	BDBG_ASSERT (BERR_SUCCESS == err);
683	sProcessingStageSettings.uConfigParams.sBTSCParams.bUseDeEmphasizedSourceSignals = false;
684
685	sProcessingStageSettings.uConfigParams.sBTSCParams.bSumChanFreqDevCtrl = true; /Default Enable: Used to Control FM Deviation of Sum Channel to 25Khz/
686	sProcessingStageSettings.uConfigParams.sBTSCParams.bDiffChanFreqDevCtrl = true; /Default Enable: Used to Control FM Deviation of Diff Channel to 50Khz/
687	sProcessingStageSettings.uConfigParams.sBTSCParams.bOpFreqDevCtrl = true; /Default Enable: Used to Control FM Deviation of Final Output to 50Khz/
688
689	sProcessingStageSettings.uConfigParams.sBTSCParams.bFreqGeneration = false; /Default Disable: Used to Generate Test Tones/
690	sProcessingStageSettings.uConfigParams.sBTSCParams.ui32Frequency = 0; /Default 0 generates frequency sweep. Programming to a fixed value generates tone/
691	sProcessingStageSettings.uConfigParams.sBTSCParams.ui32SRDCalibrationFactor = 1100;
692
693	err = BRAP_CreateProcessingStage(GetRAP(),&sProcessingStageSettings, &s_hBtscStageHandle );
694	BDBG_ASSERT (BERR_SUCCESS == err);
695	err = BRAP_GetDefaultPostProcessingStages( &sStgSettings );
696	BDBG_ASSERT (BERR_SUCCESS == err);
697	sStgSettings.hAudProcessing[0] = s_hBtscStageHandle;
698
699	err = BRAP_SetPostProcessingStages( s_hDacDstHandle, hRapCh, &sStgSettings );
700	BDBG_ASSERT (BERR_SUCCESS == err);
701	}
702	void boutput_set_postprocessing_volume(int volume)
703	{
704	BRAP_ProcessingStageSettings sProcessingStageSettings;
705	BERR_Code err;
706
707	BDBG_ASSERT(s_hBtscStageHandle);
708
709	err = BRAP_GetCurrentProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
710	BDBG_ASSERT (BERR_SUCCESS == err);
711
712	BDBG_ERR(("boutput_set_postprocessing_volume = %d", volume));
713
714	sProcessingStageSettings.uConfigParams.sBTSCParams.uiVolumeLevel = volume;
715	sProcessingStageSettings.uConfigParams.sBTSCParams.bBTSCEnableFlag = true;
716	sProcessingStageSettings.eAudioProcessing = BRAP_ProcessingType_eBtsc;
717
718	err = BRAP_SetProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
719	BDBG_ASSERT (BERR_SUCCESS == err);
720	}
721
722	int get_fm_deviation_value()
723	{
724	BRAP_ProcessingStageSettings sProcessingStageSettings;
725	BERR_Code err;
726
727	if (!s_hBtscStageHandle)
728	return 0;
729
730	err = BRAP_GetCurrentProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
731	BDBG_ASSERT (BERR_SUCCESS == err);
732
733	return sProcessingStageSettings.uConfigParams.sBTSCParams.ui32SRDCalibrationFactor;
734	}
735	void set_fm_deviation_value(int value)
736	{
737	BRAP_ProcessingStageSettings sProcessingStageSettings;
738	BERR_Code err;
739
740	if (!s_hBtscStageHandle)
741	return;
742
743	err = BRAP_GetCurrentProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
744	BDBG_ASSERT (BERR_SUCCESS == err);
745
746	BDBG_ERR(("set_fm_deviation_value = %d", value));
747
748	sProcessingStageSettings.uConfigParams.sBTSCParams.ui32SRDCalibrationFactor = value;
749	sProcessingStageSettings.eAudioProcessing = BRAP_ProcessingType_eBtsc;
750
751	err = BRAP_SetProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
752	BDBG_ASSERT (BERR_SUCCESS == err);
753	}
754
755
756	void boutput_set_postprocessing_deemphasized(bool enable)
757	{
758	BRAP_ProcessingStageSettings sProcessingStageSettings;
759	BERR_Code err;
760
761	BDBG_ASSERT(s_hBtscStageHandle);
762
763	err = BRAP_GetCurrentProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
764	BDBG_ASSERT (BERR_SUCCESS == err);
765	// Enabled by default but needs to be disabled in normal operations.
766	sProcessingStageSettings.uConfigParams.sBTSCParams.bUseDeEmphasizedSourceSignals = enable;
767	BDBG_ERR(("boutput_set_postprocessing_deemphasized = %d", enable));
768
769	err = BRAP_SetProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
770	BDBG_ASSERT (BERR_SUCCESS == err);
771	}
772
773	void boutput_set_postprocessing_preemphasized(bool enable)
774	{
775	BRAP_ProcessingStageSettings sProcessingStageSettings;
776	BERR_Code err;
777
778	BDBG_ASSERT(s_hBtscStageHandle);
779
780	err = BRAP_GetCurrentProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
781	BDBG_ASSERT (BERR_SUCCESS == err);
782	// Enabled by default but needs to be disabled in normal operations.
783	sProcessingStageSettings.uConfigParams.sBTSCParams.bMainChannelPreEmphasisOn = enable;
784	sProcessingStageSettings.uConfigParams.sBTSCParams.bDiffChannelPreEmphasisOn = enable;
785
786	BDBG_ERR(("boutput_set_postprocessing_preemphasized = %d", enable));
787
788	err = BRAP_SetProcessingStageSettings( s_hBtscStageHandle, &sProcessingStageSettings );
789	BDBG_ASSERT (BERR_SUCCESS == err);
790	}
791
792
793	BERR_Code boutput_set_association_vol(BRAP_OutputPort eOpType, unsigned int iLVol, unsigned int iRVol)
794	{
795	BERR_Code err = BERR_NOT_INITIALIZED;
796
797	/* TODO current Mai only, will add other if needed */
798	if ((BRAP_OutputPort_eMai == eOpType) && s_hMaiDstHandle)
799	{
800	err = BRAP_SetDestinationVolume(s_hMaiDstHandle, iLVol, iRVol);
801	}
802	else {
803	BDBG_ERR(("null s_hMaiDstHandle"));
804	}
805	return err;
806	}
807
808	BERR_Code boutput_set_association_mute(BRAP_OutputPort eOpType, bool bMute)
809	{
810	BERR_Code err = BERR_NOT_INITIALIZED;
811
812	/* TODO current Mai only, will add other if needed */
813	if ((BRAP_OutputPort_eMai == eOpType) && s_hMaiDstHandle)
814	{
815	err = BRAP_SetDestinationMute(s_hMaiDstHandle, bMute);
816	}
817	else {
818	BDBG_ERR(("null s_hMaiDstHandle"));
819	}
820	return err;
821	}
822	#else
823	int get_fm_deviation_value()
824	{
825	return 0;
826	}
827	void set_fm_deviation_value(int value)
828	{
829	}
830	#endif
831	void gist_init(void)
832	{
833	BERR_Code berr;
834	static BTMR_DefaultSettings tmr_settings;
835	static BMEM_Settings mem_settings;
836	static BMEM_Heap_Settings heap_settings;
837	static BXPT_DefaultSettings xpt_settings;
838	static BXPT_Rave_ChannelSettings raveSettings;
839	static BXVD_Settings xvdSettings;
840	static BXVD_ChannelSettings xvdChannelSettings;
841	static BXPT_PCR_DefSettings pcrSettings;
842	int i;
843
844	BREG_Open(&g_handles.hReg, (void*)BCM_PHYS_TO_KSEG1(BCHP_PHYSICAL_OFFSET), BCHP_REGISTER_END);
845	#if (BCHP_CHIP==7552) /* [JPF] */
846	berr = BCHP_Open7552(&g_handles.hChp, GetREG());
847	BDBG_ASSERT(BERR_SUCCESS == berr);
848
849	berr = BINT_Open(&g_handles.hInt, GetREG(), BINT_7552_GetSettings());
850	#else
851	berr = BCHP_Open7550(&g_handles.hChp, GetREG());
852	BDBG_ASSERT(BERR_SUCCESS == berr);
853
854	berr = BINT_Open(&g_handles.hInt, GetREG(), BINT_7550_GetSettings());
855	#endif
856	BDBG_ASSERT(BERR_SUCCESS == berr);
857
858	BINT_GetL1BitMask(GetINT(), s_L1Mask);
859	for (i = 0; i <= NUM_L1_STATUS; ++i)
860	{
861	BREG_Write32(GetREG(),BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR + (i * 4),s_L1Mask[i]);
862	}
863	berr = BTMR_GetDefaultSettings(&tmr_settings);
864	BDBG_ASSERT(BERR_SUCCESS == berr);
865
866	berr = BTMR_Open(&g_handles.hTmr, GetCHP(), GetREG(), GetINT(), &tmr_settings);
867	BDBG_ASSERT(BERR_SUCCESS == berr);
868
869	berr = BMEM_GetDefaultSettings(&mem_settings);
870	BDBG_ASSERT(BERR_SUCCESS == berr);
871
872	berr = BMEM_Open(&g_handles.hMem, &mem_settings);
873	BDBG_ASSERT(BERR_SUCCESS == berr);
874
875	berr = BMEM_Heap_GetDefaultSettings(&heap_settings);
876	BDBG_ASSERT(BERR_SUCCESS == berr);
877	#ifdef BCM_DEBUG
878	heap_settings.eSafetyConfig = BMEM_SafetyConfig_eSafe;
879	#endif
880	g_heap_ptr = (void *)BCM_PHYS_TO_KSEG1(BKNI_Malloc(DEVICE_MEM_SIZE));
881
882	heap_settings.pCachedAddress = (void *)BCM_PHYS_TO_KSEG0(BCM_CPU_TO_PHYS(g_heap_ptr));
883	heap_settings.flush = gist_flush_cache;
884	heap_settings.flush_isr = gist_flush_cache;
885
886	berr = BMEM_Heap_Create(GetMEM(), (void*)g_heap_ptr, BCM_CPU_TO_PHYS(g_heap_ptr), DEVICE_MEM_SIZE, &heap_settings, &g_handles.hHeap);
887	BDBG_ASSERT(BERR_SUCCESS == berr);
888
889	#if 0
890	#ifdef CONFIG_MRC
891	{
892	BERR_Code rc;
893	static BMEM_MonitorInterface interface;
894	BMRC_Settings mrcSettings;
895	BMRC_Monitor_Settings monitorSettings;
896
897	rc = BMRC_GetDefaultSettings(&mrcSettings);
898	BDBG_ASSERT(!rc);
899	rc = BMRC_Open(&mrc_handle, GetREG(), GetINT(), &mrcSettings);
900	BDBG_ASSERT(!rc);
901	BMRC_Monitor_GetDefaultSettings(&monitorSettings);
902	BDBG_ASSERT(!rc);
903	rc = BMRC_Monitor_Open(&mrc_monitor_handle, GetREG(), GetINT(), GetCHP(), mrc_handle, 0, 128 * 1024 * 1024, &monitorSettings);
904	BDBG_ASSERT(!rc);
905	rc = BMRC_Monitor_GetMemoryInterface(mrc_monitor_handle, &interface);
906	BDBG_ASSERT(!rc);
907	rc = BMEM_InstallMonitor(GetHEAP(), &interface);
908	BDBG_ASSERT(!rc);
909	}
910	#endif
911	#endif
912
913	#if defined(ACB612) \|\| defined(ACB615)
914	{
915	uint32_t reg;
916
917	reg = 0x00182003;
918	BREG_Write32(GetREG(), BCHP_MEMC_ARB_0_CLIENT_INFO_25, reg);
919	reg = 0x00142001;
920	BREG_Write32(GetREG(), BCHP_MEMC_ARB_0_CLIENT_INFO_53, reg);
921	reg = 0x0011b000;
922	BREG_Write32(GetREG(), BCHP_MEMC_ARB_0_CLIENT_INFO_61, reg);
923	reg = 0x002f4007;
924	BREG_Write32(GetREG(), BCHP_MEMC_ARB_0_CLIENT_INFO_74, reg);
925	//reg = 0x00179001;
926	//BREG_Write32(GetREG(), BCHP_MEMC_ARB_0_CLIENT_INFO_75, reg);
927	reg = 0x001d7004;
928	BREG_Write32(GetREG(), BCHP_MEMC_ARB_0_CLIENT_INFO_80, reg);
929	/* MFD0 RTS change from 0x002F6007 */
930	reg = 0x00238006;
931	BREG_Write32(GetREG(), BCHP_MEMC_ARB_0_CLIENT_INFO_60, reg);
932	}
933	#endif
934
935	#if (CONFIG_ENABLE_SCM == 1)
936	/* this must be done before XPT initialization
937	but after mem and reg initialization */
938	berr = scml_decrypt();
939	BDBG_ASSERT(BERR_SUCCESS == berr);
940	#endif
941	berr = BXPT_GetDefaultSettings(&xpt_settings, GetCHP());
942	BDBG_ASSERT(BERR_SUCCESS == berr);
943	xpt_settings.BandwidthConfig.MaxInputRate[0] = 50000000;
944	#ifdef OOB_TUNER_SUPPORT
945	xpt_settings.BandwidthConfig.MaxInputRate[OOB_TUNER_BAND] = 10000000;
946	#endif
947	berr = BXPT_Open(&g_handles.hXpt, GetCHP(), GetREG(), GetHEAP(), GetINT(), &xpt_settings);
948	BDBG_ASSERT(BERR_SUCCESS == berr);
949
950	BXPT_PCR_GetChannelDefSettings(GetXPT(),0 , &pcrSettings);
951	berr = BXPT_PCR_Open(GetXPT(), 0, &pcrSettings,&(g_handles.hDPCR));
952	BDBG_ASSERT(BERR_SUCCESS == berr);
953
954	berr = BXPT_SetParserDataSource(GetXPT(), 0, BXPT_DataSource_eInputBand, PARSER_BAND/ADS input /);
955	BDBG_ASSERT(BERR_SUCCESS == berr);
956
957	berr = BXPT_SetParserEnable(GetXPT(), 0, true);
958	BDBG_ASSERT(BERR_SUCCESS == berr);
959
960	#ifdef OOB_TUNER_SUPPORT
961	/* use PID parser 1 for OOB CA/SI... data, NOTE that OOB_IB and OOB_TUNER_BAND are defined in makefile */
962	berr = BXPT_SetParserDataSource(GetXPT(), OOB_TUNER_BAND, BXPT_DataSource_eInputBand, OOB_IB);
963	BDBG_ASSERT(BERR_SUCCESS == berr);
964
965	berr = BXPT_SetParserEnable(GetXPT(), OOB_TUNER_BAND, true);
966	BDBG_ASSERT(BERR_SUCCESS == berr);
967	#endif
968
969	berr = BXPT_Rave_GetChannelDefaultSettings(GetXPT(),0,&raveSettings);
970	BDBG_ASSERT(BERR_SUCCESS == berr);
971
972
973	berr = BXPT_Rave_OpenChannel(GetXPT(),&g_handles.hRave,0, &raveSettings);
974	BDBG_ASSERT(BERR_SUCCESS == berr);
975
976
977	NEXUS_Platform_P_InitPinmux(GetREG());
978
979	#if defined(ACB612) \|\| defined(ACB615)
980	gist_power_down_modules(GetREG());
981	#endif
982
983	#ifndef CONFIG_LWIP_TEST
984	gist_power_down_eth(GetREG());
985	#endif
986
987	#ifdef CONFIG_VSB
988	gist_config_vsb(GetREG());
989	#endif
990
991	berr = BI2C_Open( &(g_handles.hI2c),GetCHP(), GetREG(), GetINT(), (BI2C_Settings *)NULL );
992	BDBG_ASSERT(BERR_SUCCESS == berr);
993
994
995	/* Open the decoder channel and hook up interrupts before opening video windows */
996	BXVD_GetDefaultSettings(&xvdSettings);
997
998	berr = BXVD_Open(&(g_handles.hXvd),GetCHP(),GetREG(),NULL,GetHEAP(),GetINT(),&xvdSettings);
999	BDBG_ASSERT(berr == BERR_SUCCESS);
1000
1001	BXVD_GetChannelDefaultSettings(g_handles.hXvd, 0, &xvdChannelSettings);
1002	berr= BXVD_OpenChannel(g_handles.hXvd,&(g_handles.hXvdCh),0,&xvdChannelSettings);
1003	BDBG_ASSERT(berr == BERR_SUCCESS);
1004
1005	berr = BGIO_Open(&g_handles.hGio, GetCHP(), GetREG());
1006	BDBG_ASSERT(BERR_SUCCESS == berr);
1007	}
1008
1009	#if defined(ACB612) \|\| defined(ACB615)
1010	static void gist_power_down_modules(BREG_Handle hReg)
1011	{
1012	uint32_t reg;
1013
1014	/* power down USB 0 and 1 */
1015	reg = BREG_Read32(hReg,BCHP_USB_CTRL_UTMI_CTL_1);
1016	reg &= ~(BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK \|
1017	BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK);
1018	BREG_Write32 (hReg, BCHP_USB_CTRL_UTMI_CTL_1, reg);
1019
1020	reg = BREG_Read32(hReg,BCHP_USB_CTRL_PLL_CTL);
1021	reg &= ~(BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK
1022	);
1023	reg \|= (BCHP_USB_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK
1024	);
1025	BREG_Write32 (hReg, BCHP_USB_CTRL_PLL_CTL, reg);
1026
1027	reg = BREG_Read32(hReg,BCHP_CLKGEN_USB_CLOCK_DISABLE);
1028	reg \|= (BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK
1029	);
1030	BREG_Write32 (hReg, BCHP_CLKGEN_USB_CLOCK_DISABLE, reg);
1031
1032	reg = BREG_Read32(hReg,BCHP_CLKGEN_USB_CLOCK_ENABLE);
1033	reg &= ~(BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK \|
1034	BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK
1035	);
1036	BREG_Write32 (hReg, BCHP_CLKGEN_USB_CLOCK_ENABLE, reg);
1037
1038	/* some registers can be set only in atomic manner */
1039	/* smart card 0 and 1 */
1040	reg = BREG_Read32(hReg,BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE);
1041	reg \|= (BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK \|
1042	BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK
1043	);
1044	BREG_AtomicUpdate32 (hReg, BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE, reg, reg);
1045
1046	reg = BREG_Read32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0);
1047	reg \|= (BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK \|
1048	BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK);
1049	/* need to be atomic */
1050	BREG_AtomicUpdate32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0, reg, reg);
1051
1052	reg = BREG_Read32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1);
1053	reg \|= (BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK \|
1054	BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK);
1055	/* need to be atomic */
1056	BREG_AtomicUpdate32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1, reg, reg);
1057
1058	/* PLL channel2 - 184 MHz TS clock */
1059	//reg = BREG_Read32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2);
1060	//reg \|= (BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK);
1061	//BREG_Write32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2, reg);
1062
1063	//Æ¯Á¤ stream¿¡¼ audio tick-noise patch code. KHW140507
1064	/RLQ, increase audio DSP frequency for handling higher bit rate AC3 audio /
1065	reg = BREG_Read32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3);
1066	reg &= ~BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK;
1067	/* change from default 0x32 to 8 */
1068	reg \|= (8L << BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT);
1069	BREG_Write32(hReg, BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_3, reg);
1070
1071	/* power down SYS1 PLL output channel5 - 225MHz TS clock */
1072	reg = BREG_Read32(hReg, BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5);
1073	reg \|= (BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK
1074	);
1075	//BREG_Write32(hReg, BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5, reg);
1076
1077	reg = BREG_Read32(hReg, BCHP_CLKGEN_PAD_CLOCK_DISABLE);
1078	reg \|= (BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_SC_OUT_CLOCK_MASK
1079	);
1080	//BREG_Write32(hReg, BCHP_CLKGEN_PAD_CLOCK_DISABLE, reg);
1081
1082	/* ACB615 has HDMI output so don't power the module if for ACB615 build */
1083	#ifndef ACB615
1084	/* DVP HDMI */
1085	reg = BREG_Read32(hReg, BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3);
1086	reg \|= (BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK
1087	);
1088	BREG_Write32(hReg, BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3, reg);
1089
1090	#if 0
1091	reg = BREG_Read32(hReg, BCHP_HDMI_TX_PHY_POWERDOWN_CTL);
1092	reg \|= (BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_0_PWRDN_MASK \|
1093	BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_1_PWRDN_MASK \|
1094	BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_2_PWRDN_MASK \|
1095	BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_CK_PWRDN_MASK \|
1096	BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_RNDGEN_PWRDN_MASK \|
1097	BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_PLL_PWRDN_MASK \|
1098	BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_BIAS_PWRDN_MASK \|
1099	BCHP_HDMI_TX_PHY_POWERDOWN_CTL_TX_PHY_PWRDN_MASK
1100	);
1101	BREG_Write32(hReg, BCHP_HDMI_TX_PHY_POWERDOWN_CTL, reg);
1102	#endif
1103
1104	reg = BREG_Read32(hReg, BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE);
1105	reg \|= (BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK
1106	);
1107	BREG_Write32(hReg, BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE, reg);
1108
1109	reg = BREG_Read32(hReg, BCHP_CLKGEN_DVP_HT_ENABLE);
1110	reg &= ~(BCHP_CLKGEN_DVP_HT_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK
1111	);
1112	BREG_AtomicUpdate32(hReg, BCHP_CLKGEN_DVP_HT_ENABLE, reg, reg);
1113
1114	reg = BREG_Read32(hReg, BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE);
1115	reg &= ~(BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK \|
1116	BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK \|
1117	BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK \|
1118	BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK
1119	);
1120	BREG_AtomicUpdate32(hReg, BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE, reg, reg);
1121	#endif
1122
1123	/* DAC */
1124	reg = BREG_Read32(hReg, BCHP_MISC_DAC_CTRL_0);
1125	reg \|= (BCHP_MISC_DAC_CTRL_0_DAC1_PWRDN_MASK \|
1126	BCHP_MISC_DAC_CTRL_0_DAC2_PWRDN_MASK \|
1127	BCHP_MISC_DAC_CTRL_0_DAC3_PWRDN_MASK
1128	);
1129	BREG_Write32(hReg, BCHP_MISC_DAC_CTRL_0, reg);
1130
1131	#if 0
1132	/* VEC */
1133	reg = BREG_Read32(hReg, BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE);
1134	reg &= ~(BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_108_CLOCK_ENABLE_MASK \|
1135	BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_ALTERNATE_216_CLOCK_ENABLE_MASK
1136	);
1137	BREG_Write32(hReg, BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE, reg);
1138	#endif
1139
1140	/* SECTOP */
1141	reg = BREG_Read32(hReg, BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE);
1142	reg &= ~(BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SEC_ALTERNATE_SCB_CLOCK_ENABLE_MASK
1143	);
1144	BREG_AtomicUpdate32(hReg, BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE, reg, reg);
1145
1146	#if BCHP_VER >= BCHP_VER_B0
1147	/* power off tuner daisy output */
1148	reg = BREG_Read32(hReg, BCHP_UFE_AFE_TNR0_PWRUP_01);
1149	reg &= ~(BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DAISY_VHF_MASK \|
1150	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DAISY_UHF_MASK \|
1151	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LT_MASK \|
1152	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_SDADC_REG1p0_MASK \| /* SDADC */
1153	BCHP_UFE_AFE_TNR0_PWRUP_01_i_DAC_LPF_pwrup_RFAGC_MASK \| /* tuner 0 */
1154	BCHP_UFE_AFE_TNR0_PWRUP_01_i_RFDPD_pwrup_RFAGC_MASK \| /* tuner 0 */
1155	BCHP_UFE_AFE_TNR0_PWRUP_01_i_BB2DPD_pwrup_RFAGC_MASK \| /* tuner 0 */
1156	BCHP_UFE_AFE_TNR0_PWRUP_01_i_BB1DPD_pwrup_RFAGC_MASK \| /* tuner 0 */
1157	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LNAAGC_MASK \| /* tuner 0 */
1158	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DAC12B_MASK \| /* tuner 0 */
1159	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_ADC6B_MASK \| /* tuner 0 */
1160	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_UHF_incom_MASK \| /* tuner 0 */
1161	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_UHF_BUF_MASK \| /* tuner 0 */
1162	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_REG1p0_MASK \| /* tuner 0 */
1163	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DCO_MASK \| /* tuner 0 */
1164	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DPM_MASK \| /* tuner 0 */
1165	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DPM_LOBUF_REG_MASK \| /* tuner 0 */
1166	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LPF_Res_MASK \| /* tuner 0 */
1167	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LPF_Q_MASK \| /* tuner 0 */
1168	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LPF_I_MASK \| /* tuner 0 */
1169	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_FGA_MASK \| /* tuner 0 */
1170	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_MIXER_MASK \| /* tuner 0 */
1171	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_TRKFIL_BUF_MASK \| /* tuner 0 */
1172	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_TRKFIL_MASK \| /* tuner 0 */
1173	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_RFVGA_MASK \| /* tuner 0 */
1174	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_BIAS_MASK /* tuner 0 */
1175	);
1176	#ifdef CONFIG_ISDB
1177	reg = BREG_Read32(hReg, BCHP_UFE_AFE_TNR0_PWRUP_01);
1178	reg \|= (BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DAISY_VHF_MASK \|
1179	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DAISY_UHF_MASK \|
1180	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LT_MASK \|
1181	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_SDADC_REG1p0_MASK \| /* SDADC */
1182	BCHP_UFE_AFE_TNR0_PWRUP_01_i_DAC_LPF_pwrup_RFAGC_MASK \| /* tuner 0 */
1183	BCHP_UFE_AFE_TNR0_PWRUP_01_i_RFDPD_pwrup_RFAGC_MASK \| /* tuner 0 */
1184	BCHP_UFE_AFE_TNR0_PWRUP_01_i_BB2DPD_pwrup_RFAGC_MASK \| /* tuner 0 */
1185	BCHP_UFE_AFE_TNR0_PWRUP_01_i_BB1DPD_pwrup_RFAGC_MASK \| /* tuner 0 */
1186	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LNAAGC_MASK \| /* tuner 0 */
1187	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DAC12B_MASK \| /* tuner 0 */
1188	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_ADC6B_MASK \| /* tuner 0 */
1189	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_UHF_incom_MASK \| /* tuner 0 */
1190	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_UHF_BUF_MASK \| /* tuner 0 */
1191	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_REG1p0_MASK \| /* tuner 0 */
1192	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DCO_MASK \| /* tuner 0 */
1193	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DPM_MASK \| /* tuner 0 */
1194	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_DPM_LOBUF_REG_MASK \| /* tuner 0 */
1195	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LPF_Res_MASK \| /* tuner 0 */
1196	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LPF_Q_MASK \| /* tuner 0 */
1197	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_LPF_I_MASK \| /* tuner 0 */
1198	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_FGA_MASK \| /* tuner 0 */
1199	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_MIXER_MASK \| /* tuner 0 */
1200	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_TRKFIL_BUF_MASK \| /* tuner 0 */
1201	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_TRKFIL_MASK \| /* tuner 0 */
1202	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_RFVGA_MASK \| /* tuner 0 */
1203	BCHP_UFE_AFE_TNR0_PWRUP_01_i_pwrup_BIAS_MASK /* tuner 0 */
1204	);
1205	#endif
1206	BREG_Write32(hReg, BCHP_UFE_AFE_TNR0_PWRUP_01, reg);
1207
1208	#endif /* B0 */
1209
1210	/* power off THD clocks */
1211	reg = BREG_Read32(hReg, BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE);
1212	reg &= ~(BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_SCB_CLOCK_ENABLE_MASK \|
1213	BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_216_CLOCK_ENABLE_MASK \|
1214	BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_108_CLOCK_ENABLE_MASK
1215	);
1216	#ifdef CONFIG_ISDB
1217	/* power on THD clocks for IDSB-T */
1218	reg = BREG_Read32(hReg, BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE);
1219	reg \|= (BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_SCB_CLOCK_ENABLE_MASK \|
1220	BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_216_CLOCK_ENABLE_MASK \|
1221	BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE_THD_108_CLOCK_ENABLE_MASK
1222	);
1223	#endif
1224	BREG_Write32(hReg, BCHP_CLKGEN_THD_TOP_CLOCK_ENABLE, reg);
1225
1226	/* set M2MC 216 MHz */
1227	reg = BREG_Read32(hReg, BCHP_CLKGEN_INTERNAL_MUX_SELECT);
1228	reg = 0;
1229	BREG_Write32(hReg, BCHP_CLKGEN_INTERNAL_MUX_SELECT, reg);
1230
1231	/* power down all internal DS clocks */
1232	#if 0
1233	reg = BREG_Read32(hReg,BCHP_DS_PD);
1234	reg = 0xffffffff;
1235	BREG_Write32 (hReg, BCHP_DS_PD, reg);
1236	#endif
1237
1238	#ifdef OOB_TUNER_SUPPORT
1239	/* power down UFE_OBADC */
1240	#if BCHP_VER >= BCHP_VER_B0
1241	reg = BREG_Read32(hReg,BCHP_OBADC_CNTL3);
1242	reg &= ~(BCHP_OBADC_CNTL3_PWRUP_MASK
1243	);
1244	BREG_Write32 (hReg, BCHP_OBADC_CNTL3, reg);
1245	#endif
1246	#endif
1247
1248	/* power down UFE_SDADC */
1249	reg = BREG_Read32(hReg,BCHP_SDADC_CTRL_PWRUP);
1250	reg = 0;
1251	BREG_Write32 (hReg, BCHP_SDADC_CTRL_PWRUP, reg);
1252
1253	/* power down tuner 0 */
1254	reg = BREG_Read32(hReg, BCHP_UFE_AFE_TNR_PWRUP_01);
1255	reg &= ~(BCHP_UFE_AFE_TNR_PWRUP_01_i_pwrup_ADCBUF_MASK \|
1256	BCHP_UFE_AFE_TNR_PWRUP_01_REF_OUTDIV_PWRUP_MASK \|
1257	BCHP_UFE_AFE_TNR_PWRUP_01_REF_OUTCML_PWRUP_MASK \|
1258	BCHP_UFE_AFE_TNR_PWRUP_01_REF_OUTCMOS_PWRUP_MASK \|
1259	BCHP_UFE_AFE_TNR_PWRUP_01_REF_IGEN_PWRUP_MASK \|
1260	BCHP_UFE_AFE_TNR_PWRUP_01_REF_mux_PWRUP_MASK \|
1261	BCHP_UFE_AFE_TNR_PWRUP_01_REF_UGB_PWRUP_MASK \|
1262	BCHP_UFE_AFE_TNR_PWRUP_01_REF_DIV_refbuf_PWRUP_MASK \|
1263	BCHP_UFE_AFE_TNR_PWRUP_01_REF_fbreg_PWRUP_MASK \|
1264	BCHP_UFE_AFE_TNR_PWRUP_01_REF_VCO_PWRUP_MASK \|
1265	BCHP_UFE_AFE_TNR_PWRUP_01_REF_REGQPPFD_PWRUP_MASK \|
1266	BCHP_UFE_AFE_TNR_PWRUP_01_REF_QP_PWRUP_MASK \|
1267	BCHP_UFE_AFE_TNR_PWRUP_01_REF_bgp_receiver_pup_MASK \|
1268	BCHP_UFE_AFE_TNR_PWRUP_01_REF_POSTDIV_master_PWRUP_MASK \|
1269	BCHP_UFE_AFE_TNR_PWRUP_01_REF_PLL_master_PWRUP_MASK
1270	);
1271	#ifdef CONFIG_ISDB
1272	reg \|= (BCHP_UFE_AFE_TNR_PWRUP_01_i_pwrup_ADCBUF_MASK \|
1273	BCHP_UFE_AFE_TNR_PWRUP_01_REF_OUTDIV_PWRUP_MASK \|
1274	BCHP_UFE_AFE_TNR_PWRUP_01_REF_OUTCML_PWRUP_MASK \|
1275	BCHP_UFE_AFE_TNR_PWRUP_01_REF_OUTCMOS_PWRUP_MASK \|
1276	BCHP_UFE_AFE_TNR_PWRUP_01_REF_IGEN_PWRUP_MASK \|
1277	BCHP_UFE_AFE_TNR_PWRUP_01_REF_mux_PWRUP_MASK \|
1278	BCHP_UFE_AFE_TNR_PWRUP_01_REF_UGB_PWRUP_MASK \|
1279	BCHP_UFE_AFE_TNR_PWRUP_01_REF_DIV_refbuf_PWRUP_MASK \|
1280	BCHP_UFE_AFE_TNR_PWRUP_01_REF_fbreg_PWRUP_MASK \|
1281	BCHP_UFE_AFE_TNR_PWRUP_01_REF_VCO_PWRUP_MASK \|
1282	BCHP_UFE_AFE_TNR_PWRUP_01_REF_REGQPPFD_PWRUP_MASK \|
1283	BCHP_UFE_AFE_TNR_PWRUP_01_REF_QP_PWRUP_MASK \|
1284	BCHP_UFE_AFE_TNR_PWRUP_01_REF_bgp_receiver_pup_MASK \|
1285	BCHP_UFE_AFE_TNR_PWRUP_01_REF_POSTDIV_master_PWRUP_MASK \|
1286	BCHP_UFE_AFE_TNR_PWRUP_01_REF_PLL_master_PWRUP_MASK
1287	);
1288	#endif
1289	BREG_Write32(hReg, BCHP_UFE_AFE_TNR_PWRUP_01, reg);
1290
1291	reg = BREG_Read32(hReg, BCHP_UFE_AFE_TNR0_PWRUP_02);
1292	reg = 0;
1293	#ifdef CONFIG_ISDB
1294	reg = 0xffffffff;
1295	#endif
1296	BREG_Write32(hReg, BCHP_UFE_AFE_TNR0_PWRUP_02, reg);
1297
1298	#ifdef OOB_TUNER_SUPPORT
1299	/* OOB can't power down */
1300	#if 0
1301	reg = BREG_Read32(hReg,BCHP_OOB_CTRL2);
1302	reg &= ~(BCHP_OOB_CTRL2_OBPWR_MASK
1303	);
1304	BREG_Write32 (hReg, BCHP_OOB_CTRL2, reg);
1305	#endif
1306	#endif
1307	}
1308	#endif
1309
1310	static void gist_power_down_eth(BREG_Handle hReg)
1311	{
1312	uint32_t reg;
1313
1314	/* Power down phy */
1315	reg = BREG_Read32(hReg,BCHP_GENET_0_EXT_PWR_MGNT);
1316	reg \|= (BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_phy_en_MASK \|
1317	BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_phy_rd_MASK \|
1318	BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_phy_sd_MASK \|
1319	BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_phy_rx_MASK \|
1320	BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_phy_tx_MASK \|
1321	BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_dll_MASK \|
1322	BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_bias_MASK \|
1323	BCHP_GENET_0_EXT_PWR_MGNT_ext_pwr_down_phy_MASK);
1324	BREG_Write32 (hReg, BCHP_GENET_0_EXT_PWR_MGNT, reg);
1325
1326	/* SYS1 PLL */
1327	reg = BREG_Read32(hReg, BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2);
1328	reg \|= (BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK \|
1329	BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK);
1330	BREG_Write32(hReg, BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2, reg);
1331
1332	/* Power down GENET0 */
1333	reg = BREG_Read32(hReg,BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE);
1334	reg &= ~(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK \|
1335	BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK \|
1336	BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK \|
1337	BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK \|
1338	BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK \|
1339	BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK \|
1340	BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK
1341	);
1342	BREG_Write32 (hReg, BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE, reg);
1343
1344	reg = BREG_Read32(hReg,BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE);
1345	reg &= ~(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK \|
1346	BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK \|
1347	BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK
1348	);
1349	BREG_Write32 (hReg, BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_DISABLE, reg);
1350
1351	reg = BREG_Read32(hReg,BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE);
1352	reg &= ~(BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK \|
1353	BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK
1354	);
1355	BREG_Write32 (hReg, BCHP_CLKGEN_GENET_TOP_RGMII_INST_CLOCK_ENABLE, reg);
1356
1357	reg = BREG_Read32(hReg,BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0);
1358	reg &= ~(BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK
1359	);
1360	BREG_Write32 (hReg, BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0, reg);
1361	}
1362
1363	#ifdef CONFIG_VSB
1364	static void gist_config_vsb(BREG_Handle hReg)
1365	{
1366	uint32_t reg;
1367
1368	#if 0
1369	/* PKT 2 */
1370	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12);
1371	reg &= ~(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_MASK \|
1372	BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_MASK \|
1373	BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_MASK \|
1374	BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_MASK \|
1375	BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_MASK );
1376	reg \|= (BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PKT2_CLK << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SHIFT) \|
1377	(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PKT2_DATA << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SHIFT) \|
1378	(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PKT2_SYNC << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SHIFT) \|
1379	(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT2_VALID << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SHIFT) \|
1380	(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PKT2_ERROR << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SHIFT);
1381	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12, reg);
1382
1383	/* BSC 1 */
1384	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16);
1385	reg &= ~(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_MASK \|
1386	BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_MASK);
1387	reg \|= (BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_BSC_M1_SCL << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_02_SHIFT) \|
1388	(BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_BSC_M1_SDA << BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_sgpio_03_SHIFT);
1389	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16, reg);
1390	#endif
1391
1392	/* 3520 External IRQ0 */
1393	reg = BREG_Read32(hReg,BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0);
1394	reg &= ~(BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK);
1395	reg \|= (BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQ0 << BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT);
1396	BREG_Write32 (hReg, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0, reg);
1397	}
1398	#endif
1399
1400	/***************************************************************************
1401	Summary:
1402	Configure pin muxes for the 97550 reference platform
1403	Description:
1404	The core module must be initialized for this to be called
1405	***************************************************************************/
1406	#ifdef NEXUS_HAS_DVB_CI
1407	#undef NEXUS_HAS_DVB_CI
1408	#endif
1409
1410	#include "bchp_gio_aon.h"
1411
1412	static BERR_Code NEXUS_Platform_P_InitPinmux(BREG_Handle hReg)
1413	{
1414	uint32_t reg;
1415
1416	//sgpio00 , sgpio01 output mode
1417	reg = BREG_Read32(hReg,BCHP_GIO_AON_IODIR_EXT);
1418
1419	reg &= ~(BCHP_MASK(GIO_AON_IODIR_EXT,iodir));
1420	reg \|= (BCHP_FIELD_DATA(GIO_AON_IODIR_EXT,iodir,0));
1421
1422	BREG_Write32 (hReg, BCHP_GIO_AON_IODIR_EXT, reg);
1423
1424
1425	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6
1426	* GPIO_46 : POD2CHIP_MCLKI
1427	* GPIO_47 : POD2CHIP_MDI0
1428	* GPIO_48 : POD2CHIP_MDI1
1429	* GPIO_49 : POD2CHIP_MDI2
1430	* GPIO_50 : POD2CHIP_MDI3
1431	* GPIO_51 : POD2CHIP_MDI4
1432	* GPIO_52 : POD2CHIP_MDI5
1433	*/
1434
1435	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6);
1436
1437	reg &= ~(
1438	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_46) \|
1439	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_47) \|
1440	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_48) \|
1441	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_49) \|
1442	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_50) \|
1443	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_51) \|
1444	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_52)
1445	);
1446	#if NEXUS_HAS_DVB_CI
1447	reg \|= BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_46, 1) \| /* POD2CHIP_MCLKI */
1448	#else
1449	reg \|= BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_46, 3) \| /* EBI Addr 14 */
1450	#endif
1451	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_47, 1) \| /* POD2CHIP_MDI0 */
1452	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_48, 1) \| /* POD2CHIP_MDI1 */
1453	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_49, 1) \| /* POD2CHIP_MDI2 */
1454	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_50, 1) \| /* POD2CHIP_MDI3 */
1455	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_51, 1) \| /* POD2CHIP_MDI4 */
1456	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_6, gpio_52, 1) ; /* POD2CHIP_MDI5 */
1457
1458	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6, reg);
1459
1460	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7
1461	* GPIO_53 : POD2CHIP_MDI6
1462	* GPIO_54 : POD2CHIP_MDI7
1463	* GPIO_55 : POD2CHIP_MISTRT
1464	* GPIO_56 : POD2CHIP_MIVAL
1465	* GPIO_57 : CHIP2POD_MCLKO
1466	* GPIO_58 : CHIP2POD_MDO0
1467	* GPIO_59 : CHIP2POD_MDO1
1468	* GPIO_60 : CHIP2POD_MDO2
1469	*/
1470
1471	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7);
1472
1473	reg &= ~(
1474	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_53) \|
1475	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_54) \|
1476	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_55) \|
1477	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_56) \|
1478	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_57) \|
1479	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_58) \|
1480	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_59) \|
1481	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_60)
1482	);
1483
1484	reg \|= BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_53, 1) \| /* POD2CHIP_MDI6 */
1485	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_54, 1) \| /* POD2CHIP_MDI7 */
1486	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_55, 1) \| /* POD2CHIP_MISTRT */
1487	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_56, 1) \| /* POD2CHIP_MIVAL */
1488	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_57, 1) \| /* CHIP2POD_MCLKO */
1489	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_58, 1) \| /* CHIP2POD_MDO0 */
1490	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_59, 1) \| /* CHIP2POD_MDO1 */
1491	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_7, gpio_60, 1) ; /* CHIP2POD_MDO2 */
1492
1493	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7, reg);
1494
1495	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8
1496	* GPIO_61 : CHIP2POD_MDO3
1497	* GPIO_62 : CHIP2POD_MDO4
1498	* GPIO_63 : CHIP2POD_MDO5
1499	* GPIO_64 : CHIP2POD_MDO6
1500	* GPIO_65 : CHIP2POD_MDO7
1501	* GPIO_66 : CHIP2POD_MOSTRT
1502	* GPIO_67 : CHIP2POD_MOVAL
1503	* GPIO_68 : EBI_ADDR13
1504	*/
1505
1506	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8);
1507
1508	reg &= ~(
1509	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_61) \|
1510	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_62) \|
1511	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_63) \|
1512	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_64) \|
1513	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_65) \|
1514	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_66) \|
1515	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_67) \|
1516	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_68)
1517	);
1518
1519	reg \|= BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_61, 1) \| /* CHIP2POD_MDO3 */
1520	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_62, 1) \| /* CHIP2POD_MDO4 */
1521	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_63, 1) \| /* CHIP2POD_MDO5 */
1522	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_64, 1) \| /* CHIP2POD_MDO6 */
1523	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_65, 1) \| /* CHIP2POD_MDO7 */
1524	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_66, 1) \| /* CHIP2POD_MOSTRT */
1525	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_67, 1) \| /* CHIP2POD_MOVAL */
1526	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_8, gpio_68, 3) ; /* EBI Addr 13 */
1527
1528	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8, reg);
1529
1530	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9
1531	* GPIO_69 : EBI_ADDR12
1532	* GPIO_70 : EBI_ADDR2
1533	* GPIO_71 : EBI_ADDR1
1534	* GPIO_72 : EBI_ADDR0
1535	* GPIO_73 : MPOD_M_SDI
1536	* GPIO_74 : RMX0_CLK
1537	* GPIO_75 : RMX0_DATA
1538	* GPIO_76 : RMX0_SYNC
1539	*/
1540
1541	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9);
1542
1543	reg &= ~(
1544	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_69) \|
1545	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_70) \|
1546	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_71) \|
1547	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_72) \|
1548	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_73) \|
1549	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_74) \|
1550	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_75) \|
1551	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_76)
1552	);
1553
1554	reg \|= BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_69, 3) \| /* EBI Addr 13 */
1555	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_70, 2) \| /* EBI Addr 2 */
1556	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_71, 2) \| /* EBI Addr 1 */
1557	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_72, 2) \| /* EBI Addr 0 */
1558	#if NEXUS_HAS_DVB_CI
1559	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_73, 1) ; /* MPOD_M_SDI */
1560	#else
1561	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_73, 1) \| /* MPOD_M_SDI */
1562	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_74, 1) \| /* RMX0_CLK */
1563	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_75, 1) \| /* RMX0_DATA */
1564	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_9, gpio_76, 1) ; /* RMX0_SYNC */
1565	#endif
1566
1567	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9, reg);
1568
1569	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10
1570	* GPIO_77 : RMX0_VALID
1571	* GPIO_78 : RMX0_PAUSE
1572	* GPIO_79 : SC0_VCC
1573	* GPIO_80 : SC0_CLK
1574	* GPIO_81 : SC0_RST
1575	* GPIO_82 : SC0_IO
1576	* GPIO_83 : SC0_PRES
1577	* GPIO_84 : GPIO
1578	*/
1579
1580	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10);
1581
1582	reg &= ~(
1583	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_77) \|
1584	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_78) \|
1585	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_79) \|
1586	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_80) \|
1587	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_81) \|
1588	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_82) \|
1589	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_83) \|
1590	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_84)
1591	);
1592
1593	reg \|=
1594	#if !NEXUS_HAS_DVB_CI
1595	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_77, 1) \| /* RMX0_VALID */
1596	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_78, 1) \| /* RMX0_PAUSE */
1597	#endif
1598	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_79, 1) \| /* SC0_VCC */
1599	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_80, 1) \| /* SC0_CLK */
1600	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_81, 1) \| /* SC0_RST */
1601	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_82, 1) \| /* SC0_IO */
1602	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_83, 1) \| /* SC0_PRES */
1603	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_10, gpio_84, 0) ; /* GPIO */
1604
1605	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10, reg);
1606
1607	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11
1608	* GPIO_85 : GPIO
1609	* GPIO_86 : SC_VPP
1610	* GPIO_87 : UART_TX0
1611	* GPIO_88 : UART_RX0
1612	* GPIO_89 : ALT_TP_OUT_01
1613	* GPIO_90 : ALT_TP_IN_01
1614	* GPIO_91 : ALT_TP_OUT_02
1615	* GPIO_92 : ALT_TP_IN_02
1616	*/
1617
1618	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11);
1619
1620	reg &= ~(
1621	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_85) \|
1622	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_86) \|
1623	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_87) \|
1624	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_88) \|
1625	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_89) \|
1626	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_90) \|
1627	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_91) \|
1628	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_92)
1629	);
1630
1631	reg \|= BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_85, 0) \| /* GPIO */
1632	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_86, 1) \| /* SC_VPP */
1633	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_87, 2) \| /* UART_TX0 */
1634	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_88, 2) \| /* UART_RX0 */
1635	#if NEXUS_HAS_DVB_CI
1636	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_89, 4) \| /* POD_EBI_RDB */
1637	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_90, 4) \| /* POD_EBI_WE0B */
1638	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_91, 4) \| /* POD_EBI_DSB */
1639	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_92, 4) ; /* POD2CHIP_MCLKI */
1640	#else
1641	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_89, 3) \| /* ALT_TP_OUT_01 */
1642	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_90, 3) \| /* ALT_TP_IN_01 */
1643	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_91, 3) \| /* ALT_TP_OUT_02 */
1644	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_11, gpio_92, 3) ; /* ALT_TP_IN_02 */
1645	#endif
1646
1647
1648	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11, reg);
1649
1650	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12
1651	* GPIO_93 : SF_HOLDB
1652	* GPIO_94 : SF_WPB
1653	* GPIO_96 : PKT2_CLK
1654	* GPIO_97 : PKT2_DATA
1655	* GPIO_98 : PKT2_SYNC
1656	* GPIO_99 : PKT2_VALID
1657	* GPIO_100 : PKT2_ERROR
1658	* GPIO_101 : default
1659	*/
1660
1661	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12);
1662
1663	reg &= ~(
1664	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_93) \|
1665	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_94) \|
1666	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_96) \|
1667	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_97) \|
1668	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_98) \|
1669	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_99) \|
1670	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_100)
1671	);
1672
1673	reg \|= BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_93, 1) \| /* SF_HOLDB */
1674	#if NEXUS_HAS_DVB_CI
1675	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_94, 1); /* SF_WPB */
1676	#else
1677	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_94, 1) \| /* SF_WPB */
1678	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_96, 1) \| /* PKT2_CLK */
1679	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_97, 1) \| /* PKT2_DATA */
1680	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_98, 1) \| /* PKT2_SYNC */
1681	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_99, 1) \| /* PKT2_VALID */
1682	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_12, gpio_100, 1); /* PKT2_ERROR */
1683	#endif
1684
1685	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12, reg);
1686
1687	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13
1688	* GPIO_102...GPIO_109: default
1689	* GPIO_110: default EBI
1690	*/
1691
1692	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14
1693	* GPIO_111...GPIO_118: default EBI
1694	*/
1695
1696	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15
1697	* GPIO_123 : RGMII_MDC
1698	* GPIO_124 : RGMII_MDIO
1699	* SGPIO_00 : BSC_M0_SCL
1700	* SGPIO_01 : BSC_M0_SDA
1701	*/
1702
1703	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15);
1704
1705	reg &= ~(
1706	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_15, gpio_123) \|
1707	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_15, gpio_124) \|
1708	#if BCHP_VER >= BCHP_VER_B0
1709	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_02) \|
1710	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_03)
1711	#else
1712	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_00) \|
1713	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_01)
1714	#endif
1715	);
1716
1717	reg \|= BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_15, gpio_123, 1) \| /* RGMII_MDC */
1718	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_15, gpio_124, 1) \| /* RGMII_MDIO */
1719	#if BCHP_VER >= BCHP_VER_B0
1720	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_02, 1) \| /* BSC_M1_SCL */
1721	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_03, 1) ; /* BSC_M1_SDA */
1722	#else
1723	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_00, 1) \| /* BSC_M0_SCL */
1724	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_15, sgpio_01, 1) ; /* BSC_M0_SDA */
1725	#endif
1726	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15, reg);
1727
1728	#if BCHP_VER == BCHP_VER_A0
1729	/* BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16
1730	* SGPIO_02 : BSC_M1_SCL
1731	* SGPIO_03 : BSC_M1_SDA
1732	*/
1733
1734	reg = BREG_Read32(hReg,BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16);
1735
1736	reg &= ~(
1737	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_16, sgpio_02) \|
1738	BCHP_MASK(SUN_TOP_CTRL_PIN_MUX_CTRL_16, sgpio_03)
1739	);
1740
1741	reg \|= BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_16, sgpio_02, 1) \| /* BSC_M1_SCL */
1742	BCHP_FIELD_DATA(SUN_TOP_CTRL_PIN_MUX_CTRL_16, sgpio_03, 1); /* BSC_M1_SDA */
1743
1744	BREG_Write32 (hReg, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16, reg);
1745	#endif
1746
1747	/* BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0
1748	* AON_IR_IN0 : AON_IR_IN0(0)
1749	* AON_S3_STANDBYB: AON_S3_STANDBYB(0)
1750	* AON_HDMI_HTPLG : AON_HDMI_HTPLG(0)
1751	* AON_GPIO_00 : AUD_SPDIF(1)
1752	* AON_GPIO_01 : ENET_LINK(1)
1753	* AON_GPIO_03 : LED_OUT(1)
1754	* AON_GPIO_04 : I2S_CLK0_OUT(3)
1755	* AON_GPIO_05 : I2S_DATA0_OUT(3)
1756	*/
1757
1758	reg = BREG_Read32(hReg,BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0);
1759
1760	reg &=~(
1761	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_ir_in0 ) \|
1762	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_s3_standbyb ) \|
1763	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_hdmi_htplg ) \|
1764	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_00 ) \|
1765	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_01 ) \|
1766	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_03 ) \|
1767	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_04 ) \|
1768	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_05 )
1769	);
1770
1771	reg \|=(
1772	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_ir_in0, 0 ) \| /* AON_IR_IN0 */
1773	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_s3_standbyb, 0 ) \| /* AON_S3_STANDBYB */
1774	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_hdmi_htplg, 0 ) \| /* AON_HDMI_HTPLG */
1775	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_00, 1 ) \| /* AUD_SPDIF */
1776	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_01, 1 ) \| /* ENET_LINK */
1777	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_03, 1 ) \| /* LED_OUT */
1778	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_04, 3 ) \| /* I2S_CLK0_OUT */
1779	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_0, aon_gpio_05, 3 ) /* I2S_DATA0_OUT */
1780	);
1781
1782	BREG_Write32 (hReg, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0, reg);
1783
1784	/* BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1
1785	* AON_GPIO_06 : I2S_LR0_OUT(3)
1786	* AON_GPIO_07 : CODEC_SDI(3)
1787	* AON_GPIO_09 : CODEC_SCLK(3)
1788	* AON_GPIO_10 : CODEC_SDO(3)
1789	* AON_GPIO_11 : CODEC_MCLK(3)
1790	*/
1791
1792	reg = BREG_Read32(hReg,BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1);
1793
1794	reg &=~(
1795	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_06 ) \|
1796	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_07 ) \|
1797	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_09 ) \|
1798	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_10 ) \|
1799	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_11 )
1800	);
1801
1802	reg \|=(
1803	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_06, 3 ) \| /* I2S_LR0_OUT */
1804	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_07, 3 ) \| /* CODEC_SDI */
1805	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_09, 3 ) \| /* CODEC_SCLK */
1806	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_10, 3 ) \| /* CODEC_SDO */
1807	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_1, aon_gpio_11, 3 ) /* CODEC_MCLK */
1808	);
1809
1810	BREG_Write32 (hReg, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1, reg);
1811
1812	/* BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2
1813	* AON_SGPIO_00 : BSC_M3_SCL(1)
1814	*/
1815
1816	reg = BREG_Read32(hReg,BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2);
1817
1818	if (1 /* (platformStatus.chipId == 0x7574) */)
1819	{
1820	/* AON_GPIO_20 is used for RFM switch on 7574 board, no SDIO interface */
1821	reg &=~(
1822	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_2, aon_gpio_20 ) \|
1823	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_2, aon_sgpio_00 )
1824	);
1825	reg \|=(
1826	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_2, aon_gpio_20, 0 ) \| /* AON_GPIO */
1827	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_2, aon_sgpio_00,0 ) /* BSC_M3_SCL */
1828	);
1829	}
1830	else
1831	{
1832	reg &=~(
1833	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_2, aon_sgpio_00 )
1834	);
1835	reg \|=(
1836	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_2, aon_sgpio_00,1 ) /* BSC_M3_SCL */
1837	);
1838	}
1839
1840	BREG_Write32 (hReg, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2, reg);
1841
1842	/* BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3
1843	* AON_SGPIO_01 : BSC_M3_SDA(1)
1844	*/
1845
1846	reg = BREG_Read32(hReg,BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3);
1847
1848	reg &=~(
1849	#if BCHP_VER >= BCHP_VER_B0
1850	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_3, aon_sgpio_01 ) \|
1851	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_3, sgpio_00) \|
1852	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_3, sgpio_01)
1853	#else
1854	BCHP_MASK(AON_PIN_CTRL_PIN_MUX_CTRL_3, aon_sgpio_01 )
1855	#endif
1856	);
1857
1858	reg \|=(
1859	#if BCHP_VER >= BCHP_VER_B0
1860	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_3, aon_sgpio_01,0 ) \| /* BSC_M3_SDA */
1861	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_3, sgpio_00,0 ) \| /* BSC_M0_SCL */
1862	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_3, sgpio_01,0 ) /* BSC_M0_SDA */
1863	#else
1864	BCHP_FIELD_DATA(AON_PIN_CTRL_PIN_MUX_CTRL_3, aon_sgpio_01,1 ) /* BSC_M3_SDA */
1865	#endif
1866	);
1867
1868	BREG_Write32 (hReg, BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3, reg);
1869
1870	/* Configure the AVD UARTS to debug mode. AVD0_OL -> UART1, AVD1_OL -> UART2. */
1871	reg = BREG_Read32(hReg, BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL);
1872	reg &= ~(BCHP_MASK(SUN_TOP_CTRL_UART_ROUTER_SEL, port_2_cpu_sel) \| BCHP_MASK(SUN_TOP_CTRL_UART_ROUTER_SEL, port_1_cpu_sel));
1873	reg \|= BCHP_FIELD_ENUM(SUN_TOP_CTRL_UART_ROUTER_SEL, port_2_cpu_sel, AVD0_OL);
1874	reg \|= BCHP_FIELD_ENUM(SUN_TOP_CTRL_UART_ROUTER_SEL, port_1_cpu_sel, AVD0_IL);
1875	BREG_Write32(hReg,BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL,reg);
1876
1877	reg = BREG_Read32(hReg, BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL);
1878	reg &= ~(BCHP_MASK(SUN_TOP_CTRL_TEST_PORT_CTRL, encoded_tp_enable));
1879	reg \|= BCHP_FIELD_DATA(SUN_TOP_CTRL_TEST_PORT_CTRL,encoded_tp_enable, BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS);
1880	BREG_Write32(hReg, BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL, reg);
1881
1882	/* Configure the Input Band source select options */
1883	/* DS->IB1; PKT2->IB2 */
1884	reg = BREG_Read32(hReg, BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0);
1885	#if BCHP_VER >= BCHP_VER_B0
1886	reg &= ~(BCHP_MASK(SUN_TOP_CTRL_GENERAL_CTRL_0, general_ctrl0_1));
1887	reg \|= BCHP_FIELD_DATA(SUN_TOP_CTRL_GENERAL_CTRL_0,general_ctrl0_1, 1); /* PKT2 */
1888	#else
1889	reg &= ~(BCHP_MASK(SUN_TOP_CTRL_GENERAL_CTRL_0, ib2_source));
1890	reg \|= BCHP_FIELD_DATA(SUN_TOP_CTRL_GENERAL_CTRL_0,ib2_source, 1); /* PKT2 */
1891	#endif
1892	BREG_Write32(hReg, BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0, reg);
1893
1894	return BERR_SUCCESS;
1895	}
1896
1897	BERR_Code gist_rap_open(uint32_t scm_id, scm_callback_t * scm_cb)
1898	{
1899	#if (BCHP_CHIP!=7552) /* [JPF] */
1900	BERR_Code berr;
1901	static BRAP_Settings rapSettings;
1902
1903	/* Get the default RAP device settings */
1904	berr = BRAP_GetDefaultSettings(&rapSettings);
1905	BDBG_ASSERT(berr == BERR_SUCCESS);
1906
1907	/* Allocate device memory for Raptor and fill up sRapSettings */
1908	rapSettings.bExtDeviceMem = false;
1909	rapSettings.pImgInterface = &BRAP_IMG_Interface;
1910	rapSettings.pImgContext = BRAP_IMG_Context;
1911	rapSettings.bIndOpVolCtrl = false;
1912
1913	if(0 != scm_id){
1914	rapSettings.sScmSettings.bSCMEnabled = true;
1915	}else{
1916	rapSettings.sScmSettings.bSCMEnabled = false;
1917	}
1918	rapSettings.sScmSettings.ui32CaSystemId = scm_id;
1919	rapSettings.sScmSettings.pfCallbackOtpProgramming = scm_cb;
1920
1921	/* Delay 300ms to avoid audio pop in BTSC output on startup on 97572 */
1922	BKNI_Sleep(400);
1923
1924	berr = BRAP_Open(&(g_handles.hRap), GetCHP(), GetREG(), GetHEAP(), GetINT(), GetTMR(), &rapSettings);
1925	if(BERR_SUCCESS == berr){
1926	boutput_configure(); /* Configure audio outputs */
1927	}
1928	return berr;
1929	#else
1930	return BERR_SUCCESS;
1931	#endif
1932	}
1933
1934	#include "bfdb.h"
1935	#include "bspi_flash.h"
1936	void gist_read_ca_info(uint32_t *scm_id)
1937	{
1938	#define FLASH_PAGE_SIZE 0x100
1939	#define FLASH_SECTOR_SIZE 0x10000
1940	#define FLASH_DB_SIZE 0x40000
1941	#define FLASH_DB_OFFSET (0x400000 - FLASH_DB_SIZE)
1942	#define MEM_DB_OFFSET 0
1943	#define MEM_DB_SIZE FLASH_DB_SIZE
1944
1945	#define DB_CA_SYSTEM_ID 2 /* coming from bapp_settings.h */
1946
1947	bfdb_err dberr;
1948	struct bfdb_settings dbset;
1949	bspi_settings_t spi_settings;
1950	bresult rc;
1951	bfdb_handle db;
1952	unsigned char db_data[12]; /* read until EMM_Provider_ID */
1953
1954	*scm_id = 0x4749;
1955	rc = bspi_identify(&spi_settings);
1956	BDBG_ASSERT(rc == b_ok);
1957
1958	dbset.page_size = FLASH_PAGE_SIZE;
1959	dbset.sector_size = spi_settings.sector_size;
1960	dbset.db_offset = FLASH_DB_OFFSET;
1961	dbset.db_size = FLASH_DB_SIZE;
1962
1963	dberr = bfdb_open(&dbset, &db);
1964	if(BFDB_OK != dberr){
1965	goto ExitFunc;
1966	}
1967
1968	dberr = bfdb_rewind(db, DB_CA_SYSTEM_ID);
1969	if (BFDB_OK == dberr) {
1970	dberr = bfdb_get(db, db_data, 12);
1971	if (BFDB_OK != dberr) {
1972	BDBG_ERR(("Error:%d line:%d\n", dberr, __LINE__));
1973	goto ExitFunc;
1974	}
1975	}
1976
1977	*scm_id = (db_data[9]<<8) \| db_data[8];
1978
1979	ExitFunc:
1980	if (db) {
1981	bfds_close(db->store);
1982	}
1983	if (scm_id != 0xe11 && scm_id != 0x4749)
1984	*scm_id = 0x4749;
1985	}
1986
1987	void gist_flush_cache(const void *addr, size_t num)
1988	{
1989	flush_dcache((unsigned long)addr, (unsigned long)((unsigned char *)addr+num));
1990	}

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source: svn/trunk/newcon3bcm2_21bu/dta/src/gist/gist.c @ 2

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