| 1 | /************************************************************************** |
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| 2 | * * |
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| 3 | * PROJECT : MIPS port for uC/OS-II * |
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| 4 | * * |
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| 5 | * MODULE : MIPS.h * |
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| 6 | * * |
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| 7 | * AUTHOR : Michael Anburaj * |
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| 8 | * URL : http://geocities.com/michaelanburaj/ * |
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| 9 | * EMAIL: michaelanburaj@hotmail.com * |
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| 10 | * * |
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| 11 | * PROCESSOR : MIPS 4Kc (32 bit RISC) - ATLAS board * |
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| 12 | * * |
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| 13 | * TOOL-CHAIN : SDE & Cygnus * |
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| 14 | * * |
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| 15 | * DESCRIPTION : * |
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| 16 | * MIPS processor definitions. * |
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| 17 | * The basic CPU definitions are found in the file archdefs.h, which * |
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| 18 | * is included by mips.h. * |
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| 19 | * * |
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| 20 | * mips.h implements aliases for some of the definitions in archdefs.h * |
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| 21 | * and adds various definitions. * |
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| 22 | * * |
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| 23 | **************************************************************************/ |
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| 24 | |
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| 25 | |
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| 26 | #ifndef __MIPS_H__ |
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| 27 | #define __MIPS_H__ |
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| 28 | |
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| 29 | #include "archdefs.h" |
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| 30 | |
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| 31 | |
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| 32 | /* ********************************************************************* */ |
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| 33 | /* Module configuration */ |
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| 34 | |
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| 35 | |
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| 36 | /* ********************************************************************* */ |
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| 37 | /* Interface macro & data definition */ |
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| 38 | |
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| 39 | #ifndef MSK |
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| 40 | #define MSK(n) ((1 << (n)) - 1) |
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| 41 | #endif |
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| 42 | |
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| 43 | /* CPU registers */ |
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| 44 | #define SYS_CPUREG_ZERO 0 |
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| 45 | #define SYS_CPUREG_AT 1 |
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| 46 | #define SYS_CPUREG_V0 2 |
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| 47 | #define SYS_CPUREG_V1 3 |
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| 48 | #define SYS_CPUREG_A0 4 |
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| 49 | #define SYS_CPUREG_A1 5 |
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| 50 | #define SYS_CPUREG_A2 6 |
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| 51 | #define SYS_CPUREG_A3 7 |
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| 52 | #define SYS_CPUREG_T0 8 |
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| 53 | #define SYS_CPUREG_T1 9 |
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| 54 | #define SYS_CPUREG_T2 10 |
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| 55 | #define SYS_CPUREG_T3 11 |
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| 56 | #define SYS_CPUREG_T4 12 |
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| 57 | #define SYS_CPUREG_T5 13 |
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| 58 | #define SYS_CPUREG_T6 14 |
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| 59 | #define SYS_CPUREG_T7 15 |
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| 60 | #define SYS_CPUREG_S0 16 |
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| 61 | #define SYS_CPUREG_S1 17 |
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| 62 | #define SYS_CPUREG_S2 18 |
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| 63 | #define SYS_CPUREG_S3 19 |
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| 64 | #define SYS_CPUREG_S4 20 |
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| 65 | #define SYS_CPUREG_S5 21 |
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| 66 | #define SYS_CPUREG_S6 22 |
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| 67 | #define SYS_CPUREG_S7 23 |
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| 68 | #define SYS_CPUREG_T8 24 |
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| 69 | #define SYS_CPUREG_T9 25 |
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| 70 | #define SYS_CPUREG_K0 26 |
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| 71 | #define SYS_CPUREG_K1 27 |
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| 72 | #define SYS_CPUREG_GP 28 |
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| 73 | #define SYS_CPUREG_SP 29 |
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| 74 | #define SYS_CPUREG_S8 30 |
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| 75 | #define SYS_CPUREG_FP SYS_CPUREG_S8 |
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| 76 | #define SYS_CPUREG_RA 31 |
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| 77 | |
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| 78 | |
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| 79 | /* CPU register fp ($30) has an alias s8 */ |
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| 80 | #define s8 fp |
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| 81 | |
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| 82 | |
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| 83 | /* Aliases for System Control Coprocessor (CP0) registers */ |
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| 84 | #define C0_INDEX C0_Index |
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| 85 | #define C0_RANDOM C0_Random |
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| 86 | #define C0_ENTRYLO0 C0_EntryLo0 |
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| 87 | #define C0_ENTRYLO1 C0_EntryLo1 |
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| 88 | #define C0_CONTEXT C0_Context |
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| 89 | #define C0_PAGEMASK C0_PageMask |
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| 90 | #define C0_WIRED C0_Wired |
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| 91 | #define C0_BADVADDR C0_BadVAddr |
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| 92 | #define C0_COUNT C0_Count |
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| 93 | #define C0_ENTRYHI C0_EntryHi |
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| 94 | #define C0_COMPARE C0_Compare |
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| 95 | #define C0_STATUS C0_Status |
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| 96 | #define C0_CAUSE C0_Cause |
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| 97 | |
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| 98 | #ifdef C0_PRID /* ArchDefs has an obsolete def. of C0_PRID */ |
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| 99 | #undef C0_PRID |
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| 100 | #endif |
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| 101 | #define C0_PRID C0_PRId |
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| 102 | |
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| 103 | #define C0_CONFIG C0_Config |
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| 104 | #define C0_CONFIG1 C0_Config1 |
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| 105 | #define C0_LLADDR C0_LLAddr |
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| 106 | #define C0_WATCHLO C0_WatchLo |
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| 107 | #define C0_WATCHHI C0_WatchHi |
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| 108 | #define C0_DEBUG C0_Debug |
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| 109 | #define C0_PERFCNT C0_PerfCnt |
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| 110 | #define C0_ERRCTL C0_ErrCtl |
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| 111 | #define C0_CACHEERR C0_CacheErr |
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| 112 | #define C0_TAGLO C0_TagLo |
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| 113 | #define C0_DATALO C0_DataLo |
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| 114 | #define C0_TAGHI C0_TagHi |
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| 115 | #define C0_DATAHI C0_DataHi |
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| 116 | #define C0_ERROREPC C0_ErrorEPC |
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| 117 | #if 0 |
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| 118 | #define C0_DESAVE C0_DESAVE |
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| 119 | #define C0_EPC C0_EPC |
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| 120 | #define C0_DEPC C0_DEPC |
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| 121 | #endif |
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| 122 | |
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| 123 | /* System Control Coprocessor (CP0) registers select fields */ |
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| 124 | #define C0_INDEX_SEL 0 /* TLB Index */ |
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| 125 | #define C0_RANDOM_SEL 0 /* TLB Random */ |
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| 126 | #define C0_TLBLO0_SEL 0 /* TLB EntryLo0 */ |
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| 127 | #define C0_TLBLO1_SEL 0 /* TLB EntryLo1 */ |
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| 128 | #define C0_CONTEXT_SEL 0 /* Context */ |
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| 129 | #define C0_PAGEMASK_SEL 0 /* TLB PageMask */ |
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| 130 | #define C0_WIRED_SEL 0 /* TLB Wired */ |
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| 131 | #define C0_BADVADDR_SEL 0 /* Bad Virtual Address */ |
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| 132 | #define C0_COUNT_SEL 0 /* Count */ |
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| 133 | #define C0_ENTRYHI_SEL 0 /* TLB EntryHi */ |
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| 134 | #define C0_COMPARE_SEL 0 /* Compare */ |
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| 135 | #define C0_STATUS_SEL 0 /* Processor Status */ |
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| 136 | #define C0_CAUSE_SEL 0 /* Exception Cause */ |
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| 137 | #define C0_EPC_SEL 0 /* Exception PC */ |
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| 138 | #define C0_PRID_SEL 0 /* Processor Revision Indentifier */ |
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| 139 | #define C0_CONFIG_SEL 0 /* Config */ |
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| 140 | #define C0_CONFIG1_SEL 1 /* Config1 */ |
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| 141 | #define C0_LLADDR_SEL 0 /* LLAddr */ |
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| 142 | #define C0_WATCHLO_SEL 0 /* WatchpointLo */ |
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| 143 | #define C0_WATCHHI_SEL 0 /* WatchpointHi */ |
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| 144 | #define C0_DEBUG_SEL 0 /* EJTAG Debug Register */ |
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| 145 | #define C0_DEPC_SEL 0 /* Program counter at last EJTAG debug exception */ |
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| 146 | #define C0_PERFCNT_SEL 0 /* Performance counter interface */ |
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| 147 | #define C0_ERRCTL_SEL 0 /* ERRCTL */ |
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| 148 | #define C0_CACHEERR_SEL 0 /* CacheErr */ |
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| 149 | #define C0_TAGLO_SEL 0 /* TagLo */ |
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| 150 | #define C0_DATALO_SEL 1 /* DataLo */ |
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| 151 | #define C0_DTAGLO_SEL 2 /* DTagLo */ |
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| 152 | #define C0_TAGHI_SEL 0 /* TagHi */ |
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| 153 | #define C0_DATAHI_SEL 1 /* DataHi */ |
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| 154 | #define C0_DTAGHI_SEL 2 /* DTagHi */ |
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| 155 | #define C0_ERROREPC_SEL 0 /* ErrorEPC */ |
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| 156 | #define C0_DESAVE_SEL 0 /* EJTAG dbg exc. save register */ |
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| 157 | |
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| 158 | |
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| 159 | /* C0_CONFIG register encoding */ |
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| 160 | |
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| 161 | #define C0_CONFIG_M_SHF S_ConfigMore |
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| 162 | #define C0_CONFIG_M_MSK M_ConfigMore |
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| 163 | #define C0_CONFIG_M_BIT C0_CONFIG_M_MSK |
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| 164 | |
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| 165 | #define C0_CONFIG_BE_SHF S_ConfigBE |
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| 166 | #define C0_CONFIG_BE_MSK M_ConfigBE |
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| 167 | #define C0_CONFIG_BE_BIT C0_CONFIG_BE_MSK |
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| 168 | |
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| 169 | #define C0_CONFIG_AT_SHF S_ConfigAT |
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| 170 | #define C0_CONFIG_AT_MSK M_ConfigAT |
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| 171 | #define C0_CONFIG_AT_MIPS32 K_ConfigAT_MIPS32 |
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| 172 | #define C0_CONFIG_AT_MIPS64_32ADDR K_ConfigAT_MIPS64S |
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| 173 | #define C0_CONFIG_AT_MIPS64 K_ConfigAT_MIPS64 |
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| 174 | |
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| 175 | #define C0_CONFIG_AR_SHF S_ConfigAR |
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| 176 | #define C0_CONFIG_AR_MSK M_ConfigAR |
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| 177 | |
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| 178 | #define C0_CONFIG_MT_SHF S_ConfigMT |
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| 179 | #define C0_CONFIG_MT_MSK M_ConfigMT |
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| 180 | #define C0_CONFIG_MT_NONE K_ConfigMT_NoMMU |
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| 181 | #define C0_CONFIG_MT_TLB K_ConfigMT_TLBMMU |
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| 182 | #define C0_CONFIG_MT_BAT K_ConfigMT_BATMMU |
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| 183 | #define C0_CONFIG_MT_NON_STD K_ConfigMT_FMMMU |
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| 184 | |
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| 185 | #define C0_CONFIG_K0_SHF S_ConfigK0 |
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| 186 | #define C0_CONFIG_K0_MSK M_ConfigK0 |
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| 187 | #define C0_CONFIG_K0_WTHRU_NOALLOC K_CacheAttrCWTnWA |
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| 188 | #define C0_CONFIG_K0_WTHRU_ALLOC K_CacheAttrCWTWA |
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| 189 | #define C0_CONFIG_K0_UNCACHED K_CacheAttrU |
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| 190 | #define C0_CONFIG_K0_NONCOHERENT K_CacheAttrCN |
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| 191 | #define C0_CONFIG_K0_COHERENTXCL K_CacheAttrCCE |
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| 192 | #define C0_CONFIG_K0_COHERENTXCLW K_CacheAttrCCS |
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| 193 | #define C0_CONFIG_K0_COHERENTUPD K_CacheAttrCCU |
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| 194 | #define C0_CONFIG_K0_UNCACHED_ACCEL K_CacheAttrUA |
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| 195 | |
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| 196 | |
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| 197 | /* WC field. |
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| 198 | * |
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| 199 | * This feature is present specifically to support configuration |
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| 200 | * testing of the core in a lead vehicle, and is not supported |
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| 201 | * in any other environment. Attempting to use this feature |
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| 202 | * outside of the scope of a lead vehicle is a violation of the |
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| 203 | * MIPS Architecture, and may cause unpredictable operation of |
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| 204 | * the processor. |
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| 205 | */ |
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| 206 | #define C0_CONFIG_WC_SHF 19 |
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| 207 | #define C0_CONFIG_WC_MSK (MSK(1) << C0_CONFIG_WC_SHF) |
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| 208 | #define C0_CONFIG_WC_BIT C0_CONFIG_WC_MSK |
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| 209 | |
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| 210 | |
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| 211 | /* C0_CONFIG1 register encoding */ |
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| 212 | |
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| 213 | #define C0_CONFIG1_MMUSIZE_SHF S_Config1MMUSize |
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| 214 | #define C0_CONFIG1_MMUSIZE_MSK M_Config1MMUSize |
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| 215 | |
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| 216 | #define C0_CONFIG1_IS_SHF S_Config1IS |
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| 217 | #define C0_CONFIG1_IS_MSK M_Config1IS |
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| 218 | |
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| 219 | #define C0_CONFIG1_IL_SHF S_Config1IL |
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| 220 | #define C0_CONFIG1_IL_MSK M_Config1IL |
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| 221 | |
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| 222 | #define C0_CONFIG1_IA_SHF S_Config1IA |
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| 223 | #define C0_CONFIG1_IA_MSK M_Config1IA |
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| 224 | |
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| 225 | #define C0_CONFIG1_DS_SHF S_Config1DS |
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| 226 | #define C0_CONFIG1_DS_MSK M_Config1DS |
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| 227 | |
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| 228 | #define C0_CONFIG1_DL_SHF S_Config1DL |
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| 229 | #define C0_CONFIG1_DL_MSK M_Config1DL |
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| 230 | |
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| 231 | #define C0_CONFIG1_DA_SHF S_Config1DA |
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| 232 | #define C0_CONFIG1_DA_MSK M_Config1DA |
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| 233 | |
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| 234 | #define C0_CONFIG1_WR_SHF S_Config1WR |
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| 235 | #define C0_CONFIG1_WR_MSK M_Config1WR |
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| 236 | #define C0_CONFIG1_WR_BIT C0_CONFIG1_WR_MSK |
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| 237 | |
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| 238 | #define C0_CONFIG1_CA_SHF S_Config1CA |
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| 239 | #define C0_CONFIG1_CA_MSK M_Config1CA |
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| 240 | #define C0_CONFIG1_CA_BIT C0_CONFIG1_CA_MSK |
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| 241 | |
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| 242 | #define C0_CONFIG1_EP_SHF S_Config1EP |
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| 243 | #define C0_CONFIG1_EP_MSK M_Config1EP |
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| 244 | #define C0_CONFIG1_EP_BIT C0_CONFIG1_EP_MSK |
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| 245 | |
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| 246 | #define C0_CONFIG1_FP_SHF S_Config1FP |
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| 247 | #define C0_CONFIG1_FP_MSK M_Config1FP |
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| 248 | #define C0_CONFIG1_FP_BIT C0_CONFIG1_FP_MSK |
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| 249 | |
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| 250 | |
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| 251 | /* C0_STATUS register encoding */ |
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| 252 | |
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| 253 | #define C0_STATUS_CU3_SHF S_StatusCU3 |
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| 254 | #define C0_STATUS_CU3_MSK M_StatusCU3 |
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| 255 | #define C0_STATUS_CU3_BIT C0_STATUS_CU3_MSK |
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| 256 | |
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| 257 | #define C0_STATUS_CU2_SHF S_StatusCU2 |
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| 258 | #define C0_STATUS_CU2_MSK M_StatusCU2 |
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| 259 | #define C0_STATUS_CU2_BIT C0_STATUS_CU2_MSK |
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| 260 | |
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| 261 | #define C0_STATUS_CU1_SHF S_StatusCU1 |
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| 262 | #define C0_STATUS_CU1_MSK M_StatusCU1 |
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| 263 | #define C0_STATUS_CU1_BIT C0_STATUS_CU1_MSK |
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| 264 | |
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| 265 | #define C0_STATUS_CU0_SHF S_StatusCU1 |
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| 266 | #define C0_STATUS_CU0_MSK M_StatusCU1 |
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| 267 | #define C0_STATUS_CU0_BIT C0_STATUS_CU0_MSK |
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| 268 | |
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| 269 | #define C0_STATUS_RP_SHF S_StatusRP |
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| 270 | #define C0_STATUS_RP_MSK M_StatusRP |
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| 271 | #define C0_STATUS_RP_BIT C0_STATUS_RP_MSK |
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| 272 | |
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| 273 | #define C0_STATUS_FR_SHF S_StatusFR |
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| 274 | #define C0_STATUS_FR_MSK M_StatusFR |
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| 275 | #define C0_STATUS_FR_BIT C0_STATUS_FR_MSK |
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| 276 | |
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| 277 | #define C0_STATUS_RE_SHF S_StatusRE |
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| 278 | #define C0_STATUS_RE_MSK M_StatusRE |
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| 279 | #define C0_STATUS_RE_BIT C0_STATUS_RE_MSK |
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| 280 | |
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| 281 | #define C0_STATUS_BEV_SHF S_StatusBEV |
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| 282 | #define C0_STATUS_BEV_MSK M_StatusBEV |
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| 283 | #define C0_STATUS_BEV_BIT C0_STATUS_BEV_MSK |
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| 284 | |
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| 285 | #define C0_STATUS_TS_SHF S_StatusTS |
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| 286 | #define C0_STATUS_TS_MSK M_StatusTS |
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| 287 | #define C0_STATUS_TS_BIT C0_STATUS_TS_MSK |
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| 288 | |
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| 289 | #define C0_STATUS_SR_SHF S_StatusSR |
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| 290 | #define C0_STATUS_SR_MSK M_StatusSR |
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| 291 | #define C0_STATUS_SR_BIT C0_STATUS_SR_MSK |
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| 292 | |
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| 293 | #define C0_STATUS_NMI_SHF S_StatusNMI |
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| 294 | #define C0_STATUS_NMI_MSK M_StatusNMI |
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| 295 | #define C0_STATUS_NMI_BIT C0_STATUS_NMI_MSK |
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| 296 | |
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| 297 | #define C0_STATUS_IM_SHF S_StatusIM |
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| 298 | #define C0_STATUS_IM_MSK M_StatusIM |
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| 299 | /* Note that the the definitions below indicate the interrupt number |
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| 300 | * rather than the mask. |
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| 301 | * (0..1 for SW interrupts and 2...7 for HW interrupts) |
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| 302 | */ |
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| 303 | #define C0_STATUS_IM_SW0 (S_StatusIM0 - S_StatusIM) |
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| 304 | #define C0_STATUS_IM_SW1 (S_StatusIM1 - S_StatusIM) |
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| 305 | #define C0_STATUS_IM_HW0 (S_StatusIM2 - S_StatusIM) |
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| 306 | #define C0_STATUS_IM_HW1 (S_StatusIM3 - S_StatusIM) |
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| 307 | #define C0_STATUS_IM_HW2 (S_StatusIM4 - S_StatusIM) |
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| 308 | #define C0_STATUS_IM_HW3 (S_StatusIM5 - S_StatusIM) |
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| 309 | #define C0_STATUS_IM_HW4 (S_StatusIM6 - S_StatusIM) |
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| 310 | #define C0_STATUS_IM_HW5 (S_StatusIM7 - S_StatusIM) |
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| 311 | |
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| 312 | /* Max interrupt code */ |
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| 313 | #define C0_STATUS_IM_MAX C0_STATUS_IM_HW5 |
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| 314 | |
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| 315 | #define C0_STATUS_KSU_SHF S_StatusKSU |
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| 316 | #define C0_STATUS_KSU_MSK M_StatusKSU |
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| 317 | |
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| 318 | #define C0_STATUS_UM_SHF S_StatusUM |
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| 319 | #define C0_STATUS_UM_MSK M_StatusUM |
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| 320 | #define C0_STATUS_UM_BIT C0_STATUS_UM_MSK |
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| 321 | |
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| 322 | #define C0_STATUS_ERL_SHF S_StatusERL |
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| 323 | #define C0_STATUS_ERL_MSK M_StatusERL |
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| 324 | #define C0_STATUS_ERL_BIT C0_STATUS_ERL_MSK |
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| 325 | |
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| 326 | #define C0_STATUS_EXL_SHF S_StatusEXL |
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| 327 | #define C0_STATUS_EXL_MSK M_StatusEXL |
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| 328 | #define C0_STATUS_EXL_BIT C0_STATUS_EXL_MSK |
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| 329 | |
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| 330 | #define C0_STATUS_IE_SHF S_StatusIE |
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| 331 | #define C0_STATUS_IE_MSK M_StatusIE |
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| 332 | #define C0_STATUS_IE_BIT C0_STATUS_IE_MSK |
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| 333 | |
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| 334 | |
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| 335 | /* C0_PRID register encoding */ |
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| 336 | |
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| 337 | #define C0_PRID_OPT_SHF S_PRIdCoOpt |
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| 338 | #define C0_PRID_OPT_MSK M_PRIdCoOpt |
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| 339 | |
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| 340 | #define C0_PRID_COMP_SHF S_PRIdCoID |
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| 341 | #define C0_PRID_COMP_MSK M_PRIdCoID |
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| 342 | #define C0_PRID_COMP_MIPS K_PRIdCoID_MIPS |
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| 343 | #define C0_PRID_COMP_NOT_MIPS32_64 0 |
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| 344 | |
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| 345 | #define C0_PRID_PRID_SHF S_PRIdImp |
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| 346 | #define C0_PRID_PRID_MSK M_PRIdImp |
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| 347 | |
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| 348 | /* Jade */ |
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| 349 | #define C0_PRID_PRID_4Kc K_PRIdImp_Jade |
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| 350 | #define C0_PRID_PRID_4Kmp K_PRIdImp_JadeLite /* 4Km/4Kp */ |
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| 351 | /* Emerald */ |
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| 352 | #define C0_PRID_PRID_4KEc K_PRIdImp_4KEc |
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| 353 | #define C0_PRID_PRID_4KEmp K_PRIdImp_4KEmp |
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| 354 | /* Coral */ |
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| 355 | #define C0_PRID_PRID_4KSc K_PRIdImp_4KSc |
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| 356 | /* Opal */ |
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| 357 | #define C0_PRID_PRID_5K K_PRIdImp_Opal |
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| 358 | /* Ruby */ |
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| 359 | #define C0_PRID_PRID_20Kc K_PRIdImp_Ruby |
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| 360 | /* Other CPUs */ |
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| 361 | #define C0_PRID_PRID_R4000 K_PRIdImp_R4000 |
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| 362 | #define C0_PRID_PRID_RM52XX K_PRIdImp_R5200 |
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| 363 | #define C0_PRID_PRID_RM70XX 0x27 |
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| 364 | |
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| 365 | #define C0_PRID_REV_SHF S_PRIdRev |
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| 366 | #define C0_PRID_REV_MSK M_PRIdRev |
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| 367 | |
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| 368 | |
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| 369 | #define MIPS_4Kc ( (C0_PRID_COMP_MIPS << \ |
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| 370 | C0_PRID_COMP_SHF) | \ |
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| 371 | (C0_PRID_PRID_4Kc << \ |
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| 372 | C0_PRID_PRID_SHF) \ |
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| 373 | ) |
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| 374 | |
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| 375 | #define MIPS_4Kmp ( (C0_PRID_COMP_MIPS << \ |
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| 376 | C0_PRID_COMP_SHF) | \ |
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| 377 | (C0_PRID_PRID_4Kmp << \ |
|---|
| 378 | C0_PRID_PRID_SHF) \ |
|---|
| 379 | ) |
|---|
| 380 | |
|---|
| 381 | #define MIPS_4KEc ( (C0_PRID_COMP_MIPS << \ |
|---|
| 382 | C0_PRID_COMP_SHF) | \ |
|---|
| 383 | (C0_PRID_PRID_4KEc << \ |
|---|
| 384 | C0_PRID_PRID_SHF) \ |
|---|
| 385 | ) |
|---|
| 386 | |
|---|
| 387 | #define MIPS_4KEmp ( (C0_PRID_COMP_MIPS << \ |
|---|
| 388 | C0_PRID_COMP_SHF) | \ |
|---|
| 389 | (C0_PRID_PRID_4KEmp << \ |
|---|
| 390 | C0_PRID_PRID_SHF) \ |
|---|
| 391 | ) |
|---|
| 392 | |
|---|
| 393 | #define MIPS_4KSc ( (C0_PRID_COMP_MIPS << \ |
|---|
| 394 | C0_PRID_COMP_SHF) | \ |
|---|
| 395 | (C0_PRID_PRID_4KSc << \ |
|---|
| 396 | C0_PRID_PRID_SHF) \ |
|---|
| 397 | ) |
|---|
| 398 | |
|---|
| 399 | #define MIPS_5K ( (C0_PRID_COMP_MIPS << \ |
|---|
| 400 | C0_PRID_COMP_SHF) | \ |
|---|
| 401 | (C0_PRID_PRID_5K << \ |
|---|
| 402 | C0_PRID_PRID_SHF) \ |
|---|
| 403 | ) |
|---|
| 404 | |
|---|
| 405 | #define MIPS_20Kc ( (C0_PRID_COMP_MIPS << \ |
|---|
| 406 | C0_PRID_COMP_SHF) | \ |
|---|
| 407 | (C0_PRID_PRID_20Kc << \ |
|---|
| 408 | C0_PRID_PRID_SHF) \ |
|---|
| 409 | ) |
|---|
| 410 | |
|---|
| 411 | #define QED_RM52XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \ |
|---|
| 412 | C0_PRID_COMP_SHF) | \ |
|---|
| 413 | (C0_PRID_PRID_RM52XX << \ |
|---|
| 414 | C0_PRID_PRID_SHF) \ |
|---|
| 415 | ) |
|---|
| 416 | |
|---|
| 417 | #define QED_RM70XX ( (C0_PRID_COMP_NOT_MIPS32_64 << \ |
|---|
| 418 | C0_PRID_COMP_SHF) | \ |
|---|
| 419 | (C0_PRID_PRID_RM70XX << \ |
|---|
| 420 | C0_PRID_PRID_SHF) \ |
|---|
| 421 | ) |
|---|
| 422 | |
|---|
| 423 | /* C0_ENTRYHI register encoding */ |
|---|
| 424 | |
|---|
| 425 | #define C0_ENTRYHI_VPN2_SHF S_EntryHiVPN2 |
|---|
| 426 | #define C0_ENTRYHI_VPN2_MSK M_EntryHiVPN2 |
|---|
| 427 | |
|---|
| 428 | #define C0_ENTRYHI_ASID_SHF S_EntryHiASID |
|---|
| 429 | #define C0_ENTRYHI_ASID_MSK M_EntryHiASID |
|---|
| 430 | |
|---|
| 431 | |
|---|
| 432 | /* C0_CAUSE register encoding */ |
|---|
| 433 | |
|---|
| 434 | #define C0_CAUSE_BD_SHF S_CauseBD |
|---|
| 435 | #define C0_CAUSE_BD_MSK M_CauseBD |
|---|
| 436 | #define C0_CAUSE_BD_BIT C0_CAUSE_BD_MSK |
|---|
| 437 | |
|---|
| 438 | #define C0_CAUSE_CE_SHF S_CauseCE |
|---|
| 439 | #define C0_CAUSE_CE_MSK M_CauseCE |
|---|
| 440 | |
|---|
| 441 | #define C0_CAUSE_IV_SHF S_CauseIV |
|---|
| 442 | #define C0_CAUSE_IV_MSK M_CauseIV |
|---|
| 443 | #define C0_CAUSE_IV_BIT C0_CAUSE_IV_MSK |
|---|
| 444 | |
|---|
| 445 | #define C0_CAUSE_WP_SHF S_CauseWP |
|---|
| 446 | #define C0_CAUSE_WP_MSK M_CauseWP |
|---|
| 447 | #define C0_CAUSE_WP_BIT C0_CAUSE_WP_MSK |
|---|
| 448 | |
|---|
| 449 | #define C0_CAUSE_IP_SHF S_CauseIP |
|---|
| 450 | #define C0_CAUSE_IP_MSK M_CauseIP |
|---|
| 451 | |
|---|
| 452 | #define C0_CAUSE_CODE_SHF S_CauseExcCode |
|---|
| 453 | #define C0_CAUSE_CODE_MSK M_CauseExcCode |
|---|
| 454 | |
|---|
| 455 | #define C0_CAUSE_CODE_INT EX_INT |
|---|
| 456 | #define C0_CAUSE_CODE_MOD EX_MOD |
|---|
| 457 | #define C0_CAUSE_CODE_TLBL EX_TLBL |
|---|
| 458 | #define C0_CAUSE_CODE_TLBS EX_TLBS |
|---|
| 459 | #define C0_CAUSE_CODE_ADEL EX_ADEL |
|---|
| 460 | #define C0_CAUSE_CODE_ADES EX_ADES |
|---|
| 461 | #define C0_CAUSE_CODE_IBE EX_IBE |
|---|
| 462 | #define C0_CAUSE_CODE_DBE EX_DBE |
|---|
| 463 | #define C0_CAUSE_CODE_SYS EX_SYS |
|---|
| 464 | #define C0_CAUSE_CODE_BP EX_BP |
|---|
| 465 | #define C0_CAUSE_CODE_RI EX_RI |
|---|
| 466 | #define C0_CAUSE_CODE_CPU EX_CPU |
|---|
| 467 | #define C0_CAUSE_CODE_OV EX_OV |
|---|
| 468 | #define C0_CAUSE_CODE_TR EV_TR |
|---|
| 469 | #define C0_CAUSE_CODE_FPE EX_FPE |
|---|
| 470 | #define C0_CAUSE_CODE_WATCH EX_WATCH |
|---|
| 471 | #define C0_CAUSE_CODE_MCHECK EX_MCHECK |
|---|
| 472 | |
|---|
| 473 | /* Max cause code */ |
|---|
| 474 | #define C0_CAUSE_CODE_MAX EX_MCHECK |
|---|
| 475 | |
|---|
| 476 | |
|---|
| 477 | /* C0_PAGEMASK register encoding */ |
|---|
| 478 | #define C0_PAGEMASK_MASK_SHF S_PageMaskMask |
|---|
| 479 | #define C0_PAGEMASK_MASK_MSK M_PageMaskMask |
|---|
| 480 | #define C0_PAGEMASK_MASK_4K K_PageMask4K |
|---|
| 481 | #define C0_PAGEMASK_MASK_16K K_PageMask16K |
|---|
| 482 | #define C0_PAGEMASK_MASK_64K K_PageMask64K |
|---|
| 483 | #define C0_PAGEMASK_MASK_256K K_PageMask256K |
|---|
| 484 | #define C0_PAGEMASK_MASK_1M K_PageMask1M |
|---|
| 485 | #define C0_PAGEMASK_MASK_4M K_PageMask4M |
|---|
| 486 | #define C0_PAGEMASK_MASK_16M K_PageMask16M |
|---|
| 487 | |
|---|
| 488 | |
|---|
| 489 | /* C0_ENTRYLO0 register encoding (equiv. to C0_ENTRYLO1) */ |
|---|
| 490 | #define C0_ENTRYLO0_PFN_SHF S_EntryLoPFN |
|---|
| 491 | #define C0_ENTRYLO0_PFN_MSK M_EntryLoPFN |
|---|
| 492 | |
|---|
| 493 | #define C0_ENTRYLO0_C_SHF S_EntryLoC |
|---|
| 494 | #define C0_ENTRYLO0_C_MSK M_EntryLoC |
|---|
| 495 | |
|---|
| 496 | #define C0_ENTRYLO0_D_SHF S_EntryLoD |
|---|
| 497 | #define C0_ENTRYLO0_D_MSK M_EntryLoD |
|---|
| 498 | |
|---|
| 499 | #define C0_ENTRYLO0_V_SHF S_EntryLoV |
|---|
| 500 | #define C0_ENTRYLO0_V_MSK M_EntryLoV |
|---|
| 501 | |
|---|
| 502 | #define C0_ENTRYLO0_G_SHF S_EntryLoG |
|---|
| 503 | #define C0_ENTRYLO0_G_MSK M_EntryLoG |
|---|
| 504 | |
|---|
| 505 | |
|---|
| 506 | /* FPU (CP1) FIR register encoding */ |
|---|
| 507 | #define C1_FIR_3D_SHF S_FIRConfig3D |
|---|
| 508 | #define C1_FIR_3D_MSK M_FIRConfig3D |
|---|
| 509 | |
|---|
| 510 | #define C1_FIR_PS_SHF S_FIRConfigPS |
|---|
| 511 | #define C1_FIR_PS_MSK M_FIRConfigPS |
|---|
| 512 | |
|---|
| 513 | #define C1_FIR_D_SHF S_FIRConfigD |
|---|
| 514 | #define C1_FIR_D_MSK M_FIRConfigD |
|---|
| 515 | |
|---|
| 516 | #define C1_FIR_S_SHF S_FIRConfigS |
|---|
| 517 | #define C1_FIR_S_MSK M_FIRConfigS |
|---|
| 518 | |
|---|
| 519 | #define C1_FIR_PRID_SHF S_FIRImp |
|---|
| 520 | #define C1_FIR_PRID_MSK M_FIRImp |
|---|
| 521 | |
|---|
| 522 | #define C1_FIR_REV_SHF S_FIRRev |
|---|
| 523 | #define C1_FIR_REV_MSK M_FIRRev |
|---|
| 524 | |
|---|
| 525 | |
|---|
| 526 | /* FPU (CP1) FCSR control/status register */ |
|---|
| 527 | #define C1_FCSR_FCC_SHF S_FCSRFCC7_1 |
|---|
| 528 | #define C1_FCSR_FCC_MSK M_FCSRFCC7_1 |
|---|
| 529 | |
|---|
| 530 | #define C1_FCSR_FS_SHF S_FCSRFS |
|---|
| 531 | #define C1_FCSR_FS_MSK M_FCSRFS |
|---|
| 532 | #define C1_FCSR_FS_BIT C1_FCSR_FS_MSK |
|---|
| 533 | |
|---|
| 534 | #define C1_FCSR_CC_SHF S_FCSRCC |
|---|
| 535 | #define C1_FCSR_CC_MSK M_FCSRCC |
|---|
| 536 | |
|---|
| 537 | #define C1_FCSR_IMPL_SHF S_FCSRImpl |
|---|
| 538 | #define C1_FCSR_IMPL_MSK M_FCSRImpl |
|---|
| 539 | |
|---|
| 540 | #define C1_FCSR_EXC_SHF S_FCSRExc |
|---|
| 541 | #define C1_FCSR_EXC_MSK M_FCSRExc |
|---|
| 542 | |
|---|
| 543 | #define C1_FCSR_ENA_SHF S_FCSREna |
|---|
| 544 | #define C1_FCSR_ENA_MSK M_FCSREna |
|---|
| 545 | |
|---|
| 546 | #define C1_FCSR_FLG_SHF S_FCSRFlg |
|---|
| 547 | #define C1_FCSR_FLG_MSK M_FCSRFlg |
|---|
| 548 | |
|---|
| 549 | #define C1_FCSR_RM_SHF S_FCSRRM |
|---|
| 550 | #define C1_FCSR_RM_MSK M_FCSRRM |
|---|
| 551 | #define C1_FCSR_RM_RN K_FCSRRM_RN |
|---|
| 552 | #define C1_FCSR_RM_RZ K_FCSRRM_RZ |
|---|
| 553 | #define C1_FCSR_RM_RP K_FCSRRM_RP |
|---|
| 554 | #define C1_FCSR_RM_RM K_FCSRRM_RM |
|---|
| 555 | |
|---|
| 556 | |
|---|
| 557 | |
|---|
| 558 | /* cache operations */ |
|---|
| 559 | |
|---|
| 560 | #define CACHE_OP( code, type ) ( ((code) << 2) | (type) ) |
|---|
| 561 | |
|---|
| 562 | #define ICACHE_INDEX_INVALIDATE CACHE_OP(0x0, 0) |
|---|
| 563 | #define ICACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 0) |
|---|
| 564 | #define ICACHE_INDEX_STORE_TAG CACHE_OP(0x2, 0) |
|---|
| 565 | #define DCACHE_INDEX_WRITEBACK_INVALIDATE CACHE_OP(0x0, 1) |
|---|
| 566 | #define DCACHE_INDEX_LOAD_TAG CACHE_OP(0x1, 1) |
|---|
| 567 | #define DCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 1) |
|---|
| 568 | #define SCACHE_INDEX_STORE_TAG CACHE_OP(0x2, 3) |
|---|
| 569 | |
|---|
| 570 | #define ICACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 0) |
|---|
| 571 | #define ICACHE_ADDR_FILL CACHE_OP(0x5, 0) |
|---|
| 572 | #define ICACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 0) |
|---|
| 573 | #define DCACHE_ADDR_HIT_INVALIDATE CACHE_OP(0x4, 1) |
|---|
| 574 | #define DCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 1) |
|---|
| 575 | #define DCACHE_ADDR_HIT_WRITEBACK CACHE_OP(0x6, 1) |
|---|
| 576 | #define DCACHE_ADDR_FETCH_LOCK CACHE_OP(0x7, 1) |
|---|
| 577 | |
|---|
| 578 | #define SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE CACHE_OP(0x5, 3) |
|---|
| 579 | |
|---|
| 580 | /* Workaround for bug in early revisions of MIPS 4K family of |
|---|
| 581 | * processors. Only relevant in early engineering samples of test |
|---|
| 582 | * chips (RTL revision <= 3.0). |
|---|
| 583 | * |
|---|
| 584 | * The bug is described in : |
|---|
| 585 | * |
|---|
| 586 | * MIPS32 4K(tm) Processor Core Family RTL Errata Sheet |
|---|
| 587 | * MIPS Document No: MD00003 |
|---|
| 588 | * |
|---|
| 589 | * The bug is identified as : C16 |
|---|
| 590 | */ |
|---|
| 591 | #ifndef SET_MIPS0 |
|---|
| 592 | #define SET_MIPS0() |
|---|
| 593 | #define SET_PUSH() |
|---|
| 594 | #define SET_POP() |
|---|
| 595 | #endif |
|---|
| 596 | #define ICACHE_INVALIDATE_WORKAROUND(reg) \ |
|---|
| 597 | SET_PUSH(); \ |
|---|
| 598 | SET_MIPS0(); \ |
|---|
| 599 | la reg, 999f; \ |
|---|
| 600 | SET_POP(); \ |
|---|
| 601 | cache ICACHE_ADDR_FILL, 0(reg); \ |
|---|
| 602 | sync; \ |
|---|
| 603 | nop; nop; nop; nop; \ |
|---|
| 604 | 999: |
|---|
| 605 | |
|---|
| 606 | /* EMPTY_PIPELINE is used for the below cache invalidation operations. |
|---|
| 607 | * When $I is invalidated, there will still be operations in the |
|---|
| 608 | * pipeline. We make sure these are 'nop' operations. |
|---|
| 609 | */ |
|---|
| 610 | #define EMPTY_PIPELINE nop; nop; nop; nop |
|---|
| 611 | |
|---|
| 612 | #define ICACHE_INDEX_INVALIDATE_OP(index,scratch) \ |
|---|
| 613 | ICACHE_INVALIDATE_WORKAROUND(scratch); \ |
|---|
| 614 | cache ICACHE_INDEX_INVALIDATE, 0(index); \ |
|---|
| 615 | EMPTY_PIPELINE |
|---|
| 616 | |
|---|
| 617 | #define ICACHE_ADDR_INVALIDATE_OP(addr,scratch) \ |
|---|
| 618 | ICACHE_INVALIDATE_WORKAROUND(scratch); \ |
|---|
| 619 | cache ICACHE_ADDR_HIT_INVALIDATE, 0(addr); \ |
|---|
| 620 | EMPTY_PIPELINE |
|---|
| 621 | |
|---|
| 622 | /* The sync used in the below macro is there in case we are installing |
|---|
| 623 | * a new instruction (flush $D, sync, invalidate $I sequence). |
|---|
| 624 | */ |
|---|
| 625 | #define SCACHE_ADDR_HIT_WB_INVALIDATE_OP(reg) \ |
|---|
| 626 | cache SCACHE_ADDR_HIT_WRITEBACK_INVALIDATE, 0(reg); \ |
|---|
| 627 | sync; \ |
|---|
| 628 | EMPTY_PIPELINE |
|---|
| 629 | |
|---|
| 630 | /* Config1 cache field decoding */ |
|---|
| 631 | #define CACHE_CALC_SPW(s) ( 64 << (s) ) |
|---|
| 632 | #define CACHE_CALC_LS(l) ( (l) ? 2 << (l) : 0 ) |
|---|
| 633 | #define CACHE_CALC_BPW(l,s) ( CACHE_CALC_LS(l) * CACHE_CALC_SPW(s) ) |
|---|
| 634 | #define CACHE_CALC_ASSOC(a) ( (a) + 1 ) |
|---|
| 635 | |
|---|
| 636 | |
|---|
| 637 | /**** Move from/to Coprocessor operations ****/ |
|---|
| 638 | |
|---|
| 639 | /* We use ssnop instead of nop operations in order to handle |
|---|
| 640 | * superscalar CPUs. |
|---|
| 641 | * The "sll zero,zero,1" notation is compiler backwards compatible. |
|---|
| 642 | */ |
|---|
| 643 | #define SSNOP sll zero,zero,1 |
|---|
| 644 | #define NOPS SSNOP; SSNOP; SSNOP; SSNOP |
|---|
| 645 | |
|---|
| 646 | #define MFLO(dst) \ |
|---|
| 647 | mflo dst;\ |
|---|
| 648 | NOPS |
|---|
| 649 | |
|---|
| 650 | /* Workaround for bug in early revisions of MIPS 4K family of |
|---|
| 651 | * processors. |
|---|
| 652 | * |
|---|
| 653 | * This concerns the nop instruction before mtc0 in the |
|---|
| 654 | * MTC0 macro below. |
|---|
| 655 | * |
|---|
| 656 | * The bug is described in : |
|---|
| 657 | * |
|---|
| 658 | * MIPS32 4K(tm) Processor Core Family RTL Errata Sheet |
|---|
| 659 | * MIPS Document No: MD00003 |
|---|
| 660 | * |
|---|
| 661 | * The bug is identified as : C27 |
|---|
| 662 | */ |
|---|
| 663 | |
|---|
| 664 | #define MTC0(src, dst) \ |
|---|
| 665 | nop; \ |
|---|
| 666 | mtc0 src,dst;\ |
|---|
| 667 | NOPS |
|---|
| 668 | |
|---|
| 669 | #define DMTC0(src, dst) \ |
|---|
| 670 | nop; \ |
|---|
| 671 | dmtc0 src,dst;\ |
|---|
| 672 | NOPS |
|---|
| 673 | |
|---|
| 674 | #define MFC0(dst, src) \ |
|---|
| 675 | mfc0 dst,src;\ |
|---|
| 676 | NOPS |
|---|
| 677 | |
|---|
| 678 | #define DMFC0(dst, src) \ |
|---|
| 679 | dmfc0 dst,src;\ |
|---|
| 680 | NOPS |
|---|
| 681 | |
|---|
| 682 | #define MFC0_SEL_OPCODE(dst, src, sel)\ |
|---|
| 683 | .##word (0x40000000 | ((dst)<<16) | ((src)<<11) | (sel));\ |
|---|
| 684 | NOPS |
|---|
| 685 | |
|---|
| 686 | #define MTC0_SEL_OPCODE(dst, src, sel)\ |
|---|
| 687 | .##word (0x40800000 | ((dst)<<16) | ((src)<<11) | (sel));\ |
|---|
| 688 | NOPS |
|---|
| 689 | |
|---|
| 690 | #define LDC1(dst, src, offs)\ |
|---|
| 691 | .##word (0xd4000000 | ((src)<<21) | ((dst)<<16) | (offs)) |
|---|
| 692 | |
|---|
| 693 | #define SDC1(src, dst, offs)\ |
|---|
| 694 | .##word (0xf4000000 | ((dst)<<21) | ((src)<<16) | (offs)) |
|---|
| 695 | |
|---|
| 696 | |
|---|
| 697 | /* Instruction opcode fields */ |
|---|
| 698 | #define OPC_SPECIAL 0x0 |
|---|
| 699 | #define OPC_REGIM 0x1 |
|---|
| 700 | #define OPC_J 0x2 |
|---|
| 701 | #define OPC_JAL 0x3 |
|---|
| 702 | #define OPC_BEQ 0x4 |
|---|
| 703 | #define OPC_BNE 0x5 |
|---|
| 704 | #define OPC_BLEZ 0x6 |
|---|
| 705 | #define OPC_BGTZ 0x7 |
|---|
| 706 | #define OPC_COP1 0x11 |
|---|
| 707 | #define OPC_JALX 0x1D |
|---|
| 708 | #define OPC_BEQL 0x14 |
|---|
| 709 | #define OPC_BNEL 0x15 |
|---|
| 710 | #define OPC_BLEZL 0x16 |
|---|
| 711 | #define OPC_BGTZL 0x17 |
|---|
| 712 | |
|---|
| 713 | /* Instruction function fields */ |
|---|
| 714 | #define FUNC_JR 0x8 |
|---|
| 715 | #define FUNC_JALR 0x9 |
|---|
| 716 | |
|---|
| 717 | /* Instruction rt fields */ |
|---|
| 718 | #define RT_BLTZ 0x0 |
|---|
| 719 | #define RT_BGEZ 0x1 |
|---|
| 720 | #define RT_BLTZL 0x2 |
|---|
| 721 | #define RT_BGEZL 0x3 |
|---|
| 722 | #define RT_BLTZAL 0x10 |
|---|
| 723 | #define RT_BGEZAL 0x11 |
|---|
| 724 | #define RT_BLTZALL 0x12 |
|---|
| 725 | #define RT_BGEZALL 0x13 |
|---|
| 726 | |
|---|
| 727 | /* Instruction rs fields */ |
|---|
| 728 | #define RS_BC1 0x08 |
|---|
| 729 | |
|---|
| 730 | /* Access macros for instruction fields */ |
|---|
| 731 | #define MIPS_OPCODE( instr) ((instr) >> 26) |
|---|
| 732 | #define MIPS_FUNCTION(instr) ((instr) & MSK(6)) |
|---|
| 733 | #define MIPS_RT(instr) (((instr) >> 16) & MSK(5)) |
|---|
| 734 | #define MIPS_RS(instr) (((instr) >> 21) & MSK(5)) |
|---|
| 735 | #define MIPS_OFFSET(instr) ((instr) & 0xFFFF) |
|---|
| 736 | #define MIPS_TARGET(instr) ((instr) & MSK(26)) |
|---|
| 737 | |
|---|
| 738 | /* Instructions */ |
|---|
| 739 | #define OPCODE_DERET 0x4200001f |
|---|
| 740 | #define OPCODE_BREAK 0x0005000d |
|---|
| 741 | #define OPCODE_NOP 0 |
|---|
| 742 | #define OPCODE_JUMP(addr) ( (OPC_J << 26) | (((addr) >> 2) & 0x3FFFFFF) ) |
|---|
| 743 | |
|---|
| 744 | #define DERET .##word OPCODE_DERET |
|---|
| 745 | |
|---|
| 746 | /* MIPS16e opcodes and instruction field access macros */ |
|---|
| 747 | |
|---|
| 748 | #define MIPS16E_OPCODE(inst) (((inst) >> 11) & 0x1f) |
|---|
| 749 | #define MIPS16E_I8_FUNCTION(inst) (((inst) >> 8) & 0x7) |
|---|
| 750 | #define MIPS16E_X(inst) (((inst) >> 26) & 0x1) |
|---|
| 751 | #define MIPS16E_RR_FUNCTION(inst) (((inst) >> 0) & 0x1f) |
|---|
| 752 | #define MIPS16E_RY(inst) (((inst) >> 5) & 0x3) |
|---|
| 753 | #define MIPS16E_OPC_EXTEND 0x1e |
|---|
| 754 | #define MIPS16E_OPC_JAL_X 0x03 |
|---|
| 755 | #define MIPS16E_OPC_B 0x02 |
|---|
| 756 | #define MIPS16E_OPC_BEQZ 0x04 |
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| 757 | #define MIPS16E_OPC_BNEZ 0x05 |
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| 758 | #define MIPS16E_OPC_I8 0x0c |
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| 759 | #define MIPS16E_I8_FUNC_BTEQZ 0x00 |
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| 760 | #define MIPS16E_I8_FUNC_BTNEZ 0x01 |
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| 761 | #define MIPS16E_X_JALX 0x01 |
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| 762 | #define MIPS16E_OPC_RR 0x1d |
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| 763 | #define MIPS16E_RR_FUNC_JALRC 0x00 |
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| 764 | #define MIPS16E_RR_RY_JRRX 0x00 |
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| 765 | #define MIPS16E_RR_RY_JRRA 0x01 |
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| 766 | #define MIPS16E_RR_RY_JALR 0x02 |
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| 767 | #define MIPS16E_RR_RY_JRCRX 0x04 |
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| 768 | #define MIPS16E_RR_RY_JRCRA 0x05 |
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| 769 | #define MIPS16E_RR_RY_JALRC 0x06 |
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| 770 | |
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| 771 | #define MIPS16E_OPCODE_BREAK 0xE805 |
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| 772 | #define MIPS16E_OPCODE_NOP 0x6500 |
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| 773 | |
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| 774 | /* MIPS reset vector */ |
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| 775 | #define MIPS_RESET_VECTOR 0x1fc00000 |
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| 776 | |
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| 777 | /* Clock periods per count register increment */ |
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| 778 | #define MIPS4K_COUNT_CLK_PER_CYCLE 2 |
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| 779 | #define MIPS5K_COUNT_CLK_PER_CYCLE 2 |
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| 780 | #define MIPS20Kc_COUNT_CLK_PER_CYCLE 1 |
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| 781 | |
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| 782 | |
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| 783 | /**** MIPS 4K/5K families specific fields of CONFIG register ****/ |
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| 784 | |
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| 785 | #define C0_CONFIG_MIPS4K5K_K23_SHF S_ConfigK23 |
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| 786 | #define C0_CONFIG_MIPS4K5K_K23_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_K23_SHF) |
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| 787 | |
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| 788 | #define C0_CONFIG_MIPS4K5K_KU_SHF S_ConfigKU |
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| 789 | #define C0_CONFIG_MIPS4K5K_KU_MSK (MSK(3) << C0_CONFIG_MIPS4K5K_KU_SHF) |
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| 790 | |
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| 791 | |
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| 792 | /**** MIPS 20Kc specific fields of CONFIG register ****/ |
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| 793 | |
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| 794 | #define C0_CONFIG_MIPS20KC_EC_SHF 28 |
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| 795 | #define C0_CONFIG_MIPS20KC_EC_MSK (MSK(3) << C0_CONFIG_MIPS20KC_EC_SHF) |
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| 796 | |
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| 797 | #define C0_CONFIG_MIPS20KC_DD_SHF 27 |
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| 798 | #define C0_CONFIG_MIPS20KC_DD_MSK (MSK(1) << C0_CONFIG_MIPS20KC_DD_SHF) |
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| 799 | #define C0_CONFIG_MIPS20KC_DD_BIT C0_CONFIG_MIPS20KC_DD_MSK |
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| 800 | |
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| 801 | #define C0_CONFIG_MIPS20KC_LP_SHF 26 |
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| 802 | #define C0_CONFIG_MIPS20KC_LP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_LP_SHF) |
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| 803 | #define C0_CONFIG_MIPS20KC_LP_BIT C0_CONFIG_MIPS20KC_LP_MSK |
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| 804 | |
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| 805 | #define C0_CONFIG_MIPS20KC_SP_SHF 25 |
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| 806 | #define C0_CONFIG_MIPS20KC_SP_MSK (MSK(1) << C0_CONFIG_MIPS20KC_SP_SHF) |
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| 807 | #define C0_CONFIG_MIPS20KC_SP_BIT C0_CONFIG_MIPS20KC_SP_MSK |
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| 808 | |
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| 809 | #define C0_CONFIG_MIPS20KC_TI_SHF 24 |
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| 810 | #define C0_CONFIG_MIPS20KC_TI_MSK (MSK(1) << C0_CONFIG_MIPS20KC_TI_SHF) |
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| 811 | #define C0_CONFIG_MIPS20KC_TI_BIT C0_CONFIG_MIPS20KC_TI_MSK |
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| 812 | |
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| 813 | |
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| 814 | /* ********************************************************************* */ |
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| 815 | /* Interface function definition */ |
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| 816 | |
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| 817 | |
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| 818 | /* ********************************************************************* */ |
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| 819 | |
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| 820 | #endif /* #ifndef __MIPS_H__ */ |
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