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bhdm_priv.c

Last change on this file was 2, checked in by phkim, 11 years ago

1.phkim

revision copy newcon3sk r27

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1	/***************************************************************************
2	* (c)2004-2010 Broadcom Corporation
3	*
4	* This program is the proprietary software of Broadcom Corporation and/or its licensors,
5	* and may only be used, duplicated, modified or distributed pursuant to the terms and
6	* conditions of a separate, written license agreement executed between you and Broadcom
7	* (an "Authorized License"). Except as set forth in an Authorized License, Broadcom grants
8	* no license (express or implied), right to use, or waiver of any kind with respect to the
9	* Software, and Broadcom expressly reserves all rights in and to the Software and all
10	* intellectual property rights therein. IF YOU HAVE NO AUTHORIZED LICENSE, THEN YOU
11	* HAVE NO RIGHT TO USE THIS SOFTWARE IN ANY WAY, AND SHOULD IMMEDIATELY
12	* NOTIFY BROADCOM AND DISCONTINUE ALL USE OF THE SOFTWARE.
13	*
14	* Except as expressly set forth in the Authorized License,
15	*
16	* 1. This program, including its structure, sequence and organization, constitutes the valuable trade
17	* secrets of Broadcom, and you shall use all reasonable efforts to protect the confidentiality thereof,
18	* and to use this information only in connection with your use of Broadcom integrated circuit products.
19	*
20	* 2. TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
21	* AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES, REPRESENTATIONS OR
22	* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
23	* THE SOFTWARE. BROADCOM SPECIFICALLY DISCLAIMS ANY AND ALL IMPLIED WARRANTIES
24	* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE,
25	* LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION
26	* OR CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING OUT OF
27	* USE OR PERFORMANCE OF THE SOFTWARE.
28	*
29	* 3. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL BROADCOM OR ITS
30	* LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, INCIDENTAL, SPECIAL, INDIRECT, OR
31	* EXEMPLARY DAMAGES WHATSOEVER ARISING OUT OF OR IN ANY WAY RELATING TO YOUR
32	* USE OF OR INABILITY TO USE THE SOFTWARE EVEN IF BROADCOM HAS BEEN ADVISED OF
33	* THE POSSIBILITY OF SUCH DAMAGES; OR (ii) ANY AMOUNT IN EXCESS OF THE AMOUNT
34	* ACTUALLY PAID FOR THE SOFTWARE ITSELF OR U.S. $1, WHICHEVER IS GREATER. THESE
35	* LIMITATIONS SHALL APPLY NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF
36	* ANY LIMITED REMEDY.
37	*
38	* $brcm_Workfile: bhdm_priv.c $
39	* $brcm_Revision: Hydra_Software_Devel/43 $
40	* $brcm_Date: 3/9/12 6:52p $
41	*
42	* Module Description:
43	*
44	* Revision History:
45	*
46	* $brcm_Log: /magnum/portinginterface/hdm/7422/bhdm_priv.c $
47	*
48	* Hydra_Software_Devel/43 3/9/12 6:52p vle
49	* SW7435-44: Update HDMI_TX_PHY channel swap settings for all 40nm
50	* platforms. Future platforms relies on the default values
51	*
52	* Hydra_Software_Devel/42 3/7/12 11:00a rgreen
53	* SW7425-2515: Remove CEC code; see bcec pi
54	*
55	* Hydra_Software_Devel/42 3/7/12 10:52a rgreen
56	* SW7425-2515: Remove CEC code; see bcec pi
57	*
58	* Hydra_Software_Devel/41 2/9/12 3:59p rgreen
59	* SW7231-345,SW7125-1146,SW7425-2361: Refactor HDMI Power Management;
60	* separate TMDS power from clock
61	*
62	* Hydra_Software_Devel/40 1/27/12 2:10p vle
63	* SW7125-1146: merge to mainline
64	*
65	* Hydra_Software_Devel/SW7125-1146/1 1/26/12 5:35p vle
66	* SW7125-1146: Get RSEN setting at isr vs event time for applicable
67	* platforms
68	*
69	* Hydra_Software_Devel/39 1/23/12 4:46p rgreen
70	* SW7125-1146, SW7231-345,SW7346-234: Remove enable/disable of RSEN
71	* interrupt from EnableTmdsOutput; Get RSEN setting at isr vs event time
72	*
73	* Hydra_Software_Devel/38 1/23/12 1:31p rgreen
74	* SW7125-1146: Add BHDM_GetReceiverSense_isr support for 40nm
75	*
76	* Hydra_Software_Devel/37 1/6/12 6:03p vle
77	* SW7435-11: implement support for check/clearHotplugInterrupt for 7435
78	*
79	* Hydra_Software_Devel/36 1/6/12 5:06p vle
80	* SW7425-1890: Update HDMI pre_emphasis settings for 480p/576p 12bit deep
81	* color with 4x pixel repitition
82	*
83	* Hydra_Software_Devel/35 1/6/12 2:59p vle
84	* SW7435-11: Add support for 7435
85	*
86	* Hydra_Software_Devel/34 1/3/12 3:27p vle
87	* SW7358-203: Merged to mainline.
88	*
89	* Hydra_Software_Devel/33 12/22/11 3:35p vle
90	* SW7425-1890: Update HDMI pre_emphasis settings based on output format.
91	*
92	* Hydra_Software_Devel/bdvd_v4.0/2 12/19/11 1:52p rbshah
93	* SWBLURAY-26245:[ see Broadcom Issue Tracking JIRA for more info ]
94	*
95	* Hydra_Software_Devel/32 12/8/11 4:40p rgreen
96	* SW7358-194: use BCHP_PWR_RESOURCE_HDMI_TX macro consistently
97	*
98	* Hydra_Software_Devel/31 12/8/11 4:29p rgreen
99	* SW7358-194: After checking RxSense, disable TMDS lines if previously
100	* disabled
101	*
102	* Hydra_Software_Devel/30 11/22/11 6:02p vle
103	* SW7425-1140: Merge to mainline. Remove all CEC functionality out of
104	* HDM PI.
105	*
106	* Hydra_Software_Devel/SW7425-1140/2 11/22/11 5:48p vle
107	* SW7425-1140: Add BHDM_CONFIG_CEC_LEGACY_SUPPORT for backward compatible
108	* for CEC legacy platforms.
109	*
110	* Hydra_Software_Devel/SW7425-1140/1 11/16/11 12:17p vle
111	* SW7425-1140: Remove all CEC functionalities out of HDM PI
112	*
113	* Hydra_Software_Devel/29 11/14/11 2:16p rgreen
114	* SW7425-1710: Update BHDM_CONFIG macro usage. Describe specific
115	* functionality vs chip process
116	*
117	* Hydra_Software_Devel/28 10/28/11 1:20p rgreen
118	* SW7425-1629: Update hardware generation of GCP packet
119	*
120	* Hydra_Software_Devel/27 10/3/11 5:15p rgreen
121	* SW7425-158: Update internal status of TMDS lines to avoid unnecessary
122	* warning for mute/unmute when TMDS is powered down
123	*
124	* Hydra_Software_Devel/26 8/26/11 5:09p vle
125	* SW7231-322: Add support for 7231B0
126	*
127	* Hydra_Software_Devel/25 8/23/11 5:16p vle
128	* SW7231-345: Disable RxSense interrupt when TDMS lines are disabled.
129	*
130	* Hydra_Software_Devel/24 8/17/11 6:38p vle
131	* SW7231-322: Add support for 7231B0
132	*
133	* Hydra_Software_Devel/23 8/9/11 11:38a vle
134	* SWBLURAY-26743: Merge to mainline
135	*
136	* Hydra_Software_Devel/SWBLURAY-26743/1 8/8/11 4:58p rbshah
137	* SWBLURAY-26743:[ see Broadcom Issue Tracking JIRA for more info ]
138	*
139	* Hydra_Software_Devel/22 7/27/11 5:57p vle
140	* SW7346-348: Merge to main line. Do not toggle TMDS lines when checking
141	* RxSense.
142	*
143	* Hydra_Software_Devel/21 7/26/11 3:55p vle
144	* SW7346-319: Make sure HDMI_TX_PHY PLL is not in reset
145	*
146	* Hydra_Software_Devel/SW7346-348/1 7/22/11 4:09p vle
147	* SW7346-348: back out changes in JIRA SW7408-290
148	*
149	* Hydra_Software_Devel/20 7/15/11 5:12p vle
150	* SW7422-462: Update N & CTS values for 32 and 44.1Khz, 148.5/1.001Mhz
151	* pixel clock, 12bit deep color
152	*
153	* Hydra_Software_Devel/19 7/1/11 11:21a vle
154	* SW7422-459: fix indent
155	*
156	* Hydra_Software_Devel/18 7/1/11 10:48a vle
157	* SW7422-459: merge bdvd changes to mainline
158	*
159	* Hydra_Software_Devel/bdvd_v4.0/3 6/30/11 4:06p rbshah
160	* SWBLURAY-26245:[ see Broadcom Issue Tracking JIRA for more info ]
161	*
162	* Hydra_Software_Devel/17 6/28/11 5:58p vle
163	* SW7346-234: Merge to mainline
164	*
165	* Hydra_Software_Devel/SW7346-234/2 6/28/11 5:56p vle
166	* SW7346-234: Disable RSEN interrupt until the PHY is powered on. TAKE 2
167	*
168	* Hydra_Software_Devel/SW7346-234/1 6/24/11 6:07p vle
169	* SW7346-234: Disable RSEN interrupt until the PHY is powered on.
170	*
171	* Hydra_Software_Devel/15 6/24/11 1:54p vle
172	* SW7408-290: Make sure to disable TMDS lines appropriately when checking
173	* for receiver sense.
174	*
175	* Hydra_Software_Devel/14 6/13/11 6:08p vle
176	* SW7231-147: Tweak Pre-emphasis settings for some 40nm A0 platforms to
177	* fix HDMI eye diagram issue in 1080p 8bit color depth
178	*
179	* Hydra_Software_Devel/13 5/6/11 1:12p vle
180	* SW7231-128: Add power management support for 40nm platforms
181	*
182	* Hydra_Software_Devel/12 4/26/11 3:32p vle
183	* SW7125-798: Remove unused variable - fix compiler warning
184	*
185	* Hydra_Software_Devel/11 4/25/11 7:31p vle
186	* SW7125-798: fix no hdmi output issue on 7425/7231
187	*
188	* Hydra_Software_Devel/10 4/22/11 11:37a vle
189	* SW7125-798: Add API to allow customer to control pre-emphasis settings
190	*
191	* Hydra_Software_Devel/9 3/21/11 7:08p vle
192	* SW7550-664: Fix HDMI 4.1 output channel order
193	*
194	* Hydra_Software_Devel/8 12/22/10 11:40a vle
195	* SW7344-11: Configure HDMI_TX_PHY.CHANNEL_SWAP for 40nm platforms. Not
196	* all chips can use the default values.
197	*
198	* Hydra_Software_Devel/7 12/21/10 3:34p vle
199	* SW7422-130: Merge to main branch
200	*
201	* Hydra_Software_Devel/SW7422-130/1 12/20/10 7:46p vle
202	* SW7422-130: When configure HDMI in master mode, do not RECENTER fifo
203	* and USE_FULL has to be set to 0
204	*
205	* Hydra_Software_Devel/6 12/17/10 2:36p vle
206	* SW7344-11: Update support for 7344/7346 and all other 40nm platform due
207	* to RDB update
208	*
209	* Hydra_Software_Devel/5 11/24/10 11:13a vle
210	* SW7422-97: Update HDMI PHY Settings for 40nm core.
211	*
212	* Hydra_Software_Devel/4 11/11/10 2:08p vle
213	* SW7422-23: TMDS lines need to be powered on for RxSense to work.
214	*
215	* Hydra_Software_Devel/3 11/11/10 11:07a vle
216	* SW7422-12: SW_INIT register doesn't require atomic access Power on PHY,
217	* default is powered down.
218	*
219	* Hydra_Software_Devel/3 11/11/10 11:05a vle
220	* SW7422-12: SW_INIT register doesn't require Atomic access. Power on PHY
221	*
222	* Hydra_Software_Devel/2 9/29/10 4:14p vle
223	* SW7422-23: Fix build issues without CEC enable
224	*
225	* Hydra_Software_Devel/1 9/28/10 7:25p vle
226	* SW7422-23: Add support for 7422
227	*
228	***************************************************************************/
229
230	#include "bhdm.h"
231	#include "bhdm_priv.h"
232
233	BDBG_MODULE(BHDM_PRIV) ;
234
235	#define BHDM_CHECK_RC( rc, func ) \
236	do \
237	{ \
238	if( (rc = BERR_TRACE(func)) != BERR_SUCCESS ) \
239	{ \
240	goto done; \
241	} \
242	} while(0)
243
244
245	/******************************************************************************
246	Summary:
247	HDMI Pixel Clock Rate Text - Useful for debug messages
248	NOTE: These entries match the number of entries in the BHDM_RM_VideoRates Table
249	*******************************************************************************/
250	#if BDBG_DEBUG_BUILD
251	const char *BHDM_PixelClockText[BHDM_PixelClock_eCount] =
252	{
253	/* 8bit standard mode */
254	"25.2",
255	"25.2 / 1.001",
256
257	"27",
258	"27 * 1.001",
259
260	"54",
261	"54 * 1.001",
262
263	"74.25",
264	"74.25 / 1.001",
265
266	"108",
267	"108 * 1.001",
268
269	"148.5",
270	"148.5 / 1.001",
271
272
273	/* 10bit deep color mode */
274	"31.5",
275	"31.5 / 1.001",
276
277	"33.75",
278	"33.75 * 1.001",
279
280	"67.5",
281	"67.5 * 1.001",
282
283	"92.8125",
284	"92.8125 / 1.001",
285
286	"135",
287	"135 * 1.001",
288
289	"185.625",
290	"185.625 / 1.001",
291
292
293	/* 12bit deep color mode */
294	"37.8",
295	"37.8 / 1.001",
296
297	"40.5",
298	"40.5 * 1.001",
299
300	"81",
301	"81 * 1.001",
302
303	"111.375",
304	"111.375 / 1.001",
305
306	"162",
307	"162 * 1.001",
308
309	"222.75",
310	"222.75 / 1.001",
311
312
313	/* PC/DVI/custom clock rates */
314	"40.000000",
315	"65.000000",
316	"64.935065",
317
318	"60.375000",
319	"74.375000",
320	"64.000000",
321
322	"56.304000",
323	"67.4973027",
324	"67.565"
325
326	} ;
327	#endif
328
329
330	/* HDMI Rate Manager now updated by VDC for smoother transitions */
331	/******************************************************************************
332	Summary:
333	HDMI Audio Clock Capture and Regeneration Definition (See HDMI Spec Section 7)
334	NOTE: These entries match the number of entries in the BHDM_RM_VideoRates Table
335	*******************************************************************************/
336	typedef struct _BHDM_P_AUDIO_CLK_VALUES_
337	{
338	BHDM_InputPixelClock eInputPixelClock;
339	BAVC_HDMI_BitsPerPixel eBitsPerPixel;
340	uint32_t NValue ;
341	uint32_t HW_NValue ;
342	uint32_t CTS_0 ;
343	uint32_t CTS_1 ;
344	uint32_t CTS_PERIOD_0;
345	uint32_t CTS_PERIOD_1;
346	uint32_t CTS_0_REPEAT;
347	uint32_t CTS_1_REPEAT;
348	} BHDM_P_AUDIO_CLK_VALUES ;
349
350
351	/******************************************************************************
352	Summary:
353	HDMI Audio Clock Capture and Regeneration Values for 32kHz
354	NOTE: These entries match the number of entries in the BHDM_RM_VideoRates Table
355	*******************************************************************************/
356	static const BHDM_P_AUDIO_CLK_VALUES BHDM_32KHz_AudioClkValues[] =
357	{ /* InputPixelClock BitsPerPixel SW-N HW-N CTS_0 CTS_1 PERIOD REPEAT */
358
359	/***** 8bit standard mode ******/
360	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e24bit, 4096, 4096, 25200, 25200, 32, 32, 1, 1 },
361	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 4576, 4096, 28125, 28125, 35, 36, 1, 3 },
362
363	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e24bit, 4096, 4096, 27000, 27000, 32, 32, 1, 1 },
364	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 4096, 4096, 27027, 27027, 32, 32, 1, 1 },
365
366	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e24bit, 4096, 4096, 54000, 54000, 32, 32, 1, 1 },
367	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 4096, 4096, 54054, 54054, 32, 32, 1, 1 },
368
369	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e24bit, 4096, 4096, 74250, 74250, 32, 32, 1, 1 },
370	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 11648, 11648, 210937, 210938, 91, 91, 1, 1 },
371
372	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e24bit, 4096, 4096, 108000, 108000, 32, 32, 1, 1 },
373	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 4096, 4096, 108108, 108108, 32, 32, 1, 1 },
374
375	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e24bit, 4096, 4096, 148500, 148500, 32, 32, 1, 1 },
376	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 11648, 11648, 421875, 421875, 91, 91, 1, 1 },
377
378
379	/****** 10bit deep color mode *******/
380	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e30bit, 4096, 4096, 31500, 31500, 32, 32, 1, 1 },
381	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 4096, 4096, 31468, 31469, 32, 32, 1, 1 },
382
383	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e30bit, 4096, 4096, 33750, 33750, 32, 32, 1, 1 },
384	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 8192, 8192, 67567, 67568, 64, 64, 1, 1 },
385
386	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e30bit, 4096, 4096, 67500, 67500, 32, 32, 1, 1 },
387	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 4096, 4096, 67567, 67568, 32, 32, 1, 1 },
388
389	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e30bit, 4096, 4096, 92812, 92813, 32, 32, 1, 1 },
390	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 11648, 11648, 263671, 263672, 91, 91, 1, 9 },
391
392	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e30bit, 4096, 4096, 135000, 135000, 32, 32, 1, 1 },
393	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 4096, 4096, 135135, 135135, 32, 32, 1, 1 },
394
395	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e30bit, 4096, 4096, 185625, 185625, 32, 32, 1, 1 },
396	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 11648, 11648, 527343, 527344, 91, 91, 1, 4 },
397
398
399	/****** 12bit deep color mode *******/
400	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e36bit, 4096, 4096, 37800, 37800, 32, 32, 1, 1 },
401	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 9152, 4096, 84375, 84375, 71, 72, 1, 1 },
402
403	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e36bit, 4096, 4096, 40500, 40500, 32, 32, 1, 1 },
404	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 8192, 8192, 81081, 81081, 64, 64, 1, 1 },
405
406	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e36bit, 4096, 4096, 81000, 81000, 32, 32, 1, 1 },
407	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 4096, 4096, 81081, 81081, 32, 32, 1, 1 },
408
409	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e36bit, 4096, 4096, 111375, 111375, 32, 32, 1, 1 },
410	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 11648, 11648, 316406, 316407, 91, 91, 7, 3 },
411
412	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e36bit, 4096, 4096, 162000, 162000, 32, 32, 1, 1 },
413	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 4096, 4096, 162162, 162162, 32, 32, 1, 1 },
414
415	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e36bit, 4096, 4096, 222750, 222750, 32, 32, 1, 1 },
416	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 4096, 4096, 222527, 222528, 32, 32, 1, 1 },
417
418
419	/* PC/custom formats */
420	{ BHDM_PixelClock_e40, BAVC_HDMI_BitsPerPixel_e24bit, 4096, 4096, 40000, 40000, 32, 32, 1, 1 },
421	{ BHDM_PixelClock_e65, BAVC_HDMI_BitsPerPixel_e24bit, 4096, 4096, 65000, 65000, 32, 32, 1, 1 },
422	{ BHDM_PixelClock_e65_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 4096, 4096, 64935, 64936, 32, 32, 9, 1 },
423	} ;
424
425
426	/******************************************************************************
427	Summary:
428	HDMI Audio Clock Capture and Regeneration Values for 44.1kHz
429	NOTE: These entries match the number of entries in the BHDM_RM_VideoRates Table
430	*******************************************************************************/
431	static const BHDM_P_AUDIO_CLK_VALUES BHDM_44_1KHz_AudioClkValues[] =
432	{ /* InputPixelClock BitsPerPixel SW-N HW-N CTS_0 CTS_1 PERIOD REPEAT */
433
434	/****** 8bit standard mode *******/
435	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e24bit, 6272, 6272, 28000, 28000, 49, 49, 1, 1 },
436	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 7007, 6272, 31250, 31250, 54, 55, 33, 95 },
437
438	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e24bit, 6272, 6272, 30000, 30000, 49, 49, 1, 1 },
439	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 6272, 6272, 30030, 30030, 49, 49, 1, 1 },
440
441	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e24bit, 6272, 6272, 60000, 60000, 49, 49, 1, 1 },
442	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 6272, 6272, 60060, 60060, 49, 49, 1, 1 },
443
444	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e24bit, 6272, 6272, 82500, 82500, 49, 49, 1, 1 },
445	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 17836, 6272, 234375, 234375, 139, 140, 21, 11 },
446
447	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e24bit, 6272, 6272, 120000, 120000, 49, 49, 1, 1 },
448	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 6272, 6272, 120120, 120120, 49, 49, 1, 1 },
449
450	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e24bit, 6272, 6272, 165000, 165000, 49, 49, 1, 1 },
451	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 8918, 6272, 234375, 234375, 69, 70, 21, 43 },
452
453
454	/****** 10bit deep color mode *******/
455	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e30bit, 6272, 6272, 35000, 35000, 49, 49, 1, 1 },
456	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 6272, 6272, 34965, 34965, 49, 49, 1, 1 },
457
458	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e30bit, 6272, 6272, 37500, 37500, 49, 49, 1, 1 },
459	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 6272, 6272, 37537, 37538, 49, 49, 1, 1 },
460
461	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e30bit, 6272, 6272, 75000, 75000, 49, 49, 1, 1 },
462	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 6272, 6272, 75075, 75075, 49, 49, 1, 1 },
463
464	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e30bit, 6272, 6272, 103125, 103125, 49, 49, 1, 1 },
465	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 6272, 6272, 103022, 103022, 49, 49, 1, 1 },
466
467	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e30bit, 6272, 6272, 150000, 150000, 49, 49, 1, 1 },
468	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 6272, 6272, 150150, 150150, 49, 49, 1, 1 },
469
470	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e30bit, 6272, 6272, 206250, 206250, 49, 49, 1, 1 },
471	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 6272, 6272, 206044, 206044, 49, 49, 1, 1 },
472
473
474	/****** 12bit deep color mode *******/
475	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e36bit, 6272, 6272, 42000, 42000, 49, 49, 1, 1 },
476	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 7007, 6272, 46875, 46875, 54, 55, 33, 95 },
477
478	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e36bit, 6272, 6272, 45000, 45000, 49, 49, 1, 1 },
479	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 6272, 6272, 45045, 45045, 49, 49, 1, 1 },
480
481	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e36bit, 6272, 6272, 90000, 90000, 49, 49, 1, 1 },
482	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 6272, 6272, 90090, 90090, 49, 49, 1, 1 },
483
484	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e36bit, 6272, 6272, 123750, 123750, 49, 49, 1, 1 },
485	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 6272, 6272, 123626, 123627, 49, 49, 3, 2 },
486
487	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e36bit, 6272, 6272, 180000, 180000, 49, 49, 1, 1 },
488	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 6272, 6272, 180180, 180180, 49, 49, 1, 1 },
489
490	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e36bit, 6272, 6272, 247500, 247500, 49, 49, 1, 1 },
491	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 6272, 6272, 247252, 247253, 49, 49, 3, 7 },
492
493
494	/* PC/custom formats */
495	{ BHDM_PixelClock_e40, BAVC_HDMI_BitsPerPixel_e24bit, 6272, 6272, 44444, 44445, 49, 49, 6, 4 },
496	{ BHDM_PixelClock_e65, BAVC_HDMI_BitsPerPixel_e24bit, 6272, 6272, 72222, 72223, 49, 49, 8, 2 },
497	{ BHDM_PixelClock_e65_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 6272, 6272, 72150, 72151, 49, 49, 9, 1 },
498	} ;
499
500
501	/******************************************************************************
502	Summary:
503	HDMI Audio Clock Capture and Regeneration Values for 48kHz
504	NOTE: These entries match the number of entries in the BHDM_RM_VideoRates Table
505	*******************************************************************************/
506	static const BHDM_P_AUDIO_CLK_VALUES BHDM_48KHz_AudioClkValues[] =
507	{ /* InputPixelClock BitsPerPixel SW-N HW-N CTS_0 CTS_1 PERIOD REPEAT */
508
509	/****** 8bit standard mode *******/
510	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e24bit, 6144, 6144, 25200, 25200, 48, 48, 1, 1 },
511	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 6864, 6144, 28125, 28125, 53, 54, 3, 5 },
512
513	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e24bit, 6144, 6144, 27000, 27000, 48, 48, 1, 1 },
514	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 6144, 6144, 27027, 27027, 48, 48, 1, 1 },
515
516	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e24bit, 6144, 6144, 54000, 54000, 48, 48, 1, 1 },
517	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 6144, 6144, 54054, 54054, 48, 48, 1, 1 },
518
519	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e24bit, 6144, 6144, 74250, 74250, 48, 48, 1, 1 },
520	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 11648, 11648, 140625, 140625, 91, 91, 1, 1 },
521
522	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e24bit, 6144, 6144, 108000, 108000, 48, 48, 1, 1 },
523	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 6144, 6144, 108108, 108108, 48, 48, 1, 1 },
524
525	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e24bit, 6144, 6144, 148500, 148500, 48, 48, 1, 1 },
526	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 5824, 11648, 140625, 140625, 45, 46, 1, 1 },
527
528
529	/****** 10bit deep color mode *******/
530	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e30bit, 6144, 6144, 31500, 31500, 48, 48, 1, 1 },
531	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 9152, 6144, 46875, 46875, 71, 72, 1, 1 },
532
533	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e30bit, 6144, 6144, 33750, 33750, 48, 48, 1, 1 },
534	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 8192, 8192, 45045, 45045, 64, 64, 1, 1 },
535
536	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e30bit, 6144, 6144, 67500, 67500, 48, 48, 1, 1 },
537	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 6144, 6144, 67567, 67568, 48, 48, 1, 1 },
538
539	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e30bit, 6144, 6144, 92812, 92813, 48, 48, 1, 1 },
540	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 9472, 9472, 142943, 142943, 74, 74, 1, 1 },
541
542	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e30bit, 6144, 6144, 135000, 135000, 48, 48, 1, 1 },
543	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 6144, 6144, 135135, 135135, 48, 48, 1, 1 },
544
545	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e30bit, 6144, 6144, 185625, 185625, 48, 48, 1, 1 },
546	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 11648, 11648, 351562, 351563, 91, 91, 1, 1 },
547
548	/****** 12bit deep color mode *******/
549	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e36bit, 6144, 6144, 37800, 37800, 48, 48, 1, 1 },
550	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 9152, 6144, 56250, 56250, 71, 72, 1, 1 },
551
552	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e36bit, 6144, 6144, 40500, 40500, 48, 48, 1, 1 },
553	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 8192, 8192, 54054, 54054, 64, 64, 1, 1 },
554
555	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e36bit, 6144, 6144, 81000, 81000, 48, 48, 1, 1 },
556	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 6144, 6144, 81081, 81081, 48, 48, 1, 1 },
557
558	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e36bit, 6144, 6144, 111375, 111375, 48, 48, 1, 1 },
559	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 11648, 11648, 210937, 210938, 91, 91, 1, 1 },
560
561	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e36bit, 6144, 6144, 162000, 162000, 48, 48, 1, 1 },
562	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 6144, 6144, 162162, 162162, 48, 48, 1, 1 },
563
564	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e36bit, 6144, 6144, 222750, 222750, 48, 48, 1, 1 },
565	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 11648, 11648, 421875, 421875, 91, 91, 1, 1 },
566
567
568	/* PC/custom formats */
569	{ BHDM_PixelClock_e40, BAVC_HDMI_BitsPerPixel_e24bit, 6144, 6144, 40000, 40000, 48, 48, 1, 1 },
570	{ BHDM_PixelClock_e65, BAVC_HDMI_BitsPerPixel_e24bit, 6144, 6144, 65000, 65000, 48, 48, 1, 1 },
571	{ BHDM_PixelClock_e65_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 6144, 6144, 64935, 64936, 48, 48, 9, 1 },
572	} ;
573
574
575	#if BHDM_CONFIG_88_2KHZ_AUDIO_SUPPORT
576	/******************************************************************************
577	Summary:
578	HDMI Audio Clock Capture and Regeneration Values for 88.2kHz
579	NOTE: These entries match the number of entries in the BHDM_RM_VideoRates Table
580	*******************************************************************************/
581	static BHDM_P_AUDIO_CLK_VALUES BHDM_88_2KHz_AudioClkValues[] =
582	{ /* SW-N HW-N CTS_0 CTS_1 PERIOD REPEAT */
583	/****** 8bit standard mode *******/
584	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e24bit, 12544, 12544, 28000, 28000, 98, 98, 1, 1 },
585	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 14014, 12544, 31250, 31250, 109, 110, 33, 31 },
586
587	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e24bit, 12544, 12544, 30000, 30000, 98, 98, 1, 1 },
588	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 12544, 12544, 30030, 30030, 98, 98, 1, 1 },
589
590	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e24bit, 12544, 12544, 60000, 60000, 98, 98, 1, 1 },
591	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 12544, 12544, 60060, 60060, 98, 98, 1, 1 },
592
593	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e24bit, 12544, 12544, 82500, 82500, 98, 98, 1, 1 },
594	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 35672, 12544, 234375, 234375, 278, 279, 5, 11 },
595
596	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e24bit, 12544, 12544, 120000, 120000, 98, 98, 1, 1 },
597	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 12544, 12544, 120120, 120120, 98, 98, 1, 1 },
598
599	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e24bit, 12544, 12544, 165000, 165000, 98, 98, 1, 1 },
600	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 17836, 12544, 234375, 234375, 139, 140, 21, 11 },
601
602	/****** 10bit deep color mode *******/
603	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e30bit, 12544, 12544, 35000, 35000, 98, 98, 1, 1 },
604	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 12544, 12544, 34965, 34965, 98, 98, 1, 1 },
605
606	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e30bit, 12544, 12544, 37500, 37500, 98, 98, 1, 1 },
607	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 12544, 12544, 37537, 37538, 98, 98, 1, 1 },
608
609	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e30bit, 12544, 12544, 75000, 75000, 98, 98, 1, 1 },
610	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 12544, 12544, 75075, 75075, 98, 98, 1, 1 },
611
612	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e30bit, 12544, 12544, 103125, 103125, 98, 98, 1, 1 },
613	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 12544, 12544, 103022, 103022, 98, 98, 1, 1 },
614
615	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e30bit, 12544, 12544, 150000, 150000, 98, 98, 1, 1 },
616	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 12544, 12544, 150150, 150150, 98, 98, 1, 1 },
617
618	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e30bit, 12544, 12544, 206250, 206250, 98, 98, 1, 1 },
619	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 12544, 12544, 206044, 206044, 98, 98, 1, 1 },
620
621	/****** 12bit deep color mode *******/
622	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e36bit, 12544, 12544, 42000, 42000, 98, 98, 1, 1 },
623	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 14014, 12544, 46875, 46875, 109, 110, 33, 31 },
624
625	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e36bit, 12544, 12544, 45000, 45000, 98, 98, 1, 1 },
626	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 12544, 12544, 45045, 45045, 98, 98, 1, 1 },
627
628	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e36bit, 12544, 12544, 90000, 90000, 98, 98, 1, 1 },
629	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 12544, 12544, 90090, 90090, 98, 98, 1, 1 },
630
631	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e36bit, 12544, 12544, 123750, 123750, 98, 98, 1, 1 },
632	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 12544, 12544, 123626, 123627, 98, 98, 3, 2 },
633
634	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e36bit, 12544, 12544, 180000, 180000, 98, 98, 1, 1 },
635	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 12544, 12544, 180180, 180180, 98, 98, 1, 1 },
636
637	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e36bit, 12544, 12544, 247500, 247500, 98, 98, 1, 1 },
638	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 35672, 12544, 703125, 703125, 278, 279, 5, 11 },
639	} ;
640	#endif
641
642
643	#if BHDM_CONFIG_96KHZ_AUDIO_SUPPORT
644	/******************************************************************************
645	Summary:
646	HDMI Audio Clock Capture and Regeneration Values for 96kHz
647	NOTE: These entries match the number of entries in the BHDM_RM_VideoRates Table
648	*******************************************************************************/
649	static const BHDM_P_AUDIO_CLK_VALUES BHDM_96KHz_AudioClkValues[] =
650	{ /* InputPixelClock BitsPerPixel SW-N HW-N CTS_0 CTS_1 PERIOD REPEAT */
651
652	/****** 8bit standard mode *******/
653	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e24bit, 12288, 12288, 25200, 25200, 96, 96, 1, 1 },
654	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 13728, 12288, 28125, 28125, 107, 108, 3, 1 },
655
656	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e24bit, 12288, 12288, 27000, 27000, 96, 96, 1, 1 },
657	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 12288, 12288, 27027, 27027, 96, 96, 1, 1 },
658
659	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e24bit, 12288, 12288, 54000, 54000, 96, 96, 1, 1 },
660	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 12288, 12288, 54054, 54054, 96, 96, 1, 1 },
661
662	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e24bit, 12288, 12288, 74250, 74250, 96, 96, 1, 1 },
663	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 23296, 23296, 140625, 140625, 182, 182, 1, 1 },
664
665	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e24bit, 12288, 12288, 108000, 108000, 96, 96, 1, 1 },
666	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 12288, 12288, 108108, 108108, 96, 96, 1, 1 },
667
668	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e24bit, 12288, 12288, 148500, 148500, 96, 96, 1, 1 },
669	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 11648, 11648, 140625, 140625, 91, 91, 1, 1 },
670
671
672	/****** 10bit deep color mode *******/
673	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e30bit, 12288, 12288, 31500, 31500, 96, 96, 1, 1 },
674	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 18304, 18304, 46875, 46875, 143, 143, 1, 1 },
675
676	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e30bit, 12288, 12288, 33750, 33750, 96, 96, 1, 1 },
677	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 16384, 16384, 45045, 45045, 128, 128, 1, 1 },
678
679	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e30bit, 12288, 12288, 67500, 67500, 96, 96, 1, 1 },
680	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 12288, 12288, 67567, 67568, 96, 96, 1, 1 },
681
682	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e30bit, 12288, 12288, 92812, 92813, 96, 96, 1, 1 },
683	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 18944, 18944, 142943, 142943, 148, 148, 1, 1 },
684
685	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e30bit, 12288, 12288, 135000, 135000, 96, 96, 1, 1 },
686	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 12288, 12288, 135135, 135135, 96, 96, 1, 1 },
687
688	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e30bit, 12288, 12288, 185625, 185625, 96, 96, 1, 1 },
689	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 23296, 23296, 351562, 351563, 182, 182, 1, 1 },
690
691
692	/****** 12bit deep color mode *******/
693	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e36bit, 12288, 12288, 37800, 37800, 96, 96, 1, 1 },
694	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 18304, 18304, 56250, 56250, 143, 143, 1, 1 },
695
696	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e36bit, 12288, 12288, 40500, 40500, 96, 96, 1, 1 },
697	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 16384, 16384, 54054, 54054, 128, 128, 1, 1 },
698
699	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e36bit, 12288, 12288, 81000, 81000, 96, 96, 1, 1 },
700	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 12288, 12288, 81081, 81081, 96, 96, 1, 1 },
701
702	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e36bit, 12288, 12288, 111375, 111375, 96, 96, 1, 1 },
703	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 23296, 23296, 210937, 210938, 182, 182, 1, 1 },
704
705	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e36bit, 12288, 12288, 162000, 162000, 96, 96, 1, 1 },
706	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 12288, 12288, 162162, 162162, 96, 96, 1, 1 },
707
708	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e36bit, 12288, 12288, 222750, 222750, 96, 96, 1, 1 },
709	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 23296, 23296, 421875, 421875, 182, 182, 1, 1 },
710
711
712	/* PC/custom formats */
713	{ BHDM_PixelClock_e40, BAVC_HDMI_BitsPerPixel_e24bit, 12288, 12288, 40000, 40000, 96, 96, 1, 1 },
714	{ BHDM_PixelClock_e65, BAVC_HDMI_BitsPerPixel_e24bit, 12288, 12288, 65000, 65000, 96, 96, 1, 1 },
715	{ BHDM_PixelClock_e65_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 12288, 12288, 64935, 64936, 96, 96, 9, 1 },
716	} ;
717	#endif
718
719
720	#if BHDM_CONFIG_176_4KHZ_AUDIO_SUPPORT
721	/******************************************************************************
722	Summary:
723	HDMI Audio Clock Capture and Regeneration Values for 176.4kHz
724	NOTE: These entries match the number of entries in the BHDM_RM_VideoRates Table
725	*******************************************************************************/
726	static const BHDM_P_AUDIO_CLK_VALUES BHDM_176_4KHz_AudioClkValues[] =
727	{ /* InputPixelClock BitsPerPixel SW-N HW-N CTS_0 CTS_1 PERIOD REPEAT */
728
729	/****** 8bit standard mode *******/
730	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e24bit, 25088, 25088, 28000, 28000, 196, 196, 1, 1 },
731	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 28028, 25088, 31250, 31250, 218, 219, 1, 31 },
732
733	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e24bit, 25088, 25088, 30000, 30000, 196, 196, 1, 1 },
734	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 25088, 25088, 30030, 30030, 196, 196, 1, 1 },
735
736	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e24bit, 25088, 25088, 60000, 60000, 196, 196, 1, 1 },
737	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 25088, 25088, 60060, 60060, 196, 196, 1, 1 },
738
739	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e24bit, 25088, 25088, 82500, 82500, 196, 196, 1, 1 },
740	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 71344, 25088, 234375, 234375, 557, 558, 5, 3 },
741
742	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e24bit, 25088, 25088, 120000, 120000, 196, 196, 1, 1 },
743	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 25088, 25088, 120120, 120120, 196, 196, 1, 1 },
744
745	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e24bit, 25088, 25088, 165000, 165000, 196, 196, 1, 1 },
746	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 35672, 25088, 234375, 234375, 278, 279, 5, 11 },
747
748
749	/****** 10bit deep color mode *******/
750	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e30bit, 25088, 25088, 35000, 35000, 196, 196, 1, 1 },
751	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 25088, 25088, 34965, 34965, 196, 196, 1, 1 },
752
753	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e30bit, 25088, 25088, 37500, 37500, 196, 196, 1, 1 },
754	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 25088, 25088, 37537, 37538, 196, 196, 1, 1 },
755
756	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e30bit, 25088, 25088, 75000, 75000, 196, 196, 1, 1 },
757	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 25088, 25088, 75075, 75075, 196, 196, 1, 1 },
758
759	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e30bit, 25088, 25088, 103125, 103125, 196, 196, 1, 1 },
760	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 25088, 25088, 103022, 103022, 196, 196, 1, 1 },
761
762	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e30bit, 25088, 25088, 150000, 150000, 196, 196, 1, 1 },
763	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 25088, 25088, 150150, 150150, 196, 196, 1, 1 },
764
765	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e30bit, 25088, 25088, 206250, 206250, 196, 196, 1, 1 },
766	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 25088, 25088, 206044, 206044, 196, 196, 1, 1 },
767
768
769	/****** 12bit deep color mode *******/
770	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e36bit, 25088, 25088, 42000, 42000, 196, 196, 1, 1 },
771	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 28028, 25088, 46875, 46875, 218, 219, 1, 31 },
772
773	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e36bit, 25088, 25088, 45000, 45000, 196, 196, 1, 1 },
774	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 25088, 25088, 45045, 45045, 196, 196, 1, 1 },
775
776	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e36bit, 25088, 25088, 90000, 90000, 196, 196, 1, 1 },
777	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 25088, 25088, 90090, 90090, 196, 196, 1, 1 },
778
779	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e36bit, 25088, 25088, 123750, 123750, 196, 196, 1, 1 },
780	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 25088, 25088, 123626, 123627, 196, 196, 3, 2 },
781
782	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e36bit, 25088, 25088, 180000, 180000, 196, 196, 1, 1 },
783	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 25088, 25088, 180180, 180180, 196, 196, 1, 1 },
784
785	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e36bit, 25088, 25088, 247500, 247500, 196, 196, 1, 1 },
786	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 71344, 25088, 703125, 703125, 557, 558, 5, 3 },
787
788
789	/* PC/custom formats */
790	{ BHDM_PixelClock_e40, BAVC_HDMI_BitsPerPixel_e24bit, 25088, 25088, 44444, 44445, 196, 196, 6, 4 },
791	{ BHDM_PixelClock_e65, BAVC_HDMI_BitsPerPixel_e24bit, 25088, 25088, 72222, 72223, 196, 196, 8, 2 },
792	{ BHDM_PixelClock_e65_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 25088, 25088, 72150, 72151, 196, 196, 9, 1 },
793	} ;
794	#endif
795
796
797	#if BHDM_CONFIG_192KHZ_AUDIO_SUPPORT
798	/******************************************************************************
799	Summary:
800	HDMI Audio Clock Capture and Regeneration Values for 192kHz
801	NOTE: These entries match the number of entries in the BHDM_RM_VideoRates Table
802	*******************************************************************************/
803	static const BHDM_P_AUDIO_CLK_VALUES BHDM_192KHz_AudioClkValues[] =
804	{ /* InputPixelClock BitsPerPixel SW-N HW-N CTS_0 CTS_1 PERIOD REPEAT */
805
806	/****** 8bit standard mode *******/
807	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e24bit, 24576, 24576, 25200, 25200, 192, 192, 1, 1 },
808	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 27456, 24576, 28125, 28125, 214, 215, 1, 1 },
809
810	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e24bit, 24576, 24576, 27000, 27000, 192, 192, 1, 1 },
811	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 24576, 24576, 27027, 27027, 192, 192, 1, 1 },
812
813	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e24bit, 24576, 24576, 54000, 54000, 192, 192, 1, 1 },
814	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 24576, 24576, 54054, 54054, 192, 192, 1, 1 },
815
816	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e24bit, 24576, 24576, 74250, 74250, 192, 192, 1, 1 },
817	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 46592, 46592, 140625, 140625, 364, 364, 1, 1 },
818
819	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e24bit, 24576, 24576, 108000, 108000, 192, 192, 1, 1 },
820	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 24576, 24576, 108108, 108108, 192, 192, 1, 1 },
821
822	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e24bit, 24576, 24576, 148500, 148500, 192, 192, 1, 1 },
823	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 23296, 23296, 140625, 140625, 182, 182, 1, 1 },
824
825
826	/****** 10bit deep color mode *******/
827	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e30bit, 24576, 24576, 31500, 31500, 192, 192, 1, 1 },
828	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 36608, 36608, 46875, 46875, 286, 286, 1, 1 },
829
830	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e30bit, 24576, 24576, 33750, 33750, 192, 192, 1, 1 },
831	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 32768, 32768, 45045, 45045, 256, 256, 1, 1 },
832
833	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e30bit, 24576, 24576, 67500, 67500, 192, 192, 1, 1 },
834	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 24576, 24576, 67567, 67568, 192, 192, 1, 1 },
835
836	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e30bit, 24576, 24576, 92812, 92813, 192, 192, 1, 1 },
837	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 37888, 37888, 142943, 142943, 296, 296, 1, 1 },
838
839	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e30bit, 24576, 24576, 135000, 135000, 192, 192, 1, 1 },
840	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 24576, 24576, 135135, 135135, 192, 192, 1, 1 },
841
842	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e30bit, 24576, 24576, 185625, 185625, 192, 192, 1, 1 },
843	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, 46592, 46592, 351562, 351563, 364, 364, 1, 1 },
844
845
846	/****** 12bit deep color mode *******/
847	{ BHDM_PixelClock_e25_2, BAVC_HDMI_BitsPerPixel_e36bit, 24576, 24576, 37800, 37800, 192, 192, 1, 1 },
848	{ BHDM_PixelClock_e25_2_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 36608, 36608, 56250, 56250, 286, 286, 1, 1 },
849
850	{ BHDM_PixelClock_e27, BAVC_HDMI_BitsPerPixel_e36bit, 24576, 24576, 40500, 40500, 192, 192, 1, 1 },
851	{ BHDM_PixelClock_e27_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 32768, 32768, 54054, 54054, 256, 256, 1, 1 },
852
853	{ BHDM_PixelClock_e54, BAVC_HDMI_BitsPerPixel_e36bit, 24576, 24576, 81000, 81000, 192, 192, 1, 1 },
854	{ BHDM_PixelClock_e54_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 24576, 24576, 81081, 81081, 192, 192, 1, 1 },
855
856	{ BHDM_PixelClock_e74_25, BAVC_HDMI_BitsPerPixel_e36bit, 24576, 24576, 111375, 111375, 192, 192, 1, 1 },
857	{ BHDM_PixelClock_e74_25_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 46592, 46592, 210937, 210938, 364, 364, 1, 1 },
858
859	{ BHDM_PixelClock_e108, BAVC_HDMI_BitsPerPixel_e36bit, 24576, 24576, 162000, 162000, 192, 192, 1, 1 },
860	{ BHDM_PixelClock_e108_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 24576, 24576, 162162, 162162, 192, 192, 1, 1 },
861
862	{ BHDM_PixelClock_e148_5, BAVC_HDMI_BitsPerPixel_e36bit, 24576, 24576, 222750, 222750, 192, 192, 1, 1 },
863	{ BHDM_PixelClock_e148_5_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, 46592, 46592, 421875, 421875, 364, 364, 1, 1 },
864
865
866	/* PC/custom formats */
867	{ BHDM_PixelClock_e40, BAVC_HDMI_BitsPerPixel_e24bit, 24576, 24576, 40000, 40000, 192, 192, 1, 1 },
868	{ BHDM_PixelClock_e65, BAVC_HDMI_BitsPerPixel_e24bit, 24576, 24576, 65000, 65000, 192, 192, 1, 1 },
869	{ BHDM_PixelClock_e65_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, 24576, 24576, 64935, 64936, 192, 192, 9, 1 },
870	} ;
871	#endif
872
873
874	BERR_Code BHDM_P_ConfigurePhy(BHDM_Handle hHDMI, BHDM_Settings *NewHdmiSettings)
875	{
876	BERR_Code rc = BERR_SUCCESS ;
877	BHDM_PreEmphasis_Configuration stPreEmphasisConfig;
878
879	BDBG_ENTER(BHDM_P_ConfigurePhy) ;
880	BDBG_ASSERT( hHDMI ) ;
881
882	rc = BHDM_GetPreEmphasisConfiguration(hHDMI, &stPreEmphasisConfig);
883	if (rc) BERR_TRACE(rc);
884
885	/*** Additional setup of Tx PHY */
886	switch (NewHdmiSettings->eInputVideoFmt)
887	{
888	case BFMT_VideoFmt_e1080p:
889	case BFMT_VideoFmt_e1080p_50Hz:
890	switch (NewHdmiSettings->stColorDepth.eBitsPerPixel)
891	{
892	case BAVC_HDMI_BitsPerPixel_e24bit:
893
894	stPreEmphasisConfig.uiHfEn = 3;
895	stPreEmphasisConfig.uiPreEmphasis_Ch0 = 0x3c;
896	stPreEmphasisConfig.uiPreEmphasis_Ch1 = 0x3c;
897	stPreEmphasisConfig.uiPreEmphasis_Ch2 = 0x3c;
898	stPreEmphasisConfig.uiPreEmphasis_CK = 0x3c;
899	break;
900
901	case BAVC_HDMI_BitsPerPixel_e30bit:
902	stPreEmphasisConfig.uiHfEn = 1;
903	stPreEmphasisConfig.uiPreEmphasis_Ch0 = 0x2d;
904	stPreEmphasisConfig.uiPreEmphasis_Ch1 = 0x2d;
905	stPreEmphasisConfig.uiPreEmphasis_Ch2 = 0x2d;
906	stPreEmphasisConfig.uiPreEmphasis_CK = 0x2d;
907	break;
908
909	case BAVC_HDMI_BitsPerPixel_e36bit:
910	stPreEmphasisConfig.uiHfEn = 3;
911	stPreEmphasisConfig.uiPreEmphasis_Ch0 = 0x7f;
912	stPreEmphasisConfig.uiPreEmphasis_Ch1 = 0x7f;
913	stPreEmphasisConfig.uiPreEmphasis_Ch2 = 0x7f;
914	stPreEmphasisConfig.uiPreEmphasis_CK = 0x7f;
915	break;
916
917	default:
918	BDBG_ERR(("Unknown color depth")) ;
919	rc = BERR_INVALID_PARAMETER ;
920	goto done ;
921	}
922	break;
923
924	case BFMT_VideoFmt_e480p :
925	case BFMT_VideoFmt_e576p_50Hz :
926	if ((NewHdmiSettings->ePixelRepetition == BAVC_HDMI_PixelRepetition_e4x) &&
927	(NewHdmiSettings->stColorDepth.eBitsPerPixel == BAVC_HDMI_BitsPerPixel_e36bit))
928	{
929	stPreEmphasisConfig.uiHfEn = 3;
930	stPreEmphasisConfig.uiPreEmphasis_Ch0 = 0x3c;
931	stPreEmphasisConfig.uiPreEmphasis_Ch1 = 0x3c;
932	stPreEmphasisConfig.uiPreEmphasis_Ch2 = 0x3c;
933	stPreEmphasisConfig.uiPreEmphasis_CK = 0x3c;
934	}
935	break;
936
937	default:
938	stPreEmphasisConfig.uiHfEn = 0;
939	stPreEmphasisConfig.uiPreEmphasis_Ch0 = 0xa;
940	stPreEmphasisConfig.uiPreEmphasis_Ch1 = 0xa;
941	stPreEmphasisConfig.uiPreEmphasis_Ch2 = 0xa;
942	stPreEmphasisConfig.uiPreEmphasis_CK = 0xa;
943	break;
944	}
945
946	/* Set pre-emp configuration */
947	BHDM_SetPreEmphasisConfiguration(hHDMI, &stPreEmphasisConfig);
948
949	done:
950
951	BDBG_LEAVE(BHDM_P_ConfigurePhy);
952	return rc;
953	}
954
955
956
957	/******************************************************************************
958	BERR_Code BHDM_EnableTmdsOutput_isr
959	Summary: Enable (Display) TMDS Output
960	*******************************************************************************/
961	void BHDM_P_EnableTmdsOutput_isr(
962	BHDM_Handle hHDMI, /* [in] HDMI handle */
963	bool bEnableTmdsOutput /* [in] boolean to enable/disable */
964	)
965	{
966	uint32_t Register ;
967	uint32_t TmdsOutput ;
968
969	BDBG_ENTER(BHDM_P_EnableTmdsOutput_isr) ;
970	BDBG_ASSERT( hHDMI ) ;
971
972	#if BHDM_CONFIG_DVO_SUPPORT
973	/* TMDS is always off when DVO is enabled */
974	bEnableTmdsOutput = false ;
975	#endif
976
977	if (bEnableTmdsOutput)
978	TmdsOutput = 0x0 ; /* TMDS ON */
979	else
980	TmdsOutput = 0x1 ; /* TMDS OFF */
981
982	#if BHDM_CONFIG_DEBUG_TMDS
983	BDBG_WRN(("Confgure TMDS %s", TmdsOutput ? "OFF" : "ON"));
984	#endif
985
986	Register = BREG_Read32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_POWERDOWN_CTL) ;
987
988	/* set TMDS lines to power on*/
989	Register &=
990	~( BCHP_MASK(HDMI_TX_PHY_POWERDOWN_CTL, TX_CK_PWRDN)
991	\| BCHP_MASK(HDMI_TX_PHY_POWERDOWN_CTL, TX_2_PWRDN)
992	\| BCHP_MASK(HDMI_TX_PHY_POWERDOWN_CTL, TX_1_PWRDN)
993	\| BCHP_MASK(HDMI_TX_PHY_POWERDOWN_CTL, TX_0_PWRDN)) ;
994
995	/* set TMDS lines to requested value on/off */
996	Register \|=
997	BCHP_FIELD_DATA(HDMI_TX_PHY_POWERDOWN_CTL, TX_CK_PWRDN, TmdsOutput)
998	\| BCHP_FIELD_DATA(HDMI_TX_PHY_POWERDOWN_CTL, TX_2_PWRDN, TmdsOutput)
999	\| BCHP_FIELD_DATA(HDMI_TX_PHY_POWERDOWN_CTL, TX_1_PWRDN, TmdsOutput)
1000	\| BCHP_FIELD_DATA(HDMI_TX_PHY_POWERDOWN_CTL, TX_0_PWRDN, TmdsOutput) ;
1001
1002	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_POWERDOWN_CTL, Register) ;
1003
1004	/* take TMDS lines out of reset */
1005	Register = BREG_Read32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_RESET_CTL) ;
1006	Register &=
1007	~( BCHP_MASK(HDMI_TX_PHY_RESET_CTL, TX_CK_RESET)
1008	\| BCHP_MASK(HDMI_TX_PHY_RESET_CTL, TX_2_RESET)
1009	\| BCHP_MASK(HDMI_TX_PHY_RESET_CTL, TX_1_RESET)
1010	\| BCHP_MASK(HDMI_TX_PHY_RESET_CTL, TX_0_RESET)) ;
1011
1012	Register \|=
1013	BCHP_FIELD_DATA(HDMI_TX_PHY_RESET_CTL, PLL_RESETB, 1)
1014	\| BCHP_FIELD_DATA(HDMI_TX_PHY_RESET_CTL, PLLDIV_RSTB, 1) ;
1015	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_RESET_CTL, Register) ;
1016
1017	/* remember current TMDS setting... */
1018	hHDMI->tmdsEnabled = bEnableTmdsOutput ;
1019
1020	BDBG_LEAVE(BHDM_P_EnableTmdsOutput_isr) ;
1021	}
1022
1023
1024	/******************************************************************************
1025	BERR_Code BHDM_EnableTmdsOutput
1026	Summary: Enable (Display) TMDS Output
1027	*******************************************************************************/
1028	BERR_Code BHDM_EnableTmdsOutput(
1029	BHDM_Handle hHDMI, /* [in] HDMI handle */
1030	bool bEnableTmdsOutput /* [in] boolean to enable/disable */
1031	)
1032	{
1033	BERR_Code rc = BERR_SUCCESS;
1034
1035	BDBG_ENTER(BHDM_EnableTmdsOutput) ;
1036	BDBG_ASSERT( hHDMI ) ;
1037
1038	BKNI_EnterCriticalSection() ;
1039	BHDM_P_EnableTmdsOutput_isr(hHDMI, bEnableTmdsOutput) ;
1040	BKNI_LeaveCriticalSection() ;
1041
1042	BDBG_LEAVE(BHDM_EnableTmdsOutput) ;
1043	return rc ;
1044	}
1045
1046
1047	/******************************************************************************
1048	BERR_Code BHDM_SetAudioMute
1049	Summary: Implements HDMI Audio (only) mute enable/disable.
1050	*******************************************************************************/
1051	BERR_Code BHDM_SetAudioMute(
1052	BHDM_Handle hHDMI, /* [in] HDMI handle */
1053	bool bEnableAudioMute /* [in] boolean to enable/disable */
1054	)
1055	{
1056	BERR_Code rc = BERR_SUCCESS;
1057	BDBG_ENTER(BHDM_SetAudioMute) ;
1058
1059	#if BHDM_CONFIG_AUDIO_MAI_BUS_DISABLE_SUPPORT
1060	{
1061	uint32_t Register ;
1062	BDBG_ASSERT( hHDMI );
1063
1064	/* AudioMute valid for HDMI only */
1065	if (hHDMI->DeviceSettings.eOutputFormat != BHDM_OutputFormat_eHDMIMode)
1066	{
1067	BDBG_WRN(("Audio Mute only application in HDMI mode."));
1068	return BERR_INVALID_PARAMETER;
1069	}
1070	Register = BREG_Read32(hHDMI->hRegister, BCHP_HDMI_MAI_CONFIG) ;
1071	if (bEnableAudioMute) {
1072	Register \|= BCHP_FIELD_DATA(HDMI_MAI_CONFIG, DISABLE_MAI_AUDIO, 1) ;
1073	}
1074	else
1075	{
1076	Register &= ~BCHP_MASK(HDMI_MAI_CONFIG, DISABLE_MAI_AUDIO);
1077	}
1078	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_MAI_CONFIG, Register) ;
1079
1080	hHDMI->AudioMuteState = bEnableAudioMute ;
1081	BDBG_MSG(("AudioMute %d", bEnableAudioMute)) ;
1082	}
1083	#else
1084
1085	BSTD_UNUSED(hHDMI) ;
1086	BSTD_UNUSED(bEnableAudioMute) ;
1087
1088	#endif
1089
1090	BDBG_LEAVE(BHDM_SetAudioMute) ;
1091	return rc ;
1092	} /* END BHDM_SetAudioMute */
1093
1094
1095	/***************************************************************************
1096	BHDM_AudioVideoRateChangeCB_isr
1097	Summary: Configure the Rate Manager to match the Rate Manager for the
1098	Video Display System.
1099	****************************************************************************/
1100	void BHDM_AudioVideoRateChangeCB_isr(
1101	BHDM_Handle hHDMI,
1102	int CallbackType,
1103	void *pvAudioOrVideoData)
1104	{
1105	#if BDBG_DEBUG_BUILD
1106	static char *AudioSampleRateText[] = { "32kHz", "44.1kHz", "48kHz", "96kHz" ,"16kHz", "22_05kHz",
1107	"24kHz", "64kHz", "88_2kHz", "128kHz", "176_4kHz", "192kHz", "8kHz", "12kHz", "11_025kHz"} ;
1108	#endif
1109
1110	uint32_t Register ;
1111	bool masterMode;
1112	typedef struct BHDM_BAVC_Clock
1113	{
1114	uint32_t ulPixelClkRate ;
1115	BAVC_HDMI_BitsPerPixel eBitsPerPixel;
1116	BAVC_HDMI_PixelRepetition ePixelRepetition;
1117	BHDM_InputPixelClock eInputPixelClock ;
1118	} BHDM_BAVC_Clock ;
1119
1120	static const BHDM_BAVC_Clock BHDM_SupportedClocks[] =
1121	{
1122	/* 8bit standard mode */
1123	{BFMT_PXL_25_2MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e25_2}, /* 25.2 */
1124	{BFMT_PXL_25_2MHz_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e25_2_DIV_1_001}, /* 25.1748 */
1125
1126	{BFMT_PXL_27MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e27}, /* 27 */
1127	{BFMT_PXL_27MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e27_MUL_1_001}, /* 27.027 */
1128
1129	/**********************
1130	* Currently, for orthogonal VEC platforms (7420, 7342, 7550, etc.), the VEC always run at 54Mhz for 480p format, regardless of pixel repetition
1131	* If no pixel repetition, VEC runs at 54Mhz but downsample to 27Mhz before feeding into HDMI
1132	* If 2x pixel repetition is enabled, VEC runs at 54Mhz but will not downsample.
1133	* Thus, during the callback, the rate is always 54Mhz
1134	***********************/
1135	{BFMT_PXL_54MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e27_480p}, /* 27 */
1136	{BFMT_PXL_54MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e27_MUL_1_001_480p}, /* 27.027 */
1137
1138	{BFMT_PXL_54MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_e2x, BHDM_PixelClock_e54}, /* 27x2 (2x pixel repetition) */
1139	{BFMT_PXL_54MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_e2x, BHDM_PixelClock_e54_MUL_1_001}, /* 27.027x2 (2x pixel repetition) */
1140
1141	{BFMT_PXL_27MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_e2x, BHDM_PixelClock_e54}, /* 27x2 (2x pixel repetition) */
1142	{BFMT_PXL_27MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_e2x, BHDM_PixelClock_e54_MUL_1_001}, /* 27.027x2 (2x pixel repetition) */
1143
1144	{BFMT_PXL_74_25MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e74_25}, /* 74.25 */
1145	{BFMT_PXL_74_25MHz_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e74_25_DIV_1_001}, /* 74.17582 */
1146
1147	{BFMT_PXL_27MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_e4x, BHDM_PixelClock_e108}, /* 27x4 (4x pixel repetition) */
1148	{BFMT_PXL_27MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_e4x, BHDM_PixelClock_e108_MUL_1_001}, /* 27.027x4 (4x pixel repetition) */
1149
1150	{BFMT_PXL_54MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_e4x, BHDM_PixelClock_e108}, /* 27x4 (4x pixel repetition) */
1151	{BFMT_PXL_54MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_e4x, BHDM_PixelClock_e108_MUL_1_001}, /* 27x4 (4x pixel repetition) */
1152
1153	{BFMT_PXL_148_5MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e148_5}, /* 148.5 */
1154	{BFMT_PXL_148_5MHz_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e148_5_DIV_1_001}, /* 148.35165 */
1155
1156
1157	/* 10bit deep color mode */
1158	{BFMT_PXL_25_2MHz, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e31_5}, /* 31.5 */
1159	{BFMT_PXL_25_2MHz_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e31_5_DIV_1_001}, /* 31.4685 */
1160
1161	{BFMT_PXL_27MHz, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e33_75}, /* 33.75 */
1162	{BFMT_PXL_27MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e33_75_MUL_1_001}, /* 33.78375 */
1163
1164	/**********************
1165	* Currently, for orthogonal VEC platforms (7420, 7342, 7550, etc.), the VEC always run at 54Mhz for 480p format, regardless of pixel repetition
1166	* If no pixel repetition, VEC runs at 54Mhz but downsample to 27Mhz before feeding into HDMI
1167	* If 2x pixel repetition is enabled, VEC runs at 54Mhz but will not downsample.
1168	* Thus, during the callback, the rate is always 54Mhz
1169	***********************/
1170	{BFMT_PXL_54MHz, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e33_75_480p}, /* 33.75 */
1171	{BFMT_PXL_54MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e33_75_MUL_1_001_480p}, /* 33.78375 */
1172
1173	{BFMT_PXL_54MHz, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_e2x, BHDM_PixelClock_e67_5}, /* 33.75x2 (2x pixel repetition) */
1174	{BFMT_PXL_54MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_e2x, BHDM_PixelClock_e67_5_MUL_1_001}, /* 33.78375x2 (2x pixel repetition) */
1175
1176	{BFMT_PXL_27MHz, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_e2x, BHDM_PixelClock_e67_5}, /* 33.75x2 (2x pixel repetition) */
1177	{BFMT_PXL_27MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_e2x, BHDM_PixelClock_e67_5_MUL_1_001}, /* 33.78375x2 (2x pixel repetition) */
1178
1179	{BFMT_PXL_74_25MHz, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e92_8125}, /* 92.8125 */
1180	{BFMT_PXL_74_25MHz_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e92_8125_DIV_1_001}, /* 92.7198 */
1181
1182	{BFMT_PXL_27MHz, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_e4x, BHDM_PixelClock_e135}, /* 33.75x4 (4x pixel repetition) */
1183	{BFMT_PXL_27MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_e4x, BHDM_PixelClock_e135_MUL_1_001}, /* 33.78375x4 (4x pixel repetition) */
1184
1185	{BFMT_PXL_54MHz, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_e4x, BHDM_PixelClock_e135}, /* 33.75x4 (4x pixel repetition) */
1186	{BFMT_PXL_54MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_e4x, BHDM_PixelClock_e135_MUL_1_001}, /* 33.75x4 (4x pixel repetition) */
1187
1188	{BFMT_PXL_148_5MHz, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e185_625}, /* 185.625 */
1189	{BFMT_PXL_148_5MHz_DIV_1_001, BAVC_HDMI_BitsPerPixel_e30bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e185_625_DIV_1_001}, /* 185.4396 */
1190
1191
1192	/* 12bit deep color mode */
1193	{BFMT_PXL_25_2MHz, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e37_8}, /* 37.8 */
1194	{BFMT_PXL_25_2MHz_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e37_8_DIV_1_001}, /* 37.76223 */
1195
1196	{BFMT_PXL_27MHz, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e40_5}, /* 40.5 */
1197	{BFMT_PXL_27MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e40_5_MUL_1_001}, /* 40.54 */
1198
1199	/**********************
1200	* Currently, for orthogonal VEC platforms (7420, 7342, 7550, etc.), the VEC always run at 54Mhz for 480p format, regardless of pixel repetition
1201	* If no pixel repetition, VEC runs at 54Mhz but downsample to 27Mhz before feeding into HDMI
1202	* If 2x pixel repetition is enabled, VEC runs at 54Mhz but will not downsample.
1203	* Thus, during the callback, the rate is always 54Mhz
1204	***********************/
1205	{BFMT_PXL_54MHz, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e40_5_480p}, /* 40.5 */
1206	{BFMT_PXL_54MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e40_5_MUL_1_001_480p}, /* 40.54 */
1207
1208	{BFMT_PXL_54MHz, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_e2x, BHDM_PixelClock_e81}, /* 40.5x2 (2x pixel repetition) */
1209	{BFMT_PXL_54MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_e2x, BHDM_PixelClock_e81_MUL_1_001}, /* 40.54x2 (2x pixel repetition) */
1210
1211	{BFMT_PXL_27MHz, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_e2x, BHDM_PixelClock_e81}, /* 40.5x2 (2x pixel repetition) */
1212	{BFMT_PXL_27MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_e2x, BHDM_PixelClock_e81_MUL_1_001}, /* 40.54x2 (2x pixel repetition) */
1213
1214	{BFMT_PXL_74_25MHz, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e111_375}, /* 111.375 */
1215	{BFMT_PXL_74_25MHz_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e111_375_DIV_1_001}, /* 111.264 */
1216
1217	{BFMT_PXL_27MHz, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_e4x, BHDM_PixelClock_e162}, /* 40.5x4 (4x pixel repetition) */
1218	{BFMT_PXL_27MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_e4x, BHDM_PixelClock_e162_MUL_1_001}, /* 40.54x4 (4x pixel repetition) */
1219
1220	{BFMT_PXL_54MHz, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_e4x, BHDM_PixelClock_e162}, /* 40.5x4 (4x pixel repetition) */
1221	{BFMT_PXL_54MHz_MUL_1_001, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_e4x, BHDM_PixelClock_e162_MUL_1_001}, /* 40.5x4 (4x pixel repetition) */
1222
1223	{BFMT_PXL_148_5MHz, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e222_75}, /* 222.75 */
1224	{BFMT_PXL_148_5MHz_DIV_1_001, BAVC_HDMI_BitsPerPixel_e36bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e222_75_DIV_1_001}, /* 222.5275 */
1225
1226
1227	/* DVI/PC/custom pixel rate */
1228	{BFMT_PXL_40MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e40}, /* 40 MHz */
1229	{BFMT_PXL_65MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e65}, /* 65 MHz */
1230	{BFMT_PXL_65MHz_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e65_DIV_1_001}, /* 64.935 MHz */
1231
1232	{BFMT_PXL_60_375MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e60_375}, /* 60.375 */
1233	{BFMT_PXL_74_375MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e74_375}, /* 74.375 */
1234	{BFMT_PXL_64MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_e64}, /* 64.000 */
1235
1236
1237	{BFMT_PXL_56_304MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_eCUSTOM_1366x768p_50}, /* 1366x768 @ 50 */
1238	{BFMT_PXL_67_565MHz_DIV_1_001, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_eCUSTOM_1366x768p_5994}, /* 1366x768 @ 59.94 */
1239	{BFMT_PXL_67_565MHz, BAVC_HDMI_BitsPerPixel_e24bit, BAVC_HDMI_PixelRepetition_eNone, BHDM_PixelClock_eCUSTOM_1366x768p_60}, /* 1366x768 @ 60 */
1240	} ;
1241
1242
1243	BHDM_InputPixelClock eInputPixelClock ;
1244	uint8_t i ;
1245
1246	BAVC_VdcDisplay_Info pVdcRateInfo ; / VIDEO callback */
1247	uint32_t ulPixelClkRate; /* see defines in bfmt.h (Mhz) */
1248	uint32_t ulVertRefreshRate; /* see defines in bfmt.h (Mhz) */
1249	BAVC_HDMI_BitsPerPixel eBitsPerPixel;
1250	BAVC_HDMI_PixelRepetition ePixelRepetition;
1251	/* OR */
1252
1253	BAVC_Audio_Info pAudioData ; / AUDIO callback */
1254	BAVC_AudioSamplingRate eInputAudioSamplingRate ;
1255	BHDM_P_AUDIO_CLK_VALUES *pAudioParameters ;
1256
1257
1258	BDBG_ENTER(BHDM_AudioVideoRateChangeCB_isr) ;
1259
1260	if ((CallbackType != BHDM_Callback_Type_eVideoChange)
1261	&& (CallbackType != BHDM_Callback_Type_eAudioChange)
1262	&& (CallbackType != BHDM_Callback_Type_eManualAudioChange))
1263	{
1264	BDBG_ERR((
1265	"Error in Callback Type %d; Use BHDM_Callback_Type_eXXX as int argument",
1266	CallbackType)) ;
1267	goto done ;
1268	}
1269
1270	if (CallbackType == BHDM_Callback_Type_eVideoChange)
1271	{
1272	pVdcRateInfo = (BAVC_VdcDisplay_Info *) pvAudioOrVideoData ;
1273	ulPixelClkRate = pVdcRateInfo->ulPixelClkRate ;
1274	ulVertRefreshRate = pVdcRateInfo->ulVertRefreshRate ;
1275	eBitsPerPixel = hHDMI->DeviceSettings.stColorDepth.eBitsPerPixel;
1276	ePixelRepetition = hHDMI->DeviceSettings.ePixelRepetition;
1277	#if 0
1278	BDBG_MSG(("Refresh Rate: 0x%x PixelClock: %d",
1279	ulVertRefreshRate, ulPixelClkRate)) ;
1280	#endif
1281	BDBG_MSG(("\nVideo Rate Change Callback")) ;
1282
1283	eInputPixelClock = BHDM_PixelClock_eUnused ;
1284
1285	for (i = 0 ; i < sizeof(BHDM_SupportedClocks) / sizeof(BHDM_BAVC_Clock) ; i++)
1286	if ((ulPixelClkRate == BHDM_SupportedClocks[i].ulPixelClkRate) &&
1287	(eBitsPerPixel == BHDM_SupportedClocks[i].eBitsPerPixel) &&
1288	(ePixelRepetition == BHDM_SupportedClocks[i].ePixelRepetition))
1289	{
1290	eInputPixelClock = BHDM_SupportedClocks[i].eInputPixelClock ;
1291	break ;
1292	}
1293
1294	if (eInputPixelClock == BHDM_PixelClock_eUnused)
1295	{
1296	BDBG_ERR(("Unknown HDMI Pixel Clock Rate: %d", ulPixelClkRate)) ;
1297	goto done ;
1298	}
1299
1300	/* update our device settings to reflect the new Pixel Clock Rate in use */
1301	hHDMI->eInputPixelClock = eInputPixelClock ;
1302	eInputAudioSamplingRate = hHDMI->DeviceSettings.eAudioSamplingRate ;
1303
1304	BDBG_MSG(("\t************************************")) ;
1305	BDBG_MSG(("\t** Video Rate Manager Updated **")) ;
1306	BDBG_MSG(("\t************************************")) ;
1307	}
1308	else /* Audio Callback Only */
1309	{
1310	#if BDBG_DEBUG_BUILD
1311	if (CallbackType == BHDM_Callback_Type_eManualAudioChange) {
1312	BDBG_MSG(("\t********************************************")) ;
1313	BDBG_MSG(("\t** Manual Sample Rate Change Callback **")) ;
1314	BDBG_MSG(("\t*******************************************")) ;
1315	}
1316	else {
1317	BDBG_MSG(("\t*******************************************")) ;
1318	BDBG_MSG(("\t** Audio Sample Rate Change Callback **")) ;
1319	BDBG_MSG(("\t******************************************")) ;
1320	}
1321	#endif
1322
1323	/* get the new Audio Sampling Rate to use... */
1324	pAudioData = (BAVC_Audio_Info *) pvAudioOrVideoData ;
1325	eInputAudioSamplingRate = pAudioData->eAudioSamplingRate ;
1326	hHDMI->DeviceSettings.eAudioSamplingRate = pAudioData->eAudioSamplingRate ;
1327
1328	/* use current Pixel Clock Rate for adjusting the Audio parameters */
1329	eInputPixelClock = hHDMI->eInputPixelClock ;
1330	}
1331
1332
1333	/*
1334	** removed prior code to skip Audio Configuration when in DVI mode
1335	** or using the DVO port; configure HDMI Audio Registers regardless
1336	** of whether or not we are in HDMI mode
1337	*/
1338
1339
1340	/* configure Audio Registers regardless of format (DVI vs HDMI) */
1341
1342	/*
1343	** re-configure the HDMI Clock Regeneration Packet
1344	** even if it is DVI Only, CRP is used only HDMI mode
1345	**
1346	** CODE from removed function
1347	** BHDM_ConfigureAudioClockRegenerationPackets(hHDMI,
1348	** hHDMI->DeviceSettings.eAudioSamplingRate)) ;
1349	*/
1350
1351	/* First, determine what N(umerator) and CTS values */
1352	/* are to be used based on the Audio Rate */
1353	switch( eInputAudioSamplingRate )
1354	{
1355
1356	case BAVC_AudioSamplingRate_e32k :
1357	pAudioParameters = (BHDM_P_AUDIO_CLK_VALUES *) BHDM_32KHz_AudioClkValues ;
1358	break ;
1359
1360	case BAVC_AudioSamplingRate_e44_1k :
1361	pAudioParameters = (BHDM_P_AUDIO_CLK_VALUES *) BHDM_44_1KHz_AudioClkValues ;
1362	break ;
1363
1364	case BAVC_AudioSamplingRate_e48k :
1365	pAudioParameters = (BHDM_P_AUDIO_CLK_VALUES *) BHDM_48KHz_AudioClkValues ;
1366	break ;
1367
1368	#if BHDM_CONFIG_88_2KHZ_AUDIO_SUPPORT
1369	case BAVC_AudioSamplingRate_e88_2k :
1370	pAudioParameters = (BHDM_P_AUDIO_CLK_VALUES *) BHDM_88_2KHz_AudioClkValues ;
1371	break ;
1372	#endif
1373
1374	#if BHDM_CONFIG_96KHZ_AUDIO_SUPPORT
1375	case BAVC_AudioSamplingRate_e96k :
1376	pAudioParameters = (BHDM_P_AUDIO_CLK_VALUES *) BHDM_96KHz_AudioClkValues ;
1377	break ;
1378	#endif
1379
1380	#if BHDM_CONFIG_176_4KHZ_AUDIO_SUPPORT
1381	case BAVC_AudioSamplingRate_e176_4k :
1382	pAudioParameters = (BHDM_P_AUDIO_CLK_VALUES *) BHDM_176_4KHz_AudioClkValues ;
1383	break ;
1384	#endif
1385
1386	#if BHDM_CONFIG_192KHZ_AUDIO_SUPPORT
1387	case BAVC_AudioSamplingRate_e192k:
1388	pAudioParameters = (BHDM_P_AUDIO_CLK_VALUES *) BHDM_192KHz_AudioClkValues;
1389	break ;
1390	#endif
1391
1392	default :
1393	BDBG_ERR(("Unsupported eAudioSamplingRate eNumeration: %d",
1394	eInputAudioSamplingRate)) ;
1395	goto done ;
1396	}
1397
1398	#if BDBG_DEBUG_BUILD
1399	BDBG_MSG(("HDMI Audio Configuration:")) ;
1400	BDBG_MSG((" Pixel Clock Rate: %s", BHDM_PixelClockText[eInputPixelClock])) ;
1401
1402	if (eInputAudioSamplingRate < BAVC_AudioSamplingRate_eUnknown)
1403	BDBG_MSG((" Audio Sample Rate: %s", AudioSampleRateText[eInputAudioSamplingRate])) ;
1404	else
1405	BDBG_MSG((" Audio Sample Rate: Unknown")) ;
1406	#endif
1407
1408	/*
1409	* If HW (External) CTS, then we don't have to program any of
1410	* the CTS registers. If SW CTS, we get all the values from
1411	* our audio parameters table.
1412	*/
1413	Register = BCHP_FIELD_DATA(HDMI_CRP_CFG, reserved1, 0)
1414	\| BCHP_FIELD_DATA(HDMI_CRP_CFG, USE_MAI_BUS_SYNC_FOR_CTS_GENERATION, 1)
1415	\| BCHP_FIELD_DATA(HDMI_CRP_CFG, CRP_DISABLE, 0)
1416	\| BCHP_FIELD_DATA(HDMI_CRP_CFG, reserved0, 0);
1417
1418	/* HW (External) CTS */
1419	if (hHDMI->DeviceSettings.CalculateCts)
1420	{
1421	Register \|= BCHP_FIELD_DATA(HDMI_CRP_CFG, EXTERNAL_CTS_EN, 1)
1422	\| BCHP_FIELD_DATA(HDMI_CRP_CFG, N_VALUE, pAudioParameters[eInputPixelClock].HW_NValue);
1423	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_CRP_CFG, Register) ;
1424
1425	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_CTS_0, 0) ;
1426	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_CTS_1, 0) ;
1427	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_CTS_PERIOD_0, 0) ;
1428	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_CTS_PERIOD_1, 0) ;
1429	}
1430	else /* SW CTS */
1431	{
1432	Register \|= BCHP_FIELD_DATA(HDMI_CRP_CFG, EXTERNAL_CTS_EN, 0)
1433	\| BCHP_FIELD_DATA(HDMI_CRP_CFG, N_VALUE, pAudioParameters[eInputPixelClock].NValue);
1434	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_CRP_CFG, Register) ;
1435
1436	Register = BCHP_FIELD_DATA(HDMI_CTS_0, reserved0, 0)
1437	\| BCHP_FIELD_DATA(HDMI_CTS_0, CTS_0, pAudioParameters[eInputPixelClock].CTS_0) ;
1438	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_CTS_0, Register) ;
1439
1440	Register = BCHP_FIELD_DATA(HDMI_CTS_1, reserved0, 0)
1441	\| BCHP_FIELD_DATA(HDMI_CTS_1, CTS_1, pAudioParameters[eInputPixelClock].CTS_1) ;
1442	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_CTS_1, Register) ;
1443
1444	Register = BCHP_FIELD_DATA(HDMI_CTS_PERIOD_0, CTS_0_REPEAT, pAudioParameters[eInputPixelClock].CTS_0_REPEAT)
1445	\| BCHP_FIELD_DATA(HDMI_CTS_PERIOD_0, reserved0, 0)
1446	\| BCHP_FIELD_DATA(HDMI_CTS_PERIOD_0, CTS_PERIOD_0, pAudioParameters[eInputPixelClock].CTS_PERIOD_0) ;
1447	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_CTS_PERIOD_0, Register) ;
1448
1449	Register = BCHP_FIELD_DATA(HDMI_CTS_PERIOD_1, CTS_1_REPEAT, pAudioParameters[eInputPixelClock].CTS_1_REPEAT)
1450	\| BCHP_FIELD_DATA(HDMI_CTS_PERIOD_1, reserved0, 0)
1451	\| BCHP_FIELD_DATA(HDMI_CTS_PERIOD_1, CTS_PERIOD_1, pAudioParameters[eInputPixelClock].CTS_PERIOD_1) ;
1452	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_CTS_PERIOD_1, Register) ;
1453	}
1454
1455	/* Additional settings for FIFO_CTL register only if HDMI is not configured in Master Mode */
1456	Register = BREG_Read32( hHDMI->hRegister, BCHP_HDMI_FIFO_CTL) ;
1457	masterMode = (bool) BCHP_GET_FIELD_DATA(Register, HDMI_FIFO_CTL, MASTER_OR_SLAVE_N);
1458
1459	/* In master mode, No RECENTER and USE_FULL needs to be set to 0 */
1460	if (masterMode)
1461	{
1462	Register &= ~ BCHP_MASK(HDMI_FIFO_CTL, USE_FULL);
1463	Register \|= BCHP_FIELD_DATA(HDMI_FIFO_CTL, USE_FULL, 0);
1464	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_FIFO_CTL, Register);
1465	}
1466	else
1467	{
1468	Register &=
1469	~( BCHP_MASK(HDMI_FIFO_CTL, RECENTER)
1470	\| BCHP_MASK(HDMI_FIFO_CTL, CAPTURE_POINTERS));
1471
1472	/* Set to 1 */
1473	Register \|=
1474	BCHP_FIELD_DATA(HDMI_FIFO_CTL, RECENTER, 1)
1475	\| BCHP_FIELD_DATA(HDMI_FIFO_CTL, CAPTURE_POINTERS, 1);
1476	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_FIFO_CTL, Register);
1477
1478	/* Now set to 0 */
1479	Register \|=
1480	BCHP_FIELD_DATA(HDMI_FIFO_CTL, RECENTER, 0)
1481	\| BCHP_FIELD_DATA(HDMI_FIFO_CTL, CAPTURE_POINTERS, 0);
1482	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_FIFO_CTL, Register);
1483
1484	/* Set additional fields */
1485	Register &= ~( BCHP_MASK(HDMI_FIFO_CTL, USE_FULL)
1486	\| BCHP_MASK(HDMI_FIFO_CTL, USE_EMPTY));
1487
1488	Register \|= BCHP_FIELD_DATA(HDMI_FIFO_CTL, USE_FULL, 1)
1489	\| BCHP_FIELD_DATA(HDMI_FIFO_CTL, USE_EMPTY, 1);
1490	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_FIFO_CTL, Register);
1491	}
1492
1493	#if BDBG_DEBUG_BUILD
1494	if (hHDMI->DeviceSettings.CalculateCts)
1495	{
1496	BDBG_MSG(("%4d * *",
1497	pAudioParameters[eInputPixelClock].HW_NValue)) ;
1498	}
1499	else
1500	{
1501	BDBG_MSG((" N CTS 0 - CTS 1")) ;
1502	BDBG_MSG(("%4d %6d-%6d",
1503	pAudioParameters[eInputPixelClock].NValue,
1504	pAudioParameters[eInputPixelClock].CTS_0,
1505	pAudioParameters[eInputPixelClock].CTS_1)) ;
1506	BDBG_MSG(("CTS 0 Repeat Value: %d Period: %d",
1507	pAudioParameters[eInputPixelClock].CTS_0_REPEAT, pAudioParameters[eInputPixelClock].CTS_PERIOD_0)) ;
1508	BDBG_MSG(("CTS 1 Repeat Value: %d Period: %d",
1509	pAudioParameters[eInputPixelClock].CTS_1_REPEAT, pAudioParameters[eInputPixelClock].CTS_PERIOD_1)) ;
1510	}
1511	#endif
1512
1513	done:
1514	BDBG_LEAVE(BHDM_AudioVideoRateChangeCB_isr) ;
1515	return ;
1516	}
1517
1518
1519	/******************************************************************************
1520	Summary:
1521	Configure the MAI Audio Input Bus
1522	*******************************************************************************/
1523	void BHDM_P_ConfigureInputAudioFmt(
1524	BHDM_Handle hHDMI, /* [in] HDMI handle */
1525	BAVC_HDMI_AudioInfoFrame *stAudioInfoFrame
1526	)
1527	{
1528	uint32_t Register ;
1529	uint8_t ChannelMask = 0x03 ; /* default to 2 channels */
1530
1531	#if BHDM_CONFIG_AUDIO_MAI_BUS_DISABLE_SUPPORT
1532	uint8_t DisableMai = hHDMI->AudioMuteState == true ? 1 : 0;
1533	#endif
1534
1535	switch (stAudioInfoFrame->SpeakerAllocation)
1536	{
1537	case BHDM_ChannelAllocation_e_xx__xx__xx__xx__xx___xx_FR__FL :
1538	ChannelMask = 0x03 ; break ;
1539
1540	case BHDM_ChannelAllocation_e_xx__xx__xx__xx__xx__LFE_FR__FL :
1541	ChannelMask = 0x07 ; break ;
1542
1543	case BHDM_ChannelAllocation_e_xx__xx__xx__xx__FC___xx_FR__FL :
1544	ChannelMask = 0x0B ; break ;
1545
1546	case BHDM_ChannelAllocation_e_xx__xx__xx__xx__FC__LFE_FR__FL :
1547	ChannelMask = 0x0F ; break ;
1548
1549	case BHDM_ChannelAllocation_e_xx__xx__xx__RC__xx___xx_FR__FL :
1550	ChannelMask = 0x13 ; break ;
1551
1552	case BHDM_ChannelAllocation_e_xx__xx__xx__RC__xx__LFE_FR__FL :
1553	ChannelMask = 0x17 ; break ;
1554
1555	case BHDM_ChannelAllocation_e_xx__xx__xx__RC__FC___xx_FR__FL :
1556	ChannelMask = 0x1B ; break ;
1557
1558	case BHDM_ChannelAllocation_e_xx__xx__xx__RC__FC__LFE_FR__FL :
1559	ChannelMask = 0x1F ; break ;
1560
1561	case BHDM_ChannelAllocation_e_xx__xx__RR__RL__xx___xx_FR__FL :
1562	ChannelMask = 0x33 ; break ;
1563
1564	case BHDM_ChannelAllocation_e_xx__xx__RR__RL__xx__LFE_FR__FL :
1565	ChannelMask = 0x37 ; break ;
1566
1567	case BHDM_ChannelAllocation_e_xx__xx__RR__RL__FC___xx_FR__FL :
1568	ChannelMask = 0x3B ; break ;
1569
1570	case BHDM_ChannelAllocation_e_xx__xx__RR__RL__FC__LFE_FR__FL :
1571	ChannelMask = 0x3F ; break ;
1572
1573	case BHDM_ChannelAllocation_e_xx__RC__RR__RL__xx___xx_FR__FL :
1574	ChannelMask = 0x73 ; break ;
1575
1576	case BHDM_ChannelAllocation_e_xx__RC__RR__RL__xx__LFE_FR__FL :
1577	ChannelMask = 0x77 ; break ;
1578
1579	case BHDM_ChannelAllocation_e_xx__RC__RR__RL__FC___xx_FR__FL :
1580	ChannelMask = 0x7B ; break ;
1581
1582	case BHDM_ChannelAllocation_e_xx__RC__RR__RL__FC__LFE_FR__FL :
1583	ChannelMask = 0x7F ; break ;
1584
1585	case BHDM_ChannelAllocation_e_RRC_RLC__RR__RL__xx__xx_FR__FL :
1586	ChannelMask = 0xF3 ; break ;
1587
1588	case BHDM_ChannelAllocation_e_RRC_RLC__RR__RL__xx_LFE_FR__FL :
1589	ChannelMask = 0xF7 ; break ;
1590
1591	case BHDM_ChannelAllocation_e_RRC_RLC__RR__RL__FC__xx_FR__FL:
1592	ChannelMask = 0xFB ; break ;
1593
1594	case BHDM_ChannelAllocation_e_RRC_RLC__RR__RL__FC_LFE_FR__FL :
1595	ChannelMask = 0xFF ; break ;
1596
1597	default :
1598	BDBG_WRN(("UnSupported Speaker/Channel Mapping; %#X",
1599	stAudioInfoFrame->SpeakerAllocation)) ;
1600
1601	}
1602	/CP 10 Configure the MAI Bus */
1603	/**** Set Channel Mask */
1604	/* clear MAI_BIT_REVERSE bit - reset value */
1605	/* set MAI_CHANNEL_MASK = 3 - reset value */
1606
1607	Register = BCHP_FIELD_DATA(HDMI_MAI_CONFIG, MAI_BIT_REVERSE, 0)
1608	#if BHDM_CONFIG_AUDIO_MAI_BUS_DISABLE_SUPPORT
1609	\| BCHP_FIELD_DATA(HDMI_MAI_CONFIG, DISABLE_MAI_AUDIO, DisableMai)
1610	#endif
1611	\| BCHP_FIELD_DATA(HDMI_MAI_CONFIG, MAI_CHANNEL_MASK, 0xFF) ;
1612	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_MAI_CONFIG, Register) ;
1613
1614
1615	/**** Set Channel Map */
1616	/* set CHANNEL_0_MAP = 0 - reset value */
1617	/* set CHANNEL_1_MAP = 1 - reset value */
1618	/* set CHANNEL_2_MAP = 2 - reset value */
1619	/* set CHANNEL_3_MAP = 3 - reset value */
1620	/* set CHANNEL_4_MAP = 4 - reset value */
1621	/* set CHANNEL_5_MAP = 5 - reset value */
1622	/* set CHANNEL_6_MAP = 6 - reset value */
1623	/* set CHANNEL_7_MAP = 7 - reset value */
1624	Register =
1625	BCHP_FIELD_DATA(HDMI_MAI_CHANNEL_MAP, CHANNEL_0_MAP, 0)
1626	\| BCHP_FIELD_DATA(HDMI_MAI_CHANNEL_MAP, CHANNEL_1_MAP, 1)
1627	#if BHDM_CONFIG_AUDIO_MAI_BUS_CHANNEL_MAP_1TO1
1628	\| BCHP_FIELD_DATA(HDMI_MAI_CHANNEL_MAP, CHANNEL_2_MAP, 2)
1629	\| BCHP_FIELD_DATA(HDMI_MAI_CHANNEL_MAP, CHANNEL_3_MAP, 3)
1630	\| BCHP_FIELD_DATA(HDMI_MAI_CHANNEL_MAP, CHANNEL_4_MAP, 4)
1631	\| BCHP_FIELD_DATA(HDMI_MAI_CHANNEL_MAP, CHANNEL_5_MAP, 5)
1632	#else
1633	\| BCHP_FIELD_DATA(HDMI_MAI_CHANNEL_MAP, CHANNEL_2_MAP, 4)
1634	\| BCHP_FIELD_DATA(HDMI_MAI_CHANNEL_MAP, CHANNEL_3_MAP, 5)
1635	\| BCHP_FIELD_DATA(HDMI_MAI_CHANNEL_MAP, CHANNEL_4_MAP, 3)
1636	\| BCHP_FIELD_DATA(HDMI_MAI_CHANNEL_MAP, CHANNEL_5_MAP, 2)
1637	#endif
1638	\| BCHP_FIELD_DATA(HDMI_MAI_CHANNEL_MAP, CHANNEL_6_MAP, 6)
1639	\| BCHP_FIELD_DATA(HDMI_MAI_CHANNEL_MAP, CHANNEL_7_MAP, 7)
1640	\| BCHP_FIELD_DATA(HDMI_MAI_CHANNEL_MAP, reserved0, 0) ;
1641	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_MAI_CHANNEL_MAP, Register) ;
1642
1643
1644	/CP 11 Configure Audio */
1645
1646	/* clear ZERO_DATA_ON_SAMPLE_FLAT - reset value */
1647	/* clear AUDIO_SAMPLE_FLAT = 4'd0 - reset value */
1648	/* clear ZERO_DATA_ON_INACTIVE_CHANNELS - reset value */
1649	/* clear SAMPLE_PRESENT = 4'd0 - reset value */
1650	/* clear FORCE_SAMPLE_PRESENT - reset value */
1651	/* clear FORCE_B_FRAME - reset value */
1652	/* clear B_FRAME = 4'd0 - reset value */
1653	/* clear B_FRAME_IDENTIFIER = 4'd1 */
1654	/* clear AUDIO_LAYOUT - reset value */
1655	/* clear FORCE_AUDIO_LAYOUT - reset value */
1656	/* clear AUDIO_CEA_MASK = 8'd0 - reset value */
1657	Register =
1658	BCHP_FIELD_DATA(HDMI_AUDIO_PACKET_CONFIG, ZERO_DATA_ON_SAMPLE_FLAT, 1)
1659	\| BCHP_FIELD_DATA(HDMI_AUDIO_PACKET_CONFIG, AUDIO_SAMPLE_FLAT, 0)
1660	\| BCHP_FIELD_DATA(HDMI_AUDIO_PACKET_CONFIG, ZERO_DATA_ON_INACTIVE_CHANNELS, 1)
1661	\| BCHP_FIELD_DATA(HDMI_AUDIO_PACKET_CONFIG, SAMPLE_PRESENT, 0)
1662	\| BCHP_FIELD_DATA(HDMI_AUDIO_PACKET_CONFIG, FORCE_SAMPLE_PRESENT, 0)
1663	\| BCHP_FIELD_DATA(HDMI_AUDIO_PACKET_CONFIG, FORCE_B_FRAME, 0)
1664	\| BCHP_FIELD_DATA(HDMI_AUDIO_PACKET_CONFIG, B_FRAME, 0)
1665	\| BCHP_FIELD_DATA(HDMI_AUDIO_PACKET_CONFIG, B_FRAME_IDENTIFIER, 1)
1666	\| BCHP_FIELD_DATA(HDMI_AUDIO_PACKET_CONFIG, AUDIO_LAYOUT, 0)
1667	\| BCHP_FIELD_DATA(HDMI_AUDIO_PACKET_CONFIG, FORCE_AUDIO_LAYOUT, 0)
1668	\| BCHP_FIELD_DATA(HDMI_AUDIO_PACKET_CONFIG, AUDIO_CEA_MASK, ChannelMask) ;
1669	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_AUDIO_PACKET_CONFIG, Register) ;
1670
1671
1672	#if BHDM_CONFIG_DEBUG_AUDIO_INFOFRAME
1673	BDBG_MSG(("Channel Mask: %#x", ChannelMask)) ;
1674	#endif
1675	}
1676
1677
1678	/******************************************************************************
1679	Summary:
1680	Set the color mode setting and update the General Control Packet to reflect the current color mode settings
1681	*******************************************************************************/
1682	BERR_Code BHDM_SetColorDepth(
1683	BHDM_Handle hHDMI, /* [in] HDMI handle */
1684	BHDM_ColorDepth_Settings *stColorDepthSettings
1685	)
1686	{
1687	BERR_Code rc = BERR_SUCCESS;
1688	uint32_t Register;
1689	uint8_t GcpSubPacketByte1 ;
1690	BAVC_HDMI_GCP_ColorDepth eColorDepth ;
1691
1692	BDBG_ENTER(BHDM_SetColorDepth);
1693
1694	/* Check bits per pixel settings */
1695	switch (stColorDepthSettings->eBitsPerPixel)
1696	{
1697	case BAVC_HDMI_BitsPerPixel_e24bit:
1698	/* regular 24bpp mode; no deep color */
1699
1700	eColorDepth = BAVC_HDMI_GCP_ColorDepth_e24bpp ;
1701	GcpSubPacketByte1 = 0 ;
1702	break;
1703
1704
1705	case BAVC_HDMI_BitsPerPixel_e30bit:
1706	if (!hHDMI->AttachedEDID.RxVSDB.DeepColor_30bit)
1707	{
1708	BDBG_WRN(("Attached sink does not support 10-bit deep color mode"));
1709	rc = BERR_NOT_SUPPORTED;
1710	goto done;
1711	}
1712
1713	eColorDepth = BAVC_HDMI_GCP_ColorDepth_e30bpp ;
1714	GcpSubPacketByte1 = BAVC_HDMI_GCP_ColorDepth_e30bpp ;
1715	break;
1716
1717
1718	case BAVC_HDMI_BitsPerPixel_e36bit:
1719	if (!hHDMI->AttachedEDID.RxVSDB.DeepColor_36bit)
1720	{
1721	BDBG_WRN(("Attached receiver does not support 12-bit deep color"));
1722	rc = BERR_NOT_SUPPORTED;
1723	goto done;
1724	}
1725
1726	eColorDepth = BAVC_HDMI_GCP_ColorDepth_e36bpp ;
1727	GcpSubPacketByte1 = BAVC_HDMI_GCP_ColorDepth_e36bpp ;
1728	break;
1729
1730
1731	case BAVC_HDMI_BitsPerPixel_e48bit:
1732	BDBG_WRN(("16 bit deep color is not supported"));
1733	rc = BERR_NOT_SUPPORTED;
1734	goto done ;
1735
1736	default: /* use 24bpp if unknown color depth */
1737	BDBG_ERR(("Invalid Color Depth %d specified; default to 24bpp",
1738	stColorDepthSettings->eBitsPerPixel));
1739
1740	eColorDepth = BAVC_HDMI_GCP_ColorDepth_e24bpp ;
1741	GcpSubPacketByte1 = 0 ;
1742
1743	break;
1744	}
1745
1746	/* Configure color depth and GCP packets related register so that the hardware
1747	will update the packing phase accordingly */
1748	Register = BREG_Read32(hHDMI->hRegister, BCHP_HDMI_DEEP_COLOR_CONFIG_1);
1749	Register &= ~BCHP_MASK(HDMI_DEEP_COLOR_CONFIG_1, COLOR_DEPTH) ;
1750	Register &= ~BCHP_MASK(HDMI_DEEP_COLOR_CONFIG_1, DEFAULT_PHASE) ;
1751	Register \|= BCHP_FIELD_DATA(HDMI_DEEP_COLOR_CONFIG_1, COLOR_DEPTH, eColorDepth) ;
1752	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_DEEP_COLOR_CONFIG_1, Register);
1753
1754	Register = BREG_Read32(hHDMI->hRegister, BCHP_HDMI_GCP_WORD_1);
1755	Register &= ~BCHP_MASK(HDMI_GCP_WORD_1, GCP_SUBPACKET_BYTE_1) ;
1756	Register \|= BCHP_FIELD_DATA(HDMI_GCP_WORD_1, GCP_SUBPACKET_BYTE_1, GcpSubPacketByte1) ;
1757	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_GCP_WORD_1, Register);
1758
1759	Register = BREG_Read32(hHDMI->hRegister, BCHP_HDMI_GCP_CONFIG);
1760	Register &= ~BCHP_MASK(HDMI_GCP_CONFIG, GCP_ENABLE) ;
1761	Register \|= BCHP_FIELD_DATA(HDMI_GCP_CONFIG, GCP_ENABLE, 1) ;
1762	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_GCP_CONFIG, Register);
1763
1764
1765	done:
1766	BKNI_Memcpy(&hHDMI->DeviceSettings.stColorDepth, stColorDepthSettings, sizeof(BHDM_ColorDepth_Settings));
1767	BDBG_LEAVE(BHDM_SetColorDepth);
1768	return rc;
1769
1770	}
1771
1772
1773	/******************************************************************************
1774	Summary:
1775	Get the current color depth setting
1776	*******************************************************************************/
1777	BERR_Code BHDM_GetColorDepth(
1778	BHDM_Handle hHDMI, /* [in] HDMI handle */
1779	BHDM_ColorDepth_Settings stColorDepthSettings / [out] color depth setting returns */
1780	)
1781	{
1782	BDBG_ENTER(BHDM_GetColorDepth);
1783	BDBG_ASSERT(hHDMI);
1784
1785	if (stColorDepthSettings)
1786	BKNI_Memcpy(stColorDepthSettings, &hHDMI->DeviceSettings.stColorDepth, sizeof(BHDM_ColorDepth_Settings));
1787
1788	BDBG_LEAVE(BHDM_GetColorDepth);
1789	return BERR_SUCCESS;
1790	}
1791
1792
1793	/******************************************************************************
1794	Summary:
1795	Set pixel data override
1796	*******************************************************************************/
1797	BERR_Code BHDM_SetPixelDataOverride(
1798	BHDM_Handle hHDMI, /* [in] HDMI handle */
1799	uint8_t red,
1800	uint8_t green,
1801	uint8_t blue
1802	)
1803	{
1804	BERR_Code rc = BERR_SUCCESS;
1805	uint32_t Register;
1806
1807	uint16_t uiRed12bits = red;
1808	uint16_t uiGreen12bits = green;
1809	uint16_t uiBlue12bits = blue;
1810
1811	BDBG_ENTER(BHDM_SetPixelDataOverride) ;
1812
1813
1814	#if BHDM_CONFIG_PIXEL_OVERRIDE_UPDATE
1815	/* Red */
1816	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_1A) ;
1817	Register &= ~ BCHP_MASK(DVP_HT_TVG_BAR_CFG_1A, CH2);
1818	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_1A, Register);
1819
1820	Register \|= BCHP_FIELD_DATA(DVP_HT_TVG_BAR_CFG_1A, CH2, (uiRed12bits << 4));
1821	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_1A, Register);
1822
1823
1824	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_2A) ;
1825	Register &= ~ BCHP_MASK(DVP_HT_TVG_BAR_CFG_2A, CH2);
1826	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_2A, Register);
1827
1828	Register \|= BCHP_FIELD_DATA(DVP_HT_TVG_BAR_CFG_2A, CH2, (uiRed12bits << 4));
1829	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_2A, Register);
1830
1831
1832	/* Green */
1833	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_1A) ;
1834	Register &= ~ BCHP_MASK(DVP_HT_TVG_BAR_CFG_1A, CH1);
1835	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_1A, Register);
1836
1837	Register \|= BCHP_FIELD_DATA(DVP_HT_TVG_BAR_CFG_1A, CH1, (uiGreen12bits << 4));
1838	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_1A, Register);
1839
1840
1841	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_2A) ;
1842	Register &= ~ BCHP_MASK(DVP_HT_TVG_BAR_CFG_2A, CH1);
1843	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_2A, Register);
1844
1845	Register \|= BCHP_FIELD_DATA(DVP_HT_TVG_BAR_CFG_2A, CH1, (uiGreen12bits << 4));
1846	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_2A, Register);
1847
1848
1849	/* Blue */
1850	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_1B) ;
1851	Register &= ~ BCHP_MASK(DVP_HT_TVG_BAR_CFG_1B, CH0);
1852	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_1B, Register);
1853
1854	Register \|= BCHP_FIELD_DATA(DVP_HT_TVG_BAR_CFG_1B, CH0, (uiBlue12bits << 4));
1855	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_1B, Register);
1856
1857
1858	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_2B) ;
1859	Register &= ~ BCHP_MASK(DVP_HT_TVG_BAR_CFG_2B, CH0);
1860	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_2B, Register);
1861
1862	Register \|= BCHP_FIELD_DATA(DVP_HT_TVG_BAR_CFG_2B, CH0, (uiBlue12bits << 4));
1863	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_BAR_CFG_2B, Register);
1864
1865
1866	/* Setup mode & Enable */
1867	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_TVG_CFG_0) ;
1868	Register &= ~( BCHP_MASK(DVP_HT_TVG_CFG_0, PATTERN_SELECT)
1869	\| BCHP_MASK(DVP_HT_TVG_CFG_0, TEST_MODE));
1870	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_CFG_0, Register) ;
1871
1872	Register \|= BCHP_FIELD_DATA(DVP_HT_TVG_CFG_0, PATTERN_SELECT, 4)
1873	\| BCHP_FIELD_DATA(DVP_HT_TVG_CFG_0, TEST_MODE, 3);
1874	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_CFG_0, Register);
1875
1876	#else
1877	/* Red */
1878	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_10) ;
1879	Register &=
1880	~( BCHP_MASK(DVP_HT_HDMI_TX_0_TDG_CFG_10, DVO_0_FLAT_FIELD_1_RED)
1881	\| BCHP_MASK(DVP_HT_HDMI_TX_0_TDG_CFG_10, DVO_0_FLAT_FIELD_2_RED) );
1882	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_10, Register);
1883
1884	Register \|= BCHP_FIELD_DATA(DVP_HT_HDMI_TX_0_TDG_CFG_10, DVO_0_FLAT_FIELD_1_RED, (uiRed12bits << 4))
1885	\| BCHP_FIELD_DATA(DVP_HT_HDMI_TX_0_TDG_CFG_10, DVO_0_FLAT_FIELD_2_RED, (uiRed12bits << 4)) ;
1886	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_10, Register);
1887
1888	/* Green */
1889	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_11) ;
1890	Register &=
1891	~( BCHP_MASK(DVP_HT_HDMI_TX_0_TDG_CFG_11, DVO_0_FLAT_FIELD_1_GREEN)
1892	\| BCHP_MASK(DVP_HT_HDMI_TX_0_TDG_CFG_11, DVO_0_FLAT_FIELD_2_GREEN) );
1893	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_11, Register);
1894
1895	Register \|= BCHP_FIELD_DATA(DVP_HT_HDMI_TX_0_TDG_CFG_11, DVO_0_FLAT_FIELD_1_GREEN, (uiGreen12bits << 4))
1896	\| BCHP_FIELD_DATA(DVP_HT_HDMI_TX_0_TDG_CFG_11, DVO_0_FLAT_FIELD_2_GREEN, (uiGreen12bits << 4)) ;
1897	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_11, Register);
1898
1899	/* Blue */
1900	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_12) ;
1901	Register &=
1902	~( BCHP_MASK(DVP_HT_HDMI_TX_0_TDG_CFG_12, DVO_0_FLAT_FIELD_1_BLUE)
1903	\| BCHP_MASK(DVP_HT_HDMI_TX_0_TDG_CFG_12, DVO_0_FLAT_FIELD_2_BLUE) );
1904	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_12, Register);
1905
1906	Register \|= BCHP_FIELD_DATA(DVP_HT_HDMI_TX_0_TDG_CFG_12, DVO_0_FLAT_FIELD_1_BLUE, (uiBlue12bits << 4))
1907	\| BCHP_FIELD_DATA(DVP_HT_HDMI_TX_0_TDG_CFG_12, DVO_0_FLAT_FIELD_2_BLUE, (uiBlue12bits << 4)) ;
1908	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_12, Register);
1909
1910
1911	/* Setup mode */
1912	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_13) ;
1913	Register &= ~BCHP_MASK(DVP_HT_HDMI_TX_0_TDG_CFG_13, DVO_0_GEN_TEST_MODE) ;
1914	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_13, Register) ;
1915
1916	Register \|= BCHP_FIELD_DATA(DVP_HT_HDMI_TX_0_TDG_CFG_13, DVO_0_GEN_TEST_MODE, 4);
1917	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_13, Register);
1918
1919
1920	/* Enable */
1921	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_0) ;
1922	Register &= ~BCHP_MASK(DVP_HT_HDMI_TX_0_TDG_CFG_0, DVO_0_TEST_MODE) ;
1923	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_0, Register) ;
1924
1925	Register \|= BCHP_FIELD_DATA(DVP_HT_HDMI_TX_0_TDG_CFG_0, DVO_0_TEST_MODE, 3);
1926	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_0, Register);
1927	#endif
1928
1929	BDBG_LEAVE(BHDM_SetPixelDataOverride) ;
1930	return rc;
1931	}
1932
1933
1934	/******************************************************************************
1935	Summary:
1936	Clear pixel data override
1937	*******************************************************************************/
1938	BERR_Code BHDM_ClearPixelDataOverride(
1939	BHDM_Handle hHDMI /* [in] HDMI handle */
1940	)
1941	{
1942	BERR_Code rc = BERR_SUCCESS;
1943	uint32_t Register;
1944
1945	BDBG_ENTER(BHDM_ClearPixelDataOverride) ;
1946
1947
1948	#if BHDM_CONFIG_PIXEL_OVERRIDE_UPDATE
1949
1950	/* Disable */
1951	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_TVG_CFG_0) ;
1952	Register &= ~ BCHP_MASK(DVP_HT_TVG_CFG_0, TEST_MODE);
1953	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_CFG_0, Register) ;
1954
1955	Register \|= BCHP_FIELD_DATA(DVP_HT_TVG_CFG_0, TEST_MODE, 0);
1956	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_TVG_CFG_0, Register);
1957
1958	#else
1959	/* Disable */
1960	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_0) ;
1961	Register &= ~BCHP_MASK(DVP_HT_HDMI_TX_0_TDG_CFG_0, DVO_0_TEST_MODE) ;
1962	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_0, Register) ;
1963
1964	Register \|= BCHP_FIELD_DATA(DVP_HT_HDMI_TX_0_TDG_CFG_0, DVO_0_TEST_MODE, 0);
1965	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_HDMI_TX_0_TDG_CFG_0, Register);
1966	#endif
1967
1968	BDBG_LEAVE(BHDM_ClearPixelDataOverride) ;
1969	return rc;
1970	}
1971
1972
1973	/******************************************************************************
1974	Summary:
1975	Wait for stable video in HDMI core a specific amount of time
1976	*******************************************************************************/
1977	BERR_Code BHDM_WaitForStableVideo(
1978	BHDM_Handle hHDMI, /* [in] HDMI handle */
1979	uint32_t stablePeriod, /* [in] Period of time video should be stable */
1980	uint32_t maxWait /* [in] Max amount of time to wait */
1981	)
1982	{
1983	BERR_Code rc = BERR_TIMEOUT;
1984	uint32_t Register;
1985
1986	uint32_t waitThusFar = 0;
1987	uint32_t stableTime = 0;
1988	uint32_t waitIncr = 10;
1989	uint8_t bHPInterrupt = false;
1990	uint32_t driftFifoErrors = 0;
1991	uint32_t prevLineCount1 = 0;
1992	uint32_t prevLineCount2 = 0;
1993	uint32_t currLineCount;
1994	bool masterMode;
1995
1996	BDBG_ENTER(BHDM_WaitForStableVideo);
1997	BHDM_ClearHotPlugInterrupt(hHDMI);
1998
1999	BHDM_GetHdmiDataTransferMode(hHDMI, &masterMode);
2000
2001	while (waitThusFar < maxWait)
2002	{
2003	uint8_t notStable = false;
2004
2005	/*
2006	* First, ensure video is really flowing in from the VEC
2007	*/
2008	Register = BREG_Read32(hHDMI->hRegister, BCHP_HDMI_FORMAT_DET_7) ;
2009	currLineCount = BCHP_GET_FIELD_DATA(Register, HDMI_FORMAT_DET_7, UUT_CURRENT_LINE_COUNT) ;
2010	if (currLineCount == prevLineCount1 && currLineCount == prevLineCount2)
2011	{
2012	notStable = true;
2013	}
2014	else
2015	{
2016	prevLineCount2 = prevLineCount1;
2017	prevLineCount1 = currLineCount;
2018
2019	Register = BREG_Read32(hHDMI->hRegister, BCHP_HDMI_FORMAT_DET_UPDATE_STATUS) ;
2020
2021	if (Register & (BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_HAP)
2022	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_VBLANK2)
2023	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_VBLANK1)
2024	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_HSYNC_HIGH)
2025	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_HSYNC_LOW)
2026	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_HFP)
2027	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_HSP)
2028	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_HBP)
2029	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_VAL1)
2030	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_VFP_1)
2031	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_VBP_1)
2032	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_VSPO_1)
2033	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_VAL2)
2034	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_VFP_2)
2035	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_VBP_2)
2036	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_STATUS, UPDATED_VSPO_2)))
2037	{
2038	Register = BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_HAP)
2039	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_VBLANK2)
2040	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_VBLANK1)
2041	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_HSYNC_HIGH)
2042	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_HSYNC_LOW)
2043	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_HFP)
2044	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_HSP)
2045	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_HBP)
2046	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_VAL1)
2047	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_VFP_1)
2048	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_VBP_1)
2049	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_VSPO_1)
2050	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_VAL2)
2051	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_VFP_2)
2052	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_VBP_2)
2053	\| BCHP_MASK(HDMI_FORMAT_DET_UPDATE_CLEAR, CLEAR_UPDATED_VSPO_2) ;
2054
2055	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_FORMAT_DET_UPDATE_CLEAR, Register) ;
2056	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_FORMAT_DET_UPDATE_CLEAR, 0) ;
2057	notStable = true;
2058	}
2059
2060	else if (masterMode == false)
2061	{
2062	/*
2063	* Capture (pointers) status before we read it.
2064	*/
2065	Register = BREG_Read32( hHDMI->hRegister, BCHP_HDMI_FIFO_CTL) ;
2066
2067	Register &= ~BCHP_MASK(HDMI_FIFO_CTL, CAPTURE_POINTERS) ;
2068	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_FIFO_CTL, Register) ;
2069
2070	Register \|= BCHP_FIELD_DATA(HDMI_FIFO_CTL, CAPTURE_POINTERS, 1) ;
2071	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_FIFO_CTL, Register) ;
2072
2073	Register = BREG_Read32(hHDMI->hRegister, BCHP_HDMI_READ_POINTERS) ;
2074	if (Register & (BCHP_MASK(HDMI_READ_POINTERS, DRIFT_UNDERFLOW)
2075	\| BCHP_MASK(HDMI_READ_POINTERS, DRIFT_OVERFLOW)))
2076	{
2077	notStable = true;
2078
2079	/*
2080	* Re-center the Drift FIFO if we get excessive overflow or underflow
2081	* errors. There is a bug with the 76xx where the auto re-center
2082	* logic (use_full, use_empty) does not work as expected in terms of
2083	* clearing these errors.
2084	*/
2085	if (++driftFifoErrors % 10 == 0)
2086	{
2087	Register = BREG_Read32( hHDMI->hRegister, BCHP_HDMI_FIFO_CTL) ;
2088
2089	Register &= ~BCHP_MASK(HDMI_FIFO_CTL, RECENTER) ;
2090	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_FIFO_CTL, Register) ;
2091
2092	Register \|= BCHP_FIELD_DATA(HDMI_FIFO_CTL, RECENTER, 1) ;
2093	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_FIFO_CTL, Register) ;
2094	}
2095	}
2096	}
2097	}
2098
2099	BKNI_Sleep(waitIncr);
2100	waitThusFar += waitIncr;
2101
2102	if (notStable == false)
2103	{
2104	stableTime += waitIncr;
2105	if (stableTime >= stablePeriod)
2106	{
2107	rc = BERR_SUCCESS;
2108	goto done;
2109	}
2110	}
2111	else
2112	{
2113	stableTime = 0;
2114	}
2115
2116	BHDM_CheckHotPlugInterrupt(hHDMI, &bHPInterrupt);
2117	if (bHPInterrupt == true)
2118	goto done;
2119	}
2120
2121	done:
2122	BDBG_LEAVE(BHDM_WaitForStableVideo);
2123	return rc;
2124
2125	}
2126
2127
2128	/**********************************
2129	** PRIVATE FUNCTIONS
2130	***********************************/
2131	void BHDM_P_ResetHdmiCore (BHDM_Handle hHDMI)
2132	{
2133
2134	/* Reset the HDMI core */
2135
2136	BREG_Write32(hHDMI->hRegister, BCHP_SUN_TOP_CTRL_SW_INIT_0_SET,
2137	BCHP_FIELD_DATA(SUN_TOP_CTRL_SW_INIT_0_SET, dvp_ht_sw_init, 1));
2138
2139	BREG_Write32(hHDMI->hRegister, BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR,
2140	BCHP_FIELD_DATA(SUN_TOP_CTRL_SW_INIT_0_CLEAR, dvp_ht_sw_init, 1));
2141
2142	return;
2143	}
2144
2145
2146	void BHDM_P_PowerOnPhy (BHDM_Handle hHDMI)
2147	{
2148	uint32_t Register;
2149	bool masterMode;
2150
2151	BHDM_GetHdmiDataTransferMode(hHDMI, &masterMode);
2152
2153	#if BHDM_CONFIG_CLOCK_STOP_SUPPORT
2154	Register = BREG_Read32(hHDMI->hRegister, BCHP_DVP_HT_CLOCK_STOP);
2155	Register &= ~ BCHP_MASK(DVP_HT_CLOCK_STOP, PIXEL);
2156	BREG_Write32(hHDMI->hRegister, BCHP_DVP_HT_CLOCK_STOP, Register) ;
2157	#endif
2158
2159
2160	/* Assert the fields to prevent DRIFT FIFO UNDERFLOW when trying to
2161	authenticate with DVI receivers */
2162	Register = BREG_Read32(hHDMI->hRegister, BCHP_HDMI_FIFO_CTL);
2163	Register &= ~( BCHP_MASK(HDMI_FIFO_CTL, USE_EMPTY)
2164	\| BCHP_MASK(HDMI_FIFO_CTL, USE_FULL));
2165
2166	Register \|= BCHP_FIELD_DATA(HDMI_FIFO_CTL, USE_EMPTY, 1)
2167	\| BCHP_FIELD_DATA(HDMI_FIFO_CTL, USE_FULL, masterMode?0:1);
2168	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_FIFO_CTL, Register) ;
2169
2170	/* PR 28685: Enable Random bit block power down. */
2171	/* Power PLL, etc. */
2172	Register = BREG_Read32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_POWERDOWN_CTL);
2173	Register &= ~( BCHP_MASK(HDMI_TX_PHY_POWERDOWN_CTL, RNDGEN_PWRDN)
2174	\| BCHP_MASK(HDMI_TX_PHY_POWERDOWN_CTL, PLL_PWRDN)
2175	\| BCHP_MASK(HDMI_TX_PHY_POWERDOWN_CTL, BIAS_PWRDN)
2176	\| BCHP_MASK(HDMI_TX_PHY_POWERDOWN_CTL, PHY_PWRDN)) ;
2177	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_POWERDOWN_CTL, Register) ;
2178
2179
2180	/* Bring PLL PHY out of reset */
2181	Register = BREG_Read32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_RESET_CTL);
2182	Register &= ~( BCHP_MASK(HDMI_TX_PHY_RESET_CTL, PLL_RESETB)
2183	\| BCHP_MASK(HDMI_TX_PHY_RESET_CTL, PLLDIV_RSTB)) ;
2184
2185	Register \|= BCHP_FIELD_DATA(HDMI_TX_PHY_RESET_CTL, PLL_RESETB, 1)
2186	\| BCHP_FIELD_DATA(HDMI_TX_PHY_RESET_CTL, PLLDIV_RSTB, 1);
2187	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_RESET_CTL, Register) ;
2188
2189
2190	/* Program HDMI_TX_PHY.CHANNEL_SWAP if required */
2191	#if BHDM_CONFIG_SWAP_DEFAULT_PHY_CHANNELS
2192	Register = BREG_Read32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_CHANNEL_SWAP);
2193	Register &= ~( BCHP_MASK(HDMI_TX_PHY_CHANNEL_SWAP, TXCK_OUT_INV)
2194	\| BCHP_MASK(HDMI_TX_PHY_CHANNEL_SWAP, TXCK_OUT_SEL)
2195	\| BCHP_MASK(HDMI_TX_PHY_CHANNEL_SWAP, TX2_OUT_INV)
2196	\| BCHP_MASK(HDMI_TX_PHY_CHANNEL_SWAP, TX2_OUT_SEL)
2197	\| BCHP_MASK(HDMI_TX_PHY_CHANNEL_SWAP, TX1_OUT_INV)
2198	\| BCHP_MASK(HDMI_TX_PHY_CHANNEL_SWAP, TX1_OUT_SEL)
2199	\| BCHP_MASK(HDMI_TX_PHY_CHANNEL_SWAP, TX0_OUT_INV)
2200	\| BCHP_MASK(HDMI_TX_PHY_CHANNEL_SWAP, TX0_OUT_SEL));
2201
2202	Register \|= BCHP_FIELD_DATA(HDMI_TX_PHY_CHANNEL_SWAP, TXCK_OUT_INV,
2203	BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_INV)
2204	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CHANNEL_SWAP, TXCK_OUT_SEL,
2205	BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TXCK_OUT_SEL)
2206	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CHANNEL_SWAP, TX2_OUT_INV,
2207	BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_INV)
2208	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CHANNEL_SWAP, TX2_OUT_SEL,
2209	BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX2_OUT_SEL)
2210	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CHANNEL_SWAP, TX1_OUT_INV,
2211	BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_INV)
2212	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CHANNEL_SWAP, TX1_OUT_SEL,
2213	BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX1_OUT_SEL)
2214	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CHANNEL_SWAP, TX0_OUT_INV,
2215	BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_INV)
2216	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CHANNEL_SWAP, TX0_OUT_SEL,
2217	BHDM_CONFIG_HDMI_TX_PHY_CHANNEL_SWAP_TX0_OUT_SEL);
2218	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_CHANNEL_SWAP, Register) ;
2219	#endif
2220
2221	return;
2222	}
2223
2224
2225	void BHDM_P_SetPreEmphasisMode (BHDM_Handle hHDMI, uint8_t uValue, uint8_t uDriverAmp)
2226	{
2227	uint32_t Register;
2228
2229	Register = BREG_Read32( hHDMI->hRegister, BCHP_HDMI_TX_PHY_CTL_0) ;
2230	Register &= ~(BCHP_MASK(HDMI_TX_PHY_CTL_0, PREEMP_2)
2231	\| BCHP_MASK(HDMI_TX_PHY_CTL_0, PREEMP_1)
2232	\| BCHP_MASK(HDMI_TX_PHY_CTL_0, PREEMP_0));
2233
2234	Register \|= BCHP_FIELD_DATA(HDMI_TX_PHY_CTL_0, PREEMP_2, uValue)
2235	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CTL_0, PREEMP_1, uValue)
2236	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CTL_0, PREEMP_0, uValue) ;
2237	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_CTL_0, Register) ;
2238
2239
2240	Register = BREG_Read32( hHDMI->hRegister, BCHP_HDMI_TX_PHY_CTL_1) ;
2241	Register &= ~(BCHP_MASK(HDMI_TX_PHY_CTL_1, PREEMP_CK));
2242	Register \|= BCHP_FIELD_DATA(HDMI_TX_PHY_CTL_1, PREEMP_CK, uValue);
2243	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_CTL_1, Register) ;
2244
2245	BSTD_UNUSED(uDriverAmp);
2246	return;
2247	}
2248
2249
2250	BERR_Code BHDM_P_GetPreEmphasisConfiguration (
2251	BHDM_Handle hHDMI,
2252	BHDM_PreEmphasis_Configuration *stPreEmphasisConfig
2253	)
2254	{
2255	BERR_Code rc = BERR_SUCCESS;
2256	uint32_t Register;
2257
2258	Register = BREG_Read32( hHDMI->hRegister, BCHP_HDMI_TX_PHY_CTL_0) ;
2259	stPreEmphasisConfig->uiHfEn = BCHP_GET_FIELD_DATA(Register, HDMI_TX_PHY_CTL_0, HF_EN);
2260	stPreEmphasisConfig->uiPreEmphasis_Ch2 = BCHP_GET_FIELD_DATA(Register,HDMI_TX_PHY_CTL_0,PREEMP_2);
2261	stPreEmphasisConfig->uiPreEmphasis_Ch1 = BCHP_GET_FIELD_DATA(Register,HDMI_TX_PHY_CTL_0,PREEMP_1);
2262	stPreEmphasisConfig->uiPreEmphasis_Ch0 = BCHP_GET_FIELD_DATA(Register,HDMI_TX_PHY_CTL_0,PREEMP_0);
2263
2264	Register = BREG_Read32( hHDMI->hRegister, BCHP_HDMI_TX_PHY_CTL_1) ;
2265	stPreEmphasisConfig->uiPreEmphasis_CK = BCHP_GET_FIELD_DATA(Register,HDMI_TX_PHY_CTL_1,PREEMP_CK);
2266	stPreEmphasisConfig->uiCurrentRatioSel = BCHP_GET_FIELD_DATA(Register, HDMI_TX_PHY_CTL_1, CURRENT_RATIO_SEL);
2267
2268	Register = BREG_Read32( hHDMI->hRegister, BCHP_HDMI_TX_PHY_CTL_2) ;
2269	stPreEmphasisConfig->uiKP = BCHP_GET_FIELD_DATA(Register, HDMI_TX_PHY_CTL_2, KP);
2270	stPreEmphasisConfig->uiKI = BCHP_GET_FIELD_DATA(Register, HDMI_TX_PHY_CTL_2, KI);
2271	stPreEmphasisConfig->uiKA = BCHP_GET_FIELD_DATA(Register, HDMI_TX_PHY_CTL_2, KA);
2272
2273	return rc;
2274	}
2275
2276
2277	BERR_Code BHDM_P_SetPreEmphasisConfiguration(
2278	BHDM_Handle hHDMI,
2279	BHDM_PreEmphasis_Configuration *stPreEmphasisConfig)
2280	{
2281	BERR_Code rc = BERR_SUCCESS;
2282	uint32_t Register;
2283
2284	/* Set Preemphasis configurations */
2285	Register = BREG_Read32( hHDMI->hRegister, BCHP_HDMI_TX_PHY_CTL_0) ;
2286	Register &= ~(
2287	BCHP_MASK(HDMI_TX_PHY_CTL_0, HF_EN)
2288	\| BCHP_MASK(HDMI_TX_PHY_CTL_0, PREEMP_2)
2289	\| BCHP_MASK(HDMI_TX_PHY_CTL_0, PREEMP_1)
2290	\| BCHP_MASK(HDMI_TX_PHY_CTL_0, PREEMP_0)) ;
2291
2292	Register \|=
2293	BCHP_FIELD_DATA(HDMI_TX_PHY_CTL_0, HF_EN, stPreEmphasisConfig->uiHfEn)
2294	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CTL_0, PREEMP_2, stPreEmphasisConfig->uiPreEmphasis_Ch2)
2295	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CTL_0, PREEMP_1, stPreEmphasisConfig->uiPreEmphasis_Ch1)
2296	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CTL_0, PREEMP_0, stPreEmphasisConfig->uiPreEmphasis_Ch0) ;
2297	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_CTL_0, Register) ;
2298
2299	Register = BREG_Read32( hHDMI->hRegister, BCHP_HDMI_TX_PHY_CTL_1) ;
2300	Register &= ~ (
2301	BCHP_MASK(HDMI_TX_PHY_CTL_1, PREEMP_CK)
2302	\| BCHP_MASK(HDMI_TX_PHY_CTL_1, CURRENT_RATIO_SEL));
2303	Register \|=
2304	BCHP_FIELD_DATA(HDMI_TX_PHY_CTL_1, PREEMP_CK, stPreEmphasisConfig->uiPreEmphasis_CK)
2305	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CTL_1, CURRENT_RATIO_SEL, stPreEmphasisConfig->uiCurrentRatioSel);
2306	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_CTL_1, Register) ;
2307
2308	Register = BREG_Read32( hHDMI->hRegister, BCHP_HDMI_TX_PHY_CTL_2) ;
2309	Register &= ~ (
2310	BCHP_MASK(HDMI_TX_PHY_CTL_2, KP)
2311	\| BCHP_MASK(HDMI_TX_PHY_CTL_2, KI)
2312	\| BCHP_MASK(HDMI_TX_PHY_CTL_2, KA));
2313	Register \|=
2314	BCHP_FIELD_DATA(HDMI_TX_PHY_CTL_2, KP, stPreEmphasisConfig->uiKP)
2315	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CTL_2, KI, stPreEmphasisConfig->uiKI)
2316	\| BCHP_FIELD_DATA(HDMI_TX_PHY_CTL_2, KA, stPreEmphasisConfig->uiKA);
2317	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_TX_PHY_CTL_2, Register) ;
2318
2319
2320	return rc;
2321	}
2322
2323
2324	void BHDM_P_ClearHotPlugInterrupt(
2325	BHDM_Handle hHDMI /* [in] HDMI handle */
2326	)
2327	{
2328	uint32_t Register ;
2329
2330	#if BHDM_CONFIG_DUAL_HPD_SUPPORT
2331	/* reset boolean status */
2332	hHDMI->hotplugInterruptFired = false;
2333	BSTD_UNUSED(Register);
2334
2335	#else
2336	Register = BREG_Read32(hHDMI->hRegister, BCHP_AON_HDMI_TX_HDMI_HOTPLUG_CONTROL) ;
2337	Register &= ~BCHP_MASK(AON_HDMI_TX_HDMI_HOTPLUG_CONTROL, CLEAR_HOTPLUG_INT_STATUS) ;
2338	Register \|= BCHP_FIELD_DATA(AON_HDMI_TX_HDMI_HOTPLUG_CONTROL, CLEAR_HOTPLUG_INT_STATUS, 1) ;
2339	BREG_Write32(hHDMI->hRegister, BCHP_AON_HDMI_TX_HDMI_HOTPLUG_CONTROL, Register) ;
2340
2341	Register &= ~BCHP_MASK(AON_HDMI_TX_HDMI_HOTPLUG_CONTROL, CLEAR_HOTPLUG_INT_STATUS) ;
2342	Register \|= BCHP_FIELD_DATA(AON_HDMI_TX_HDMI_HOTPLUG_CONTROL, CLEAR_HOTPLUG_INT_STATUS, 0) ;
2343	BREG_Write32(hHDMI->hRegister, BCHP_AON_HDMI_TX_HDMI_HOTPLUG_CONTROL, Register) ;
2344	#endif
2345
2346	return;
2347	}
2348
2349
2350	void BHDM_P_CheckHotPlugInterrupt(
2351	BHDM_Handle hHDMI, /* [in] HDMI handle */
2352	uint8_t bHotPlugInterrupt / [out] Interrupt asserted or not */
2353	)
2354	{
2355	uint32_t Register ;
2356
2357	#if BHDM_CONFIG_DUAL_HPD_SUPPORT
2358	*bHotPlugInterrupt = hHDMI->hotplugInterruptFired;
2359	BSTD_UNUSED(Register);
2360
2361	#else
2362	Register = BREG_Read32(hHDMI->hRegister, BCHP_AON_HDMI_TX_HDMI_HOTPLUG_STATUS) ;
2363
2364	if (Register & BCHP_MASK(AON_HDMI_TX_HDMI_HOTPLUG_STATUS, HOTPLUG_INT_STATUS))
2365	*bHotPlugInterrupt = true;
2366	else
2367	*bHotPlugInterrupt = false;
2368	#endif
2369
2370	return;
2371	}
2372
2373
2374	void BHDM_P_RxDeviceAttached(
2375	BHDM_Handle hHDMI, /* [in] HDMI handle */
2376	uint8_t bDeviceAttached / [out] Device Attached Status */
2377	)
2378	{
2379	uint32_t Register ;
2380
2381	BDBG_ENTER(BHDM_P_RxDeviceAttached) ;
2382
2383	Register = BREG_Read32(hHDMI->hRegister, BCHP_HDMI_HOTPLUG_STATUS) ;
2384	*bDeviceAttached =
2385	BCHP_GET_FIELD_DATA(Register, HDMI_HOTPLUG_STATUS, HOTPLUG_STATUS) ;
2386
2387	BDBG_LEAVE(BHDM_P_RxDeviceAttached) ;
2388	return ;
2389	}
2390
2391
2392	/******************************************************************************
2393	Summary:
2394	Enable/Disable FIFO interrupts for debuging
2395	*******************************************************************************/
2396	#if BHDM_CONFIG_DEBUG_FIFO
2397	BERR_Code BHDM_P_EnableFIFOInterrupts(
2398	BHDM_Handle hHDMI,
2399	bool on)
2400	{
2401	BERR_Code rc = BERR_SUCCESS ;
2402	uint32_t Register ;
2403
2404	if (on)
2405	{
2406	/* clear any pending interrupts first */
2407	Register =
2408	BCHP_FIELD_DATA(HDMI_TX_INTR2_CPU_CLEAR, DRIFT_FIFO_FULL_MINUS_INTR, 1)
2409	\| BCHP_FIELD_DATA(HDMI_TX_INTR2_CPU_CLEAR, DRIFT_FIFO_ALMOST_FULL_INTR, 1)
2410	\| BCHP_FIELD_DATA(HDMI_TX_INTR2_CPU_CLEAR, DRIFT_FIFO_EMPTY_MINUS_INTR, 1)
2411	\| BCHP_FIELD_DATA(HDMI_TX_INTR2_CPU_CLEAR, DRIFT_FIFO_ALMOST_EMPTY_INTR, 1) ;
2412	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_TX_INTR2_CPU_CLEAR, Register) ;
2413
2414
2415	/* enable the interrupts */
2416	BHDM_CHECK_RC( rc, BINT_EnableCallback( hHDMI->hCallback[MAKE_INTR_ENUM(DF_FULL_MINUS)] )) ;
2417	BHDM_CHECK_RC( rc, BINT_EnableCallback( hHDMI->hCallback[MAKE_INTR_ENUM(DF_ALMOST_FULL)])) ;
2418	BHDM_CHECK_RC( rc, BINT_EnableCallback( hHDMI->hCallback[MAKE_INTR_ENUM(DF_EMPTY_MINUS)])) ;
2419	BHDM_CHECK_RC( rc, BINT_EnableCallback( hHDMI->hCallback[MAKE_INTR_ENUM(DF_ALMOST_EMPTY)])) ;
2420
2421	/* disable any interrupt masks; so we can see the interrupts if they occur */
2422	Register =
2423	BCHP_FIELD_DATA(HDMI_TX_INTR2_CPU_MASK_CLEAR, DRIFT_FIFO_FULL_MINUS_INTR, 1)
2424	\| BCHP_FIELD_DATA(HDMI_TX_INTR2_CPU_MASK_CLEAR, DRIFT_FIFO_ALMOST_FULL_INTR, 1)
2425	\| BCHP_FIELD_DATA(HDMI_TX_INTR2_CPU_MASK_CLEAR, DRIFT_FIFO_EMPTY_MINUS_INTR, 1)
2426	\| BCHP_FIELD_DATA(HDMI_TX_INTR2_CPU_MASK_CLEAR, DRIFT_FIFO_ALMOST_EMPTY_INTR, 1) ;
2427	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_TX_INTR2_CPU_MASK_CLEAR, Register) ;
2428	}
2429	else
2430	{
2431	/* disable the interrupt callbacks */
2432	BHDM_CHECK_RC( rc, BINT_DisableCallback( hHDMI->hCallback[MAKE_INTR_ENUM(DF_FULL_MINUS)])) ;
2433	BHDM_CHECK_RC( rc, BINT_DisableCallback( hHDMI->hCallback[MAKE_INTR_ENUM(DF_ALMOST_FULL)])) ;
2434	BHDM_CHECK_RC( rc, BINT_DisableCallback( hHDMI->hCallback[MAKE_INTR_ENUM(DF_EMPTY_MINUS)])) ;
2435	BHDM_CHECK_RC( rc, BINT_DisableCallback( hHDMI->hCallback[MAKE_INTR_ENUM(DF_ALMOST_EMPTY)])) ;
2436
2437	/* mask the interrupts; */
2438	Register =
2439	BCHP_FIELD_DATA(HDMI_TX_INTR2_CPU_MASK_SET, DRIFT_FIFO_FULL_MINUS_INTR, 1)
2440	\| BCHP_FIELD_DATA(HDMI_TX_INTR2_CPU_MASK_SET, DRIFT_FIFO_ALMOST_FULL_INTR, 1)
2441	\| BCHP_FIELD_DATA(HDMI_TX_INTR2_CPU_MASK_SET, DRIFT_FIFO_EMPTY_MINUS_INTR, 1)
2442	\| BCHP_FIELD_DATA(HDMI_TX_INTR2_CPU_MASK_SET, DRIFT_FIFO_ALMOST_EMPTY_INTR, 1) ;
2443	BREG_Write32(hHDMI->hRegister, BCHP_HDMI_TX_INTR2_CPU_MASK_SET, Register) ;
2444	}
2445
2446	done:
2447	return rc ;
2448	}
2449	#endif
2450
2451

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source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/hdm/7552/bhdm_priv.c

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