Context Navigation

bpwr_priv.c

Last change on this file was 2, checked in by phkim, 11 years ago

1.phkim

revision copy newcon3sk r27

Property svn:executable set to *

File size: 52.4 KB

Line
1	/***************************************************************************
2	* Copyright (c) 2003-2011, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bpwr_priv.c $
11	* $brcm_Revision: Hydra_Software_Devel/2 $
12	* $brcm_Date: 7/29/11 10:24a $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/portinginterface/pwr/7552/bpwr_priv.c $
19	*
20	* Hydra_Software_Devel/2 7/29/11 10:24a xhuang
21	* SW7552-4: fix warning
22	*
23	* Hydra_Software_Devel/1 11/23/10 2:10p xhuang
24	* SW7552-9: Add support for 97552
25	*
26	*
27	***************************************************************************/
28	#include "bstd.h" /* standard types */
29	#include "berr.h"
30	#include "bstd_ids.h"
31	#include "bdbg.h" /* Dbglib */
32	#include "bkni.h" /* malloc */
33
34	/#include "bchp_clk.h"/
35	#include "bchp_hdmi_tx_phy.h"
36	/#include "bchp_uhfr_glbl.h" /
37	/#include "bchp_rfm_sysclk.h"/
38	#include "bchp_misc.h"
39	/#include "bchp_vcxo_ctl_misc.h"/
40	#include "bchp_aio_misc.h"
41	#include "bchp_fmisc.h"
42	#if 0
43	#include "bchp_avlink_phy.h"
44	#include "bchp_avlink_avrx.h"
45	/#include "bchp_avd_rgr_0.h"/
46	#include "bchp_avd_rgr_1.h"
47	#endif
48
49	#include "bpwr.h"
50	#include "bpwr_priv.h"
51	#include "bpwr_mem.h"
52
53	BDBG_MODULE(BPWR);
54
55	/* List of modules relevant to this chip.
56	Don't add unused ids here. */
57	#if SMS93380_SUPPORT
58	static BSTD_Module g_ModuleList[] =
59	{
60	BSTD_SCD_ID,
61	BSTD_XPT_ID,
62	BSTD_SDS_ID,
63	BSTD_VSB_ID,
64	BSTD_DMA_ID,
65	0
66	};
67	#else
68	static BSTD_Module g_ModuleList[] =
69	{
70	BSTD_HDM_ID,
71	BSTD_RFM_ID,
72	BSTD_SCD_ID,
73	BSTD_VBI_ID,
74	BSTD_VDC_ID,
75	BSTD_XPT_ID,
76	BSTD_SDS_ID,
77	BSTD_VSB_ID,
78	BSTD_DMA_ID,
79	BSTD_GRC_ID,
80	BSTD_P3D_ID,
81	BSTD_XVD_ID,
82	BSTD_RAP_ID,
83	BSTD_UHF_ID,
84	BSTD_MDM_ID,
85	BSTD_CTK_ID,
86	BSTD_TMN_ID,
87	BSTD_TNF_ID,
88	0
89	};
90	#endif
91
92	BERR_Code BPWR_P_Init(BPWR_P_Context *pPwr )
93	{
94	unsigned i;
95
96	BDBG_OBJECT_ASSERT(pPwr, BPWR_P_Context);
97
98	for (i=0;i<BPWR_MAX_MODULES && g_ModuleList[i];i++)
99	{
100	pPwr->modules[i].moduleId = g_ModuleList[i];
101	pPwr->modules[i].mode = BPWR_Mode_ePowerUndefined;
102	}
103	/* if we assert, then BPWR_MAX_MODULES must be increased. it's an internal failure, so assert. */
104	BDBG_ASSERT(i < BPWR_MAX_MODULES);
105
106	if (pPwr->hChip == NULL)
107	{
108	BERR_Code rc;
109
110	/* BPWR_Open is being called before BCHP_Open. This code must power up the minimum number of modules to allow
111	Magnum to initialize safely. This usually means ensuring that every L2 interrupt register can be accessed safely. */
112	BSTD_Module initModuleList[] = {BSTD_HDM_ID, BSTD_VDC_ID, BSTD_VBI_ID, BSTD_XVD_ID, BSTD_RFM_ID,
113	BSTD_RAP_ID, /* needed to access AIO_INTH_R5F_MASK_SET */
114	BSTD_UHF_ID, /* needed to access UHFR_1_IMSK */
115	};
116	rc = BPWR_SetModes(pPwr, initModuleList, sizeof(initModuleList)/sizeof(BSTD_Module), BPWR_Mode_ePowerUp);
117	if (rc) return BERR_TRACE(rc);
118	rc = BPWR_ApplyChanges(pPwr);
119	if (rc) return BERR_TRACE(rc);
120	}
121
122	return 0;
123	}
124
125	BERR_Code BPWR_P_Destroy(BPWR_P_Context *pPwr)
126	{
127	BSTD_UNUSED(pPwr);
128	return 0;
129	}
130
131	bool BPWR_P_IsModuleChanging(const BPWR_P_Context *pPwr, BSTD_Module moduleId)
132	{
133	unsigned i;
134	for (i=0;i<BPWR_MAX_MODULES;i++)
135	{
136	if (pPwr->modules[i].moduleId == moduleId)
137	{
138	return pPwr->modules[i].change;
139	}
140	}
141	return false;
142	}
143
144	BERR_Code BPWR_P_ValidateChanges
145	( BPWR_P_Context *pPwr )
146	{
147	BERR_Code rc = BERR_SUCCESS;
148	unsigned count;
149
150	/* verify change sets */
151	count = (BPWR_P_IsModuleChanging(pPwr, BSTD_HDM_ID)?1:0) +
152	(BPWR_P_IsModuleChanging(pPwr, BSTD_VDC_ID)?1:0) +
153	(BPWR_P_IsModuleChanging(pPwr, BSTD_VBI_ID)?1:0);
154	if (count != 0 && count != 3)
155	{
156	BDBG_ERR(("VDC, VBI and HDM modes all need to be set together (%d).", count));
157	rc = BERR_TRACE(BERR_INVALID_PARAMETER);
158	}
159
160	return rc;
161	}
162
163	BERR_Code BPWR_P_SetPowerMode ( BPWR_P_Context *pPwr)
164	{
165
166
167	BERR_Code eStatus = BERR_SUCCESS;
168	#if 0
169	uint32_t ulRegData;
170
171	BDBG_ENTER(BPWR_P_SetPowerMode);
172
173	/* handle power down or power up in the order PWR requires */
174	if (pPwr->changeMode == BPWR_Mode_ePowerDown)
175	{
176	/* Power Down HDMI */
177	if (BPWR_P_IsModuleChanging(pPwr, BSTD_HDM_ID))
178	{
179	BDBG_MSG(("Power Down: HDM"));
180
181	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL);
182	ulRegData \|= BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_0_PWRDN_MASK \|
183	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_1_PWRDN_MASK \|
184	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_2_PWRDN_MASK \|
185	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_CK_PWRDN_MASK \|
186	/* BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_PWRDN_CEC_MASK \| 4 */
187	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_PLL_PWRDN_MASK \|
188	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_REF_COMP_PWRDN_MASK \|
189	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_PWRDN_BG_MASK \|
190	/* BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_PWRDN_REFAMP_MASK \| 8 */
191	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_D_RESET_MASK \|
192	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_A_RESET_MASK \|
193	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_CK_RESET_MASK \|
194	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_2_RESET_MASK \|
195	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_1_RESET_MASK \|
196	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_0_RESET_MASK;
197
198	BREG_Write32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL, ulRegData);
199
200	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_0);
201	ulRegData \|= BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_0_RND_PWRDN_MASK;
202	BREG_Write32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_0, ulRegData);
203
204	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_1);
205	ulRegData \|= BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_1_I_PWR_DN_CH1_MASK;
206	BREG_Write32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_1, ulRegData);
207
208	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_2);
209	ulRegData \|= BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_2_I_PWRDN_CH2_MASK;
210	BREG_Write32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_2, ulRegData);
211
212	/* Power down HDMI clocks */
213	ulRegData = (BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_VEC_216M_CLK_MASK \|
214	BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_MAX_250M_CLK_MASK \|
215	BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_27M_CLK_MASK \|
216	BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_108M_CLK_MASK \|
217	BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_216M_CLK_MASK);
218
219	BREG_AtomicUpdate32(pPwr->hRegister, BCHP_CLK_DVP_HT_CLK_PM_CTRL,ulRegData,ulRegData);
220	}
221
222	/* Power Down 1394 */
223	if (BPWR_P_IsModuleChanging(pPwr, BSTD_TNF_ID))
224	{
225	BDBG_MSG(("Power Down: 1394"));
226	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_AVLINK_PHY_PHY_PM_CTRL);
227	ulRegData \|= BCHP_AVLINK_PHY_PHY_PM_CTRL_BIAS_POWER_DOWN_MASK \|
228	BCHP_AVLINK_PHY_PHY_PM_CTRL_DS_POWER_DOWN_MASK \|
229	BCHP_AVLINK_PHY_PHY_PM_CTRL_PLL_POWER_DOWN_MASK;
230	BREG_Write32(pPwr->hRegister, BCHP_AVLINK_PHY_PHY_PM_CTRL, ulRegData);
231
232	ulRegData = (BCHP_CLK_TOP1394_CLK_PM_CTRL_DIS_1394_PM_27M_CLK_MASK \|
233	BCHP_CLK_TOP1394_CLK_PM_CTRL_DIS_108M_CLK_MASK \|
234	BCHP_CLK_TOP1394_CLK_PM_CTRL_DIS_216M_CLK_MASK);
235	BREG_AtomicUpdate32(pPwr->hRegister, BCHP_CLK_TOP1394_CLK_PM_CTRL,ulRegData,ulRegData);
236
237	#if 0
238	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_AVLINK_AVRX_LPS_LINK_ON);
239	ulRegData \|= BCHP_AVLINK_AVRX_LPS_LINK_ON_lps_Disable_MASK;
240	BREG_Write32(pPwr->hRegister, BCHP_AVLINK_AVRX_LPS_LINK_ON, ulRegData);
241	#endif
242	}
243
244
245	/* Power Down Smartcard */
246	if (BPWR_P_IsModuleChanging(pPwr, BSTD_SCD_ID))
247	{
248	BDBG_MSG(("Power Down: SCD"));
249	ulRegData = (BCHP_CLK_MISC_SMARTCARD_CLOCK_0_SOURCE_SEL_MASK \|
250	BCHP_CLK_MISC_SMARTCARD_CLOCK_1_SOURCE_SEL_MASK);
251	BREG_AtomicUpdate32(pPwr->hRegister, BCHP_CLK_MISC,ulRegData,ulRegData);
252
253	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_SC_PM_CLOCK_ENA_1);
254	ulRegData &= ~BCHP_VCXO_CTL_MISC_SC_PM_CLOCK_ENA_1_CLOCK_ENA_MASK;
255	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_SC_PM_CLOCK_ENA_1, ulRegData);
256
257	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_SC_PM_DIS_CHL_1);
258	ulRegData \|= BCHP_VCXO_CTL_MISC_SC_PM_DIS_CHL_1_DIS_CH_MASK;
259	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_SC_PM_DIS_CHL_1, ulRegData);
260
261	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_SC_CTRL);
262	ulRegData \|= BCHP_VCXO_CTL_MISC_SC_CTRL_POWERDOWN_MASK \|
263	BCHP_VCXO_CTL_MISC_SC_CTRL_RESET_MASK;
264	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_SC_CTRL, ulRegData);
265	}
266
267	/* Power Down UHF */
268	if (BPWR_P_IsModuleChanging(pPwr, BSTD_UHF_ID))
269	{
270	BDBG_MSG(("Power Down: UHF"));
271	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_UHFR_GLBL_AUTOPD1);
272	ulRegData \|= BCHP_UHFR_GLBL_AUTOPD1_MANUAL_PD_MASK;
273	ulRegData &= ~BCHP_UHFR_GLBL_AUTOPD1_AUTO_PD_EN_MASK;
274	BREG_Write32(pPwr->hRegister, BCHP_UHFR_GLBL_AUTOPD1, ulRegData);
275
276	ulRegData = (BCHP_CLK_UHFR_CLK_PM_CTRL_DIS_ANA_UHFR_CLK_MASK \|
277	BCHP_CLK_UHFR_CLK_PM_CTRL_DIS_DIGI_UHFR_CLK_MASK);
278
279	BREG_AtomicUpdate32(pPwr->hRegister, BCHP_CLK_UHFR_CLK_PM_CTRL,ulRegData,ulRegData);
280	}
281
282
283	/* TestPort block */
284	BPWR_P_TestPort_Down(pPwr);
285
286	/* Power Down MDM */
287	if (BPWR_P_IsModuleChanging(pPwr, BSTD_MDM_ID))
288	{
289	BDBG_MSG(("Power Down: Modem"));
290	ulRegData = BCHP_CLK_SUN_DAA_CLK_PM_CTRL_DIS_SUN_DAA_32P4M_CLK_MASK;
291	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_SUN_DAA_CLK_PM_CTRL,ulRegData,ulRegData);
292
293	ulRegData = BCHP_CLK_SUN_SM_CLK_PM_CTRL_DIS_SUN_SM_27M_CLK_MASK;
294	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_SUN_SM_CLK_PM_CTRL,ulRegData,ulRegData);
295	}
296
297
298	/* Power Down RFM */
299	if (BPWR_P_IsModuleChanging(pPwr, BSTD_RFM_ID)) /* No other modules are tied to RFM clock */
300	{
301	/* turn on RFM clock before attempting reg access */
302	ulRegData = BCHP_CLK_RFM_CLK_PM_CTRL_DIS_RFM_108M_CLK_MASK;
303	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_RFM_CLK_PM_CTRL, ulRegData, 0);
304
305	BDBG_MSG(("Power Down: RFM"));
306	/* Power down RFM sysclk clkctl */
307	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_RFM_SYSCLK_CLKCTL);
308	ulRegData \|= BCHP_RFM_SYSCLK_CLKCTL_CLK_OFF_MASK;
309	BREG_Write32(pPwr->hRegister, BCHP_RFM_SYSCLK_CLKCTL, ulRegData);
310
311	/* Power down RFM Phase Interpolator circuit */
312	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_RFM_SYSCLK_RFM_PHASEITP_CTL);
313	ulRegData \|= BCHP_RFM_SYSCLK_RFM_PHASEITP_CTL_PHASEITP_PWRDN_MASK;
314	BREG_Write32(pPwr->hRegister, BCHP_RFM_SYSCLK_RFM_PHASEITP_CTL, ulRegData);
315
316	/* Power down RFM PLL Misc1 */
317	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_RFM_SYSCLK_PLL_MISC1);
318	ulRegData \|= BCHP_RFM_SYSCLK_PLL_MISC1_NDIV_PWRDN_MASK \|
319	BCHP_RFM_SYSCLK_PLL_MISC1_REFCOMP_PWRDN_MASK \|
320	BCHP_RFM_SYSCLK_PLL_MISC1_PWRDN_MASK;
321	BREG_Write32(pPwr->hRegister, BCHP_RFM_SYSCLK_PLL_MISC1, ulRegData);
322
323	/* Power down RFM DAC */
324	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_RFM_SYSCLK_DACCTL);
325	ulRegData \|= BCHP_RFM_SYSCLK_DACCTL_BIAS50U_OFF_MASK \|
326	BCHP_RFM_SYSCLK_DACCTL_BIASLOG_OFF_MASK;
327	BREG_Write32(pPwr->hRegister, BCHP_RFM_SYSCLK_DACCTL, ulRegData);
328
329	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_RFM_SYSCLK_DACCTL);
330	ulRegData \|= BCHP_RFM_SYSCLK_DACCTL_DAC_PWRDN_MASK;
331	BREG_Write32(pPwr->hRegister, BCHP_RFM_SYSCLK_DACCTL, ulRegData);
332
333	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_RFM_SYSCLK_DACCTL);
334	ulRegData \|= BCHP_RFM_SYSCLK_DACCTL_DAC_PWRDN_2_MASK;
335	BREG_Write32(pPwr->hRegister, BCHP_RFM_SYSCLK_DACCTL, ulRegData);
336
337
338	/* Power down RFM clock control */
339	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_RFM_SYSCLK_CLKCTL);
340	ulRegData \|= BCHP_RFM_SYSCLK_CLKCTL_RFMCLK_OFF_MASK \|
341	BCHP_RFM_SYSCLK_CLKCTL_VREG_OFF_MASK \|
342	BCHP_RFM_SYSCLK_CLKCTL_BGCORE_OFF_MASK;
343	BREG_Write32(pPwr->hRegister, BCHP_RFM_SYSCLK_CLKCTL, ulRegData);
344
345	/* Power down RFM Digital */
346	ulRegData = BCHP_CLK_RFM_CLK_PM_CTRL_DIS_RFM_108M_CLK_MASK;
347	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_RFM_CLK_PM_CTRL,ulRegData,ulRegData);
348	}
349
350	if (BPWR_P_IsModuleChanging(pPwr, BSTD_VDC_ID) && BPWR_P_IsModuleChanging(pPwr, BSTD_VBI_ID))
351	{
352	BDBG_MSG(("Power Down: VDC DACs"));
353	/* Power down TDAC BG */
354	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_BG_CTRL_0);
355	ulRegData \|= BCHP_MISC_DAC_BG_CTRL_0_PWRDN_REFAMP_MASK \|
356	BCHP_MISC_DAC_BG_CTRL_0_PWRDN_MASK;
357	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_BG_CTRL_0, ulRegData);
358
359	/* Power down TDAC 0 */
360	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_0_CTRL);
361	ulRegData \|= BCHP_MISC_DAC_0_CTRL_PWRDN_MASK;
362	ulRegData &= ~BCHP_MISC_DAC_0_CTRL_PWRUP_BAIS_MASK;
363	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_0_CTRL, ulRegData);
364
365	/* Power down TDAC 1 */
366	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_1_CTRL);
367	ulRegData \|= BCHP_MISC_DAC_1_CTRL_PWRDN_MASK;
368	ulRegData &= ~BCHP_MISC_DAC_1_CTRL_PWRUP_BAIS_MASK;
369	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_1_CTRL, ulRegData);
370
371	/* Power down TDAC 2 */
372	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_2_CTRL);
373	ulRegData \|= BCHP_MISC_DAC_2_CTRL_PWRDN_MASK;
374	ulRegData &= ~BCHP_MISC_DAC_2_CTRL_PWRUP_BAIS_MASK;
375	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_2_CTRL, ulRegData);
376
377	/* Power down TDAC 216 MHz clock */
378	ulRegData = BCHP_CLK_TDAC_CLK_PM_CTRL_DIS_TDAC_216M_CLK_MASK;
379	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_TDAC_CLK_PM_CTRL,ulRegData,ulRegData);
380
381	/* Power down QDAC */
382	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_BG_CTRL_1);
383	ulRegData \|= BCHP_MISC_DAC_BG_CTRL_1_PWRDN_REFAMP_MASK \|
384	BCHP_MISC_DAC_BG_CTRL_1_PWRDN_MASK;
385	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_BG_CTRL_1, ulRegData);
386
387	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_3_CTRL);
388	ulRegData \|= BCHP_MISC_DAC_3_CTRL_PWRDN_MASK;
389	ulRegData &= ~BCHP_MISC_DAC_3_CTRL_PWRUP_BAIS_MASK;
390	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_3_CTRL, ulRegData);
391
392	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_4_CTRL);
393	ulRegData \|= BCHP_MISC_DAC_4_CTRL_PWRDN_MASK;
394	ulRegData &= ~BCHP_MISC_DAC_4_CTRL_PWRUP_BAIS_MASK;
395	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_4_CTRL, ulRegData);
396
397	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_5_CTRL);
398	ulRegData \|= BCHP_MISC_DAC_5_CTRL_PWRDN_MASK;
399	ulRegData &= ~BCHP_MISC_DAC_5_CTRL_PWRUP_BAIS_MASK;
400	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_5_CTRL, ulRegData);
401
402	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_6_CTRL);
403	ulRegData \|= BCHP_MISC_DAC_6_CTRL_PWRDN_MASK;
404	ulRegData &= ~BCHP_MISC_DAC_6_CTRL_PWRUP_BAIS_MASK;
405	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_6_CTRL, ulRegData);
406
407	/* Power down QDAC 216 MHz clock */
408	ulRegData = BCHP_CLK_QDAC_CLK_PM_CTRL_DIS_QDAC_216M_CLK_MASK;
409	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_QDAC_CLK_PM_CTRL,ulRegData,ulRegData);
410	}
411
412
413	if (BPWR_P_IsModuleChanging(pPwr, BSTD_RAP_ID))
414	{
415
416	BDBG_MSG(("Power Down: RAP AIO"));
417	/* Power down HifiDriver0 */
418	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_AIO_MISC_PWRDOWN);
419	ulRegData \|= BCHP_AIO_MISC_PWRDOWN_DAC0_MASK;
420	BREG_Write32(pPwr->hRegister, BCHP_AIO_MISC_PWRDOWN, ulRegData);
421
422	/* Power down HifiDriver1 */
423	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_AIO_MISC_PWRDOWN);
424	ulRegData \|= BCHP_AIO_MISC_PWRDOWN_DAC1_MASK;
425	BREG_Write32(pPwr->hRegister, BCHP_AIO_MISC_PWRDOWN, ulRegData);
426
427
428	/* Power down AC0 */
429	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_AC0_CTRL);
430	ulRegData \|= BCHP_VCXO_CTL_MISC_AC0_CTRL_RESET_MASK \|
431	BCHP_VCXO_CTL_MISC_AC0_CTRL_POWERDOWN_MASK;
432	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_AC0_CTRL, ulRegData);
433
434	/* Power down AC1 */
435	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_AC1_CTRL);
436	ulRegData \|= BCHP_VCXO_CTL_MISC_AC1_CTRL_RESET_MASK \|
437	BCHP_VCXO_CTL_MISC_AC1_CTRL_POWERDOWN_MASK;
438	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_AC1_CTRL, ulRegData);
439
440	/* Power down AC2 */
441	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_AC2_CTRL);
442	ulRegData \|= BCHP_VCXO_CTL_MISC_AC2_CTRL_RESET_MASK \|
443	BCHP_VCXO_CTL_MISC_AC2_CTRL_POWERDOWN_MASK;
444	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_AC2_CTRL, ulRegData);
445
446
447	/* Power down AIO clocks */
448	ulRegData = (BCHP_CLK_RPT_AIO_CLK_PM_CTRL_DIS_216M_CLK_MASK \|
449	#if BCHP_VER >= BCHP_VER_B0
450	BCHP_CLK_RPT_AIO_CLK_PM_CTRL_DIS_RPT_250M_CLK_MASK);
451	#else
452	BCHP_CLK_RPT_AIO_CLK_PM_CTRL_DIS_RPT_PROG_CLK_MASK);
453	#endif
454	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_RPT_AIO_CLK_PM_CTRL,ulRegData,ulRegData);
455
456	/* Power down VC1 */
457	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1);
458	ulRegData &= ~BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_CLOCK_ENA_MASK;
459	ulRegData &= ~BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_EN_CMLBUF_MASK;
460	/* DO NOT Enable this in AX - Should be fixed in B0 */
461	#if BCHP_VER >= BCHP_VER_B0
462	ulRegData \|= BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_DIS_CH_MASK;
463	#endif
464	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1, ulRegData);
465
466
467	#if BCHP_VER >= BCHP_VER_B0
468	/* Power down D2CDiff */
469	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_AIO_MISC_PWRDOWN);
470	ulRegData \|= BCHP_AIO_MISC_CTRL_PWRDWN_D2CDIFF_MASK;
471	BREG_Write32(pPwr->hRegister, BCHP_AIO_MISC_PWRDOWN, ulRegData);
472	#endif
473
474	/* Power down AIO 108M clock */
475	ulRegData = BCHP_CLK_RPT_AIO_CLK_PM_CTRL_DIS_108M_CLK_MASK;
476	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_RPT_AIO_CLK_PM_CTRL,ulRegData,ulRegData);
477	}
478
479
480	if (BPWR_P_IsModuleChanging(pPwr, BSTD_VDC_ID) && BPWR_P_IsModuleChanging(pPwr, BSTD_VBI_ID))
481	{
482	BDBG_MSG(("Power Down: VEC"));
483	/* Power down VEC 656 */
484	ulRegData = BCHP_CLK_VEC_656_CLK_PM_CTRL_DIS_VEC_VCXO_656_CLK_MASK;
485	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_VEC_656_CLK_PM_CTRL,ulRegData,ulRegData);
486
487	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1);
488	ulRegData \|= BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1_DIS_CH_MASK;
489	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1, ulRegData);
490
491	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_1);
492	ulRegData \|= BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_1_DIS_CH_MASK;
493	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_1, ulRegData);
494
495	/* Power down VEC */
496	ulRegData = (BCHP_CLK_VEC_CLK_PM_CTRL_DIS_216M_CLK_MASK \|
497	BCHP_CLK_VEC_CLK_PM_CTRL_DIS_108M_CLK_MASK \|
498	BCHP_CLK_VEC_CLK_PM_CTRL_DIS_VEC_DAC_216M_CLK_MASK);
499	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_VEC_CLK_PM_CTRL,ulRegData,ulRegData);
500	}
501
502
503	if (BPWR_P_IsModuleChanging(pPwr, BSTD_GRC_ID))
504	{
505	BDBG_MSG(("Power Down: GFX 2D"));
506	/* Power down GFX 2D */
507	ulRegData = (BCHP_CLK_GFX_2D_PM_CTRL_DIS_216M_CLK_MASK \|
508	BCHP_CLK_GFX_2D_PM_CTRL_DIS_108M_CLK_MASK);
509	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_GFX_2D_PM_CTRL,ulRegData,ulRegData);
510	}
511
512
513	if (BPWR_P_IsModuleChanging(pPwr, BSTD_P3D_ID) )
514	{
515	BDBG_MSG(("Power Down: GFX 3D"));
516	/* Power down GFX 3D */
517	ulRegData = (BCHP_CLK_GFX_3D_PM_CTRL_DIS_216M_CLK_MASK \|
518	BCHP_CLK_GFX_3D_PM_CTRL_DIS_108M_CLK_MASK);
519	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_GFX_3D_PM_CTRL,ulRegData,ulRegData);
520	}
521
522
523	if (BPWR_P_IsModuleChanging(pPwr, BSTD_DMA_ID) )
524	{
525	BDBG_MSG(("Power Down: DMA"));
526	/* Power down DMA */
527	ulRegData = BCHP_CLK_SECTOP_DMA_PM_CTRL_DIS_216M_CLK_MASK;
528	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_SECTOP_DMA_PM_CTRL,ulRegData,ulRegData);
529	}
530
531
532	if (BPWR_P_IsModuleChanging(pPwr, BSTD_VDC_ID) && BPWR_P_IsModuleChanging(pPwr, BSTD_VBI_ID))
533	{
534	BDBG_MSG(("Power Down: VDC"));
535
536	/* Power down BVNE 216 MHz and 108 MHz Clks */
537	ulRegData = (BCHP_CLK_BVN_EDGE_PM_CTRL_DIS_216M_CLK_MASK \|
538	BCHP_CLK_BVN_EDGE_PM_CTRL_DIS_108M_CLK_MASK);
539	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_BVN_EDGE_PM_CTRL,ulRegData,ulRegData);
540
541
542	/* Power down MCVP 216 MHz and 108 MHz Clks */
543	ulRegData = (BCHP_CLK_BVN_MCVP_PM_CTRL_DIS_216M_CLK_MASK \|
544	BCHP_CLK_BVN_MCVP_PM_CTRL_DIS_108M_CLK_MASK);
545	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_BVN_MCVP_PM_CTRL,ulRegData,ulRegData);
546
547
548	/* Power down BVNM 216 MHz and 108 MHz Clks */
549	ulRegData = (BCHP_CLK_BVN_MIDDLE_PM_CTRL_DIS_216M_CLK_MASK \|
550	BCHP_CLK_BVN_MIDDLE_PM_CTRL_DIS_108M_CLK_MASK);
551	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_BVN_MIDDLE_PM_CTRL,ulRegData,ulRegData);
552	}
553
554
555	if (BPWR_P_IsModuleChanging(pPwr, BSTD_XVD_ID))
556	{
557	BDBG_MSG(("Power Down: AVD"));
558
559	/* Power down AVD0 clocks */
560	ulRegData = (BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_216M_CLK_MASK \|
561	#if BCHP_VER >= BCHP_VER_B0
562	BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_250M_CLK_MASK);
563	#else
564	BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_AVD0_PROG_CLK_MASK);
565	#endif
566	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_AVD0_CLK_PM_CTRL,ulRegData,ulRegData);
567
568	/* Power down AVD1 clocks */
569	ulRegData = (BCHP_CLK_AVD1_CLK_PM_CTRL_DIS_216M_CLK_MASK \|
570	#if BCHP_VER >= BCHP_VER_B0
571	BCHP_CLK_AVD1_CLK_PM_CTRL_DIS_250M_CLK_MASK);
572	#else
573	BCHP_CLK_AVD1_CLK_PM_CTRL_DIS_AVD1_PROG_CLK_MASK);
574	#endif
575	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_AVD1_CLK_PM_CTRL,ulRegData,ulRegData);
576
577	#if BCHP_VER >= BCHP_VER_B0
578	/* Power down */
579	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6);
580	ulRegData &= ~BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_EN_CMLBUF_MASK;
581	ulRegData &= ~BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_CLOCK_ENA_MASK;
582	ulRegData \|= BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_DIS_CH_MASK;
583	/* DO NOT Enable in Ax */
584	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6, ulRegData);
585	#else
586	/* Power down FMISC */
587	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2);
588	ulRegData &= ~BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_EN_CMLBUF_MASK;
589	ulRegData &= ~BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_CLOCK_ENA_MASK;
590	/* DO NOT Enable in Ax */
591	/* ulRegData \|= BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_DIS_CH_MASK; */
592	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2, ulRegData);
593	#endif
594
595	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_AVD_RGR_0_SW_RESET_0);
596	ulRegData \|= BCHP_AVD_RGR_0_SW_RESET_0_disable_avd_clk_rcvr_MASK;
597	BREG_Write32(pPwr->hRegister, BCHP_AVD_RGR_0_SW_RESET_0, ulRegData);
598
599	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_AVD_RGR_1_SW_RESET_0);
600	ulRegData \|= BCHP_AVD_RGR_0_SW_RESET_0_disable_avd_clk_rcvr_MASK;
601	BREG_Write32(pPwr->hRegister, BCHP_AVD_RGR_1_SW_RESET_0, ulRegData);
602
603	/* Power down AVD0 108M clock */
604	ulRegData = BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_108M_CLK_MASK;
605	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_AVD0_CLK_PM_CTRL,ulRegData,ulRegData);
606
607	/* Power down AVD1 108M clock */
608	ulRegData = BCHP_CLK_AVD1_CLK_PM_CTRL_DIS_108M_CLK_MASK;
609	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_AVD1_CLK_PM_CTRL,ulRegData,ulRegData);
610	}
611
612
613	if (BPWR_P_IsModuleChanging(pPwr, BSTD_XPT_ID))
614	{
615	BDBG_MSG(("Power Down: XPT"));
616	ulRegData = (BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_20P25M_CLK_MASK \|
617	BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_27M_CLK_MASK \|
618	BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_40P5M_CLK_MASK \|
619	BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_54M_CLK_MASK \|
620	BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_81M_CLK_MASK \|
621	BCHP_CLK_XPT_CLK_PM_CTRL_DIS_216M_CLK_MASK \|
622	BCHP_CLK_XPT_CLK_PM_CTRL_DIS_108M_CLK_MASK);
623	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_XPT_CLK_PM_CTRL,ulRegData,ulRegData);
624	}
625
626	if (BPWR_P_IsModuleChanging(pPwr, BSTD_VDC_ID) && BPWR_P_IsModuleChanging(pPwr, BSTD_SCD_ID) && BPWR_P_IsModuleChanging(pPwr, BSTD_RAP_ID))
627	{
628	BDBG_MSG(("Power Down: System PLL's"));
629	/* Power down VC0 */
630	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC0_CTRL);
631	ulRegData \|= BCHP_VCXO_CTL_MISC_VC0_CTRL_DRESET_MASK \|
632	BCHP_VCXO_CTL_MISC_VC0_CTRL_ARESET_MASK \|
633	BCHP_VCXO_CTL_MISC_VC0_CTRL_POWERDOWN_MASK;
634	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC0_CTRL, ulRegData);
635
636	/* Power down VC1 */
637	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC1_CTRL);
638	ulRegData \|= BCHP_VCXO_CTL_MISC_VC1_CTRL_DRESET_MASK \|
639	BCHP_VCXO_CTL_MISC_VC1_CTRL_ARESET_MASK \|
640	BCHP_VCXO_CTL_MISC_VC1_CTRL_POWERDOWN_MASK;
641	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC1_CTRL, ulRegData);
642	}
643
644	if (BPWR_P_IsModuleChanging(pPwr, BSTD_RAP_ID) && BPWR_P_IsModuleChanging(pPwr, BSTD_XVD_ID))
645	{
646	BDBG_MSG(("Power Down: System PLL's"));
647	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL);
648	ulRegData \|= BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_POWERDOWN_MASK \|
649	BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_RESET_MASK;
650	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL, ulRegData);
651	}
652
653	if (BPWR_P_IsModuleChanging(pPwr, BSTD_XPT_ID) && BPWR_P_IsModuleChanging(pPwr, BSTD_SCD_ID))
654	{
655	BDBG_MSG(("Power Down: System PLL's"));
656	ulRegData = BCHP_CLK_SYS_PLL_0_PLL_3_DIS_CH_MASK;
657	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_SYS_PLL_0_PLL_3,ulRegData,ulRegData);
658	}
659	/*
660	*============================================================
661	* Power Up
662	*============================================================
663	*/
664	}
665	else
666	{
667
668	if (BPWR_P_IsModuleChanging(pPwr, BSTD_XPT_ID) && BPWR_P_IsModuleChanging(pPwr, BSTD_SCD_ID))
669	{
670	BDBG_MSG(("Power Up: System PLL's"));
671	ulRegData = BCHP_CLK_SYS_PLL_0_PLL_3_DIS_CH_MASK;
672	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_SYS_PLL_0_PLL_3,ulRegData,0);
673	}
674
675
676	if (BPWR_P_IsModuleChanging(pPwr, BSTD_RAP_ID) && BPWR_P_IsModuleChanging(pPwr, BSTD_XVD_ID))
677	{
678	BDBG_MSG(("Power Up: System PLL's"));
679	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL);
680	ulRegData &= ~(BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_POWERDOWN_MASK \|
681	BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL_RESET_MASK);
682	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CTRL, ulRegData);
683	}
684
685	if (BPWR_P_IsModuleChanging(pPwr, BSTD_VDC_ID) && BPWR_P_IsModuleChanging(pPwr, BSTD_SCD_ID) && BPWR_P_IsModuleChanging(pPwr, BSTD_RAP_ID))
686	{
687	BDBG_MSG(("Power Up: System PLL's"));
688	/* Power up VC0 */
689	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC0_CTRL);
690	ulRegData &= ~(BCHP_VCXO_CTL_MISC_VC0_CTRL_DRESET_MASK \|
691	BCHP_VCXO_CTL_MISC_VC0_CTRL_ARESET_MASK \|
692	BCHP_VCXO_CTL_MISC_VC0_CTRL_POWERDOWN_MASK);
693	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC0_CTRL, ulRegData);
694
695	/* Power up VC1 */
696	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC1_CTRL);
697	ulRegData &= ~(BCHP_VCXO_CTL_MISC_VC1_CTRL_DRESET_MASK \|
698	BCHP_VCXO_CTL_MISC_VC1_CTRL_ARESET_MASK \|
699	BCHP_VCXO_CTL_MISC_VC1_CTRL_POWERDOWN_MASK);
700	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC1_CTRL, ulRegData);
701	}
702
703	if (BPWR_P_IsModuleChanging(pPwr, BSTD_XPT_ID))
704	{
705	BDBG_MSG(("Power Up: XPT"));
706	ulRegData = (BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_20P25M_CLK_MASK \|
707	BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_27M_CLK_MASK \|
708	BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_40P5M_CLK_MASK \|
709	BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_54M_CLK_MASK \|
710	BCHP_CLK_XPT_CLK_PM_CTRL_DIS_XPT_81M_CLK_MASK \|
711	BCHP_CLK_XPT_CLK_PM_CTRL_DIS_216M_CLK_MASK \|
712	BCHP_CLK_XPT_CLK_PM_CTRL_DIS_108M_CLK_MASK);
713	BREG_AtomicUpdate32(pPwr->hRegister, BCHP_CLK_XPT_CLK_PM_CTRL,ulRegData,0);
714	}
715
716	if (BPWR_P_IsModuleChanging(pPwr, BSTD_XVD_ID))
717	{
718	BDBG_MSG(("Power Up: AVD"));
719
720	/* Power up AVD0 108M clock */
721	ulRegData = BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_108M_CLK_MASK;
722	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_AVD0_CLK_PM_CTRL,ulRegData,0);
723
724	/* Power up AVD1 108M clock */
725	ulRegData = BCHP_CLK_AVD1_CLK_PM_CTRL_DIS_108M_CLK_MASK;
726	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_AVD1_CLK_PM_CTRL,ulRegData,0);
727
728	/* Power up RGR clocks */
729	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_AVD_RGR_0_SW_RESET_0);
730	ulRegData &= ~BCHP_AVD_RGR_0_SW_RESET_0_disable_avd_clk_rcvr_MASK;
731	BREG_Write32(pPwr->hRegister, BCHP_AVD_RGR_0_SW_RESET_0, ulRegData);
732
733	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_AVD_RGR_1_SW_RESET_0);
734	ulRegData &= ~BCHP_AVD_RGR_0_SW_RESET_0_disable_avd_clk_rcvr_MASK;
735	BREG_Write32(pPwr->hRegister, BCHP_AVD_RGR_1_SW_RESET_0, ulRegData);
736
737
738	#if BCHP_VER >= BCHP_VER_B0
739	/* Power up */
740	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6);
741	ulRegData \|= BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_EN_CMLBUF_MASK \|
742	BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_CLOCK_ENA_MASK;
743	ulRegData &= ~BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6_DIS_CH_MASK;
744	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_6, ulRegData);
745	#else
746	/* Power up FMISC */
747	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2);
748	ulRegData \|= BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_EN_CMLBUF_MASK \|
749	BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_CLOCK_ENA_MASK;
750	/* DO NOT Enable in Ax */
751	/* ulRegData \|= BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2_DIS_CH_MASK; */
752	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_2, ulRegData);
753	#endif
754
755	/* Power up AVD1 clocks */
756	ulRegData = (BCHP_CLK_AVD1_CLK_PM_CTRL_DIS_216M_CLK_MASK \|
757	#if BCHP_VER >= BCHP_VER_B0
758	BCHP_CLK_AVD1_CLK_PM_CTRL_DIS_250M_CLK_MASK);
759	#else
760	BCHP_CLK_AVD1_CLK_PM_CTRL_DIS_AVD1_PROG_CLK_MASK);
761	#endif
762	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_AVD1_CLK_PM_CTRL,ulRegData,0);
763
764	/* Power up AVD0 clocks */
765	ulRegData = (BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_216M_CLK_MASK \|
766	#if BCHP_VER >= BCHP_VER_B0
767	BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_250M_CLK_MASK);
768	#else
769	BCHP_CLK_AVD0_CLK_PM_CTRL_DIS_AVD0_PROG_CLK_MASK);
770	#endif
771	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_AVD0_CLK_PM_CTRL,ulRegData,0);
772	}
773
774	if (BPWR_P_IsModuleChanging(pPwr, BSTD_VDC_ID) && BPWR_P_IsModuleChanging(pPwr, BSTD_VBI_ID))
775	{
776	BDBG_MSG(("Power Up: VDC"));
777	/* Power up BVNM 216 MHz and 108 MHz Clks */
778	ulRegData = (BCHP_CLK_BVN_MIDDLE_PM_CTRL_DIS_216M_CLK_MASK \|
779	BCHP_CLK_BVN_MIDDLE_PM_CTRL_DIS_108M_CLK_MASK);
780	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_BVN_MIDDLE_PM_CTRL,ulRegData,0);
781
782	/* Power up MCVP 216 MHz and 108 MHz Clks */
783	ulRegData = (BCHP_CLK_BVN_MCVP_PM_CTRL_DIS_216M_CLK_MASK \|
784	BCHP_CLK_BVN_MCVP_PM_CTRL_DIS_108M_CLK_MASK);
785	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_BVN_MCVP_PM_CTRL,ulRegData,0);
786
787	/* Power up BVNE 216 MHz and 108 MHz Clks */
788	ulRegData = (BCHP_CLK_BVN_EDGE_PM_CTRL_DIS_216M_CLK_MASK \|
789	BCHP_CLK_BVN_EDGE_PM_CTRL_DIS_108M_CLK_MASK);
790	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_BVN_EDGE_PM_CTRL,ulRegData,0);
791	}
792
793	if (BPWR_P_IsModuleChanging(pPwr, BSTD_DMA_ID) )
794	{
795	BDBG_MSG(("Power Up: DMA"));
796	/* Power up DMA */
797	ulRegData = BCHP_CLK_SECTOP_DMA_PM_CTRL_DIS_216M_CLK_MASK;
798	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_SECTOP_DMA_PM_CTRL,ulRegData,0);
799	}
800
801	if (BPWR_P_IsModuleChanging(pPwr, BSTD_P3D_ID) )
802	{
803	BDBG_MSG(("Power Up: GFX 3D"));
804	/* Power up GFX 3D */
805	ulRegData = (BCHP_CLK_GFX_3D_PM_CTRL_DIS_216M_CLK_MASK \|
806	BCHP_CLK_GFX_3D_PM_CTRL_DIS_108M_CLK_MASK);
807	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_GFX_3D_PM_CTRL,ulRegData,0);
808	}
809
810	if (BPWR_P_IsModuleChanging(pPwr, BSTD_GRC_ID) )
811	{
812	BDBG_MSG(("Power Up: GFX 2D"));
813	/* Power up GFX 2D */
814	ulRegData = (BCHP_CLK_GFX_2D_PM_CTRL_DIS_216M_CLK_MASK \|
815	BCHP_CLK_GFX_2D_PM_CTRL_DIS_108M_CLK_MASK);
816	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_GFX_2D_PM_CTRL,ulRegData,0);
817	}
818
819	if (BPWR_P_IsModuleChanging(pPwr, BSTD_VDC_ID) && BPWR_P_IsModuleChanging(pPwr, BSTD_VBI_ID))
820	{
821	BDBG_MSG(("Power Up: VEC"));
822	/* Power up VEC */
823	ulRegData = (BCHP_CLK_VEC_CLK_PM_CTRL_DIS_216M_CLK_MASK \|
824	BCHP_CLK_VEC_CLK_PM_CTRL_DIS_108M_CLK_MASK \|
825	BCHP_CLK_VEC_CLK_PM_CTRL_DIS_VEC_DAC_216M_CLK_MASK);
826	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_VEC_CLK_PM_CTRL,ulRegData,0);
827
828	/* Power up VEC 656 */
829	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1);
830	ulRegData &= ~BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1_DIS_CH_MASK;
831	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1, ulRegData);
832
833	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_1);
834	ulRegData &= ~BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_1_DIS_CH_MASK;
835	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_VC1_PM_DIS_CHL_1, ulRegData);
836
837	/* Power up VEC 656 */
838	ulRegData = BCHP_CLK_VEC_656_CLK_PM_CTRL_DIS_VEC_VCXO_656_CLK_MASK;
839	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_VEC_656_CLK_PM_CTRL,ulRegData,0);
840	}
841
842
843	if (BPWR_P_IsModuleChanging(pPwr, BSTD_RAP_ID))
844	{
845	BDBG_MSG(("Power Up: RAP AIO"));
846
847	/* Power up AIO 108M clock */
848	ulRegData = BCHP_CLK_RPT_AIO_CLK_PM_CTRL_DIS_108M_CLK_MASK;
849	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_RPT_AIO_CLK_PM_CTRL,ulRegData,0);
850
851
852	#if BCHP_VER >= BCHP_VER_B0
853	/* Power up D2CDiff */
854	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_AIO_MISC_PWRDOWN);
855	ulRegData &= ~BCHP_AIO_MISC_CTRL_PWRDWN_D2CDIFF_MASK;
856	BREG_Write32(pPwr->hRegister, BCHP_AIO_MISC_PWRDOWN, ulRegData);
857	#endif
858
859	/* Power up VC1 */
860	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1);
861	ulRegData \|= (BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_CLOCK_ENA_MASK \|
862	BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_EN_CMLBUF_MASK);
863	/* DO NOT Enable this in AX - Should be fixed in B0 */
864	#if BCHP_VER >= BCHP_VER_B0
865	ulRegData &= ~BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1_DIS_CH_MASK;
866	#endif
867	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_RAP_AVD_PLL_CHL_1, ulRegData);
868
869	/* Power up AIO clocks */
870	ulRegData = (BCHP_CLK_RPT_AIO_CLK_PM_CTRL_DIS_216M_CLK_MASK \|
871	#if BCHP_VER >= BCHP_VER_B0
872	BCHP_CLK_RPT_AIO_CLK_PM_CTRL_DIS_RPT_250M_CLK_MASK);
873	#else
874	BCHP_CLK_RPT_AIO_CLK_PM_CTRL_DIS_RPT_PROG_CLK_MASK);
875	#endif
876	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_RPT_AIO_CLK_PM_CTRL,ulRegData,0);
877
878
879	/* Power up AC2 */
880	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_AC2_CTRL);
881	ulRegData &= ~(BCHP_VCXO_CTL_MISC_AC2_CTRL_RESET_MASK \|
882	BCHP_VCXO_CTL_MISC_AC2_CTRL_POWERDOWN_MASK);
883	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_AC2_CTRL, ulRegData);
884
885	/* Power up AC1 */
886	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_AC1_CTRL);
887	ulRegData &= ~(BCHP_VCXO_CTL_MISC_AC1_CTRL_RESET_MASK \|
888	BCHP_VCXO_CTL_MISC_AC1_CTRL_POWERDOWN_MASK);
889	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_AC1_CTRL, ulRegData);
890
891	/* Power up AC0 */
892	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_AC0_CTRL);
893	ulRegData &= ~(BCHP_VCXO_CTL_MISC_AC0_CTRL_RESET_MASK \|
894	BCHP_VCXO_CTL_MISC_AC0_CTRL_POWERDOWN_MASK);
895	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_AC0_CTRL, ulRegData);
896
897
898	/* Power up HifiDriver1 */
899	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_AIO_MISC_PWRDOWN);
900	ulRegData &= ~BCHP_AIO_MISC_PWRDOWN_DAC1_MASK;
901	BREG_Write32(pPwr->hRegister, BCHP_AIO_MISC_PWRDOWN, ulRegData);
902
903	/* Power up HifiDriver0 */
904	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_AIO_MISC_PWRDOWN);
905	ulRegData &= ~BCHP_AIO_MISC_PWRDOWN_DAC0_MASK;
906	BREG_Write32(pPwr->hRegister, BCHP_AIO_MISC_PWRDOWN, ulRegData);
907	}
908
909
910	if (BPWR_P_IsModuleChanging(pPwr, BSTD_VDC_ID) && BPWR_P_IsModuleChanging(pPwr, BSTD_VBI_ID))
911	{
912	BDBG_MSG(("Power Up: VDC DACs"));
913	/* Power up QDAC 216 MHz clock */
914	ulRegData = BCHP_CLK_QDAC_CLK_PM_CTRL_DIS_QDAC_216M_CLK_MASK;
915	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_QDAC_CLK_PM_CTRL,ulRegData,0);
916
917	/* Power up QDAC */
918	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_6_CTRL);
919	ulRegData &= ~BCHP_MISC_DAC_6_CTRL_PWRDN_MASK;
920	ulRegData \|= BCHP_MISC_DAC_6_CTRL_PWRUP_BAIS_MASK;
921	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_6_CTRL, ulRegData);
922
923	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_5_CTRL);
924	ulRegData &= ~BCHP_MISC_DAC_5_CTRL_PWRDN_MASK;
925	ulRegData \|= BCHP_MISC_DAC_5_CTRL_PWRUP_BAIS_MASK;
926	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_5_CTRL, ulRegData);
927
928	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_4_CTRL);
929	ulRegData &= ~BCHP_MISC_DAC_4_CTRL_PWRDN_MASK;
930	ulRegData \|= BCHP_MISC_DAC_4_CTRL_PWRUP_BAIS_MASK;
931	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_4_CTRL, ulRegData);
932
933	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_3_CTRL);
934	ulRegData &= ~BCHP_MISC_DAC_3_CTRL_PWRDN_MASK;
935	ulRegData \|= BCHP_MISC_DAC_3_CTRL_PWRUP_BAIS_MASK;
936	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_3_CTRL, ulRegData);
937
938	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_BG_CTRL_1);
939	ulRegData &= ~(BCHP_MISC_DAC_BG_CTRL_1_PWRDN_REFAMP_MASK \|
940	BCHP_MISC_DAC_BG_CTRL_1_PWRDN_MASK);
941	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_BG_CTRL_1, ulRegData);
942
943	/* Power up TDAC 216 MHz clock */
944	ulRegData = BCHP_CLK_TDAC_CLK_PM_CTRL_DIS_TDAC_216M_CLK_MASK;
945	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_TDAC_CLK_PM_CTRL,ulRegData,0);
946
947	/* Power up TDAC 2 */
948	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_2_CTRL);
949	ulRegData &= ~BCHP_MISC_DAC_2_CTRL_PWRDN_MASK;
950	ulRegData \|= BCHP_MISC_DAC_2_CTRL_PWRUP_BAIS_MASK;
951	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_2_CTRL, ulRegData);
952
953	/* Power up TDAC 1 */
954	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_1_CTRL);
955	ulRegData &= ~BCHP_MISC_DAC_1_CTRL_PWRDN_MASK;
956	ulRegData \|= BCHP_MISC_DAC_1_CTRL_PWRUP_BAIS_MASK;
957	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_1_CTRL, ulRegData);
958
959	/* Power up TDAC 0 */
960	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_0_CTRL);
961	ulRegData &= ~BCHP_MISC_DAC_0_CTRL_PWRDN_MASK;
962	ulRegData \|= BCHP_MISC_DAC_0_CTRL_PWRUP_BAIS_MASK;
963	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_0_CTRL, ulRegData);
964
965	/* Power up TDAC BG */
966	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_MISC_DAC_BG_CTRL_0);
967	ulRegData &= ~(BCHP_MISC_DAC_BG_CTRL_0_PWRDN_REFAMP_MASK \|
968	BCHP_MISC_DAC_BG_CTRL_0_PWRDN_MASK);
969	BREG_Write32(pPwr->hRegister, BCHP_MISC_DAC_BG_CTRL_0, ulRegData);
970	}
971
972
973	/* Power Up RFM */
974	if (BPWR_P_IsModuleChanging(pPwr, BSTD_RFM_ID)) /* No other modules are tied to RFM clock */
975	{
976	/* turn on RFM clock before attempting reg access */
977	ulRegData = BCHP_CLK_RFM_CLK_PM_CTRL_DIS_RFM_108M_CLK_MASK;
978	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_RFM_CLK_PM_CTRL, ulRegData, 0);
979
980	BDBG_MSG(("Power Up: RFM"));
981	/* Power up RFM sysclk clkctl */
982	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_RFM_SYSCLK_CLKCTL);
983	ulRegData &= ~BCHP_RFM_SYSCLK_CLKCTL_CLK_OFF_MASK;
984	BREG_Write32(pPwr->hRegister, BCHP_RFM_SYSCLK_CLKCTL, ulRegData);
985
986	/* Power up RFM Phase Interpolator circuit */
987	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_RFM_SYSCLK_RFM_PHASEITP_CTL);
988	ulRegData &= ~BCHP_RFM_SYSCLK_RFM_PHASEITP_CTL_PHASEITP_PWRDN_MASK;
989	BREG_Write32(pPwr->hRegister, BCHP_RFM_SYSCLK_RFM_PHASEITP_CTL, ulRegData);
990
991	/* Power up RFM PLL Misc1 */
992	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_RFM_SYSCLK_PLL_MISC1);
993	ulRegData &= ~(BCHP_RFM_SYSCLK_PLL_MISC1_NDIV_PWRDN_MASK \|
994	BCHP_RFM_SYSCLK_PLL_MISC1_REFCOMP_PWRDN_MASK \|
995	BCHP_RFM_SYSCLK_PLL_MISC1_PWRDN_MASK);
996	BREG_Write32(pPwr->hRegister, BCHP_RFM_SYSCLK_PLL_MISC1, ulRegData);
997
998	/* Power up RFM DAC */
999	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_RFM_SYSCLK_DACCTL);
1000	ulRegData &= ~(BCHP_RFM_SYSCLK_DACCTL_BIAS50U_OFF_MASK \|
1001	BCHP_RFM_SYSCLK_DACCTL_BIASLOG_OFF_MASK);
1002	BREG_Write32(pPwr->hRegister, BCHP_RFM_SYSCLK_DACCTL, ulRegData);
1003
1004	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_RFM_SYSCLK_DACCTL);
1005	ulRegData &= ~BCHP_RFM_SYSCLK_DACCTL_DAC_PWRDN_MASK;
1006	BREG_Write32(pPwr->hRegister, BCHP_RFM_SYSCLK_DACCTL, ulRegData);
1007
1008	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_RFM_SYSCLK_DACCTL);
1009	ulRegData &= ~BCHP_RFM_SYSCLK_DACCTL_DAC_PWRDN_2_MASK;
1010	BREG_Write32(pPwr->hRegister, BCHP_RFM_SYSCLK_DACCTL, ulRegData);
1011
1012
1013	/* Power up RFM clock control */
1014	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_RFM_SYSCLK_CLKCTL);
1015	ulRegData &= ~(BCHP_RFM_SYSCLK_CLKCTL_RFMCLK_OFF_MASK \|
1016	BCHP_RFM_SYSCLK_CLKCTL_VREG_OFF_MASK \|
1017	BCHP_RFM_SYSCLK_CLKCTL_BGCORE_OFF_MASK);
1018	BREG_Write32(pPwr->hRegister, BCHP_RFM_SYSCLK_CLKCTL, ulRegData);
1019
1020	/* Power up RFM Digital */
1021	ulRegData = BCHP_CLK_RFM_CLK_PM_CTRL_DIS_RFM_108M_CLK_MASK;
1022	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_RFM_CLK_PM_CTRL,ulRegData,0);
1023	}
1024
1025
1026	/* Power Up MDM */
1027	if (BPWR_P_IsModuleChanging(pPwr, BSTD_MDM_ID))
1028	{
1029	BDBG_MSG(("Power Up: Modem"));
1030	ulRegData = BCHP_CLK_SUN_SM_CLK_PM_CTRL_DIS_SUN_SM_27M_CLK_MASK;
1031	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_SUN_SM_CLK_PM_CTRL,ulRegData,0);
1032
1033	ulRegData = BCHP_CLK_SUN_DAA_CLK_PM_CTRL_DIS_SUN_DAA_32P4M_CLK_MASK;
1034	BREG_AtomicUpdate32( pPwr->hRegister, BCHP_CLK_SUN_DAA_CLK_PM_CTRL,ulRegData,0);
1035	}
1036
1037	/* Test block */
1038	BPWR_P_TestPort_Up(pPwr);
1039
1040	/* Power Up UHF */
1041	if (BPWR_P_IsModuleChanging(pPwr, BSTD_UHF_ID))
1042	{
1043	BDBG_MSG(("Power Up: UHF"));
1044	ulRegData = (BCHP_CLK_UHFR_CLK_PM_CTRL_DIS_ANA_UHFR_CLK_MASK \|
1045	BCHP_CLK_UHFR_CLK_PM_CTRL_DIS_DIGI_UHFR_CLK_MASK);
1046	BREG_AtomicUpdate32(pPwr->hRegister, BCHP_CLK_UHFR_CLK_PM_CTRL,ulRegData,0);
1047
1048	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_UHFR_GLBL_AUTOPD1);
1049	ulRegData &= ~BCHP_UHFR_GLBL_AUTOPD1_MANUAL_PD_MASK;
1050	ulRegData \|= BCHP_UHFR_GLBL_AUTOPD1_AUTO_PD_EN_MASK;
1051	BREG_Write32(pPwr->hRegister, BCHP_UHFR_GLBL_AUTOPD1, ulRegData);
1052	}
1053
1054
1055	/* Power Up Smartcard */
1056	if (BPWR_P_IsModuleChanging(pPwr, BSTD_SCD_ID))
1057	{
1058	BDBG_MSG(("Power Up: SCD"));
1059	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_SC_CTRL);
1060	ulRegData &= ~(BCHP_VCXO_CTL_MISC_SC_CTRL_POWERDOWN_MASK \|
1061	BCHP_VCXO_CTL_MISC_SC_CTRL_RESET_MASK);
1062	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_SC_CTRL, ulRegData);
1063
1064	ulRegData = ~BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_SC_PM_DIS_CHL_1);
1065	ulRegData &= BCHP_VCXO_CTL_MISC_SC_PM_DIS_CHL_1_DIS_CH_MASK;
1066	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_SC_PM_DIS_CHL_1, ulRegData);
1067
1068	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_SC_PM_CLOCK_ENA_1);
1069	ulRegData \|= BCHP_VCXO_CTL_MISC_SC_PM_CLOCK_ENA_1_CLOCK_ENA_MASK;
1070	BREG_Write32(pPwr->hRegister, BCHP_VCXO_CTL_MISC_SC_PM_CLOCK_ENA_1, ulRegData);
1071
1072	ulRegData = (BCHP_CLK_MISC_SMARTCARD_CLOCK_0_SOURCE_SEL_MASK \|
1073	BCHP_CLK_MISC_SMARTCARD_CLOCK_1_SOURCE_SEL_MASK);
1074	BREG_AtomicUpdate32(pPwr->hRegister, BCHP_CLK_MISC,ulRegData,0);
1075	}
1076
1077	/* Power Up 1394 */
1078	if (BPWR_P_IsModuleChanging(pPwr, BSTD_TNF_ID))
1079	{
1080	BDBG_MSG(("Power Up: 1394"));
1081	#if 0
1082	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_AVLINK_AVRX_LPS_LINK_ON);
1083	ulRegData &= ~BCHP_AVLINK_AVRX_LPS_LINK_ON_lps_Disable_MASK;
1084	BREG_Write32(pPwr->hRegister, BCHP_AVLINK_AVRX_LPS_LINK_ON, ulRegData);
1085	#endif
1086
1087	ulRegData = (BCHP_CLK_TOP1394_CLK_PM_CTRL_DIS_1394_PM_27M_CLK_MASK \|
1088	BCHP_CLK_TOP1394_CLK_PM_CTRL_DIS_108M_CLK_MASK \|
1089	BCHP_CLK_TOP1394_CLK_PM_CTRL_DIS_216M_CLK_MASK);
1090	BREG_AtomicUpdate32(pPwr->hRegister, BCHP_CLK_TOP1394_CLK_PM_CTRL,ulRegData,0);
1091
1092	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_AVLINK_PHY_PHY_PM_CTRL);
1093	ulRegData \|= ~(BCHP_AVLINK_PHY_PHY_PM_CTRL_BIAS_POWER_DOWN_MASK \|
1094	BCHP_AVLINK_PHY_PHY_PM_CTRL_DS_POWER_DOWN_MASK \|
1095	BCHP_AVLINK_PHY_PHY_PM_CTRL_PLL_POWER_DOWN_MASK);
1096	BREG_Write32(pPwr->hRegister, BCHP_AVLINK_PHY_PHY_PM_CTRL, ulRegData);
1097	}
1098
1099	/* Power Up HDMI */
1100	if (BPWR_P_IsModuleChanging(pPwr, BSTD_HDM_ID))
1101	{
1102	BDBG_MSG(("Power Up: HDM"));
1103	/* Power up HDMI clocks */
1104	ulRegData = (BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_VEC_216M_CLK_MASK \|
1105	BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_MAX_250M_CLK_MASK \|
1106	BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_HDMI_27M_CLK_MASK \|
1107	BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_108M_CLK_MASK \|
1108	BCHP_CLK_DVP_HT_CLK_PM_CTRL_DIS_216M_CLK_MASK);
1109
1110	BREG_AtomicUpdate32(pPwr->hRegister, BCHP_CLK_DVP_HT_CLK_PM_CTRL,ulRegData,0);
1111
1112	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_2);
1113	ulRegData &= ~BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_2_I_PWRDN_CH2_MASK;
1114	BREG_Write32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_2, ulRegData);
1115
1116	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_1);
1117	ulRegData &= ~BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_1_I_PWR_DN_CH1_MASK;
1118	BREG_Write32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_1, ulRegData);
1119
1120	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_0);
1121	ulRegData &= ~BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_0_RND_PWRDN_MASK;
1122	BREG_Write32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_CTL_0, ulRegData);
1123
1124	ulRegData = BREG_Read32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL);
1125	ulRegData &= ~(BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_0_PWRDN_MASK \|
1126	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_1_PWRDN_MASK \|
1127	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_2_PWRDN_MASK \|
1128	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_CK_PWRDN_MASK \|
1129	/* BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_PWRDN_CEC_MASK \| 4 */
1130	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_PLL_PWRDN_MASK \|
1131	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_REF_COMP_PWRDN_MASK \|
1132	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_PWRDN_BG_MASK \|
1133	/* BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_PWRDN_REFAMP_MASK \| 8 */
1134	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_D_RESET_MASK \|
1135	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_A_RESET_MASK \|
1136	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_CK_RESET_MASK \|
1137	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_2_RESET_MASK \|
1138	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_1_RESET_MASK \|
1139	BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL_TX_0_RESET_MASK);
1140	BREG_Write32(pPwr->hRegister, BCHP_HDMI_TX_PHY_HDMI_TX_PHY_RESET_CTL, ulRegData);
1141	}
1142	}
1143
1144	BDBG_LEAVE(BPWR_P_SetPowerMode);
1145	#else
1146	BSTD_UNUSED(pPwr);
1147	#endif
1148	return eStatus;
1149	}
1150
1151	/* End of file */
1152

Note: See TracBrowser for help on using the repository browser.

Context Navigation

source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/pwr/7552/bpwr_priv.c

Download in other formats: