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bvbi_cgmsd.c

Last change on this file was 2, checked in by phkim, 11 years ago

1.phkim

revision copy newcon3sk r27

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1	/***************************************************************************
2	* Copyright (c) 2003-2008, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bvbi_cgmsd.c $
11	* $brcm_Revision: Hydra_Software_Devel/1 $
12	* $brcm_Date: 12/3/08 8:00p $
13	*
14	* Module Description:
15	*
16	* Revision History:
17	*
18	* $brcm_Log: /magnum/portinginterface/vbi/7400/bvbi_cgmsd.c $
19	*
20	* Hydra_Software_Devel/1 12/3/08 8:00p darnstein
21	* PR45819:
22	*
23	***************************************************************************/
24
25	#include "bstd.h" /* standard types */
26	#include "bdbg.h" /* Dbglib */
27	#include "bkni.h" /* For critical sections */
28	#include "bvbi.h" /* VBI processing, this module. */
29	#include "bvbi_priv.h" /* VBI internal data structures */
30	#if (BVBI_P_NUM_VDEC >= 1)
31	#include "bchp_cgmsd_0.h" /* RDB info for CGMSD core */
32	#endif
33	#if (BVBI_P_NUM_VDEC >= 2)
34	#include "bchp_cgmsd_1.h" /* RDB info for CGMSD core */
35	#endif
36
37	BDBG_MODULE(BVBI);
38
39
40	/***************************************************************************
41	* Forward declarations of static (private) functions
42	***************************************************************************/
43
44
45	/***************************************************************************
46	* Implementation of supporting CGMS functions that are not in API
47	***************************************************************************/
48
49	#if (BVBI_P_NUM_VDEC >= 1) / { /
50
51	void BVBI_P_CGMS_Dec_Init (BREG_Handle hReg, uint32_t ulCoreOffset)
52	{
53	uint32_t ulReg = 0x0;
54
55	BDBG_ENTER(BVBI_P_CGMS_Dec_Init);
56
57	BKNI_EnterCriticalSection();
58
59	BREG_Write32 (hReg, BCHP_CGMSD_0_Reset + ulCoreOffset, ulReg);
60
61	BKNI_LeaveCriticalSection();
62
63	BDBG_LEAVE(BVBI_P_CGMS_Dec_Init);
64	}
65
66	BERR_Code BVBI_P_CGMS_Dec_Program (
67	BREG_Handle hReg,
68	BAVC_SourceId eSource,
69	bool bActive,
70	BFMT_VideoFmt eVideoFormat)
71	{
72	uint32_t H_Top_Format;
73	uint32_t H_Top_Control;
74	uint32_t H_Bot_Format;
75	uint32_t H_Bot_Control;
76	uint32_t H_Status;
77	uint32_t ulTop_FormatReg;
78	uint32_t ulTop_ControlReg;
79	uint32_t ulBot_FormatReg;
80	uint32_t ulBot_ControlReg;
81	uint32_t ulStatusReg;
82	uint32_t idle_width, num_samples, hsync_delay;
83	int top_line;
84	int bot_line;
85	BERR_Code eErr = BERR_SUCCESS;
86
87	BDBG_ENTER(BVBI_P_CGMS_Dec_Program);
88
89	/* Figure out which decoder core to use */
90	switch (eSource)
91	{
92	case BAVC_SourceId_eVdec0:
93	H_Top_Format = BCHP_CGMSD_0_Top_Format;
94	H_Top_Control = BCHP_CGMSD_0_Top_Control;
95	H_Bot_Format = BCHP_CGMSD_0_Bot_Format;
96	H_Bot_Control = BCHP_CGMSD_0_Bot_Control;
97	H_Status = BCHP_CGMSD_0_Status;
98	break;
99	#if (BVBI_P_NUM_VDEC > 1)
100	case BAVC_SourceId_eVdec1:
101	H_Top_Format = BCHP_CGMSD_1_Top_Format;
102	H_Top_Control = BCHP_CGMSD_1_Top_Control;
103	H_Bot_Format = BCHP_CGMSD_1_Bot_Format;
104	H_Bot_Control = BCHP_CGMSD_1_Bot_Control;
105	H_Status = BCHP_CGMSD_1_Status;
106	break;
107	#endif
108	default:
109	/* This should never happen! This parameter was checked by
110	BVBI_Decode_Create() */
111	BDBG_LEAVE(BVBI_P_CGMS_Dec_Program);
112	return BERR_TRACE(BERR_INVALID_PARAMETER);
113	break;
114	}
115
116	BKNI_EnterCriticalSection();
117
118	/* get the control registers' values */
119	ulTop_ControlReg = BREG_Read32 (hReg, H_Top_Control);
120	ulBot_ControlReg = BREG_Read32 (hReg, H_Bot_Control);
121
122	/* If decoding is to be enabled */
123	if (bActive)
124	{
125	/* Select video line */
126	switch (eVideoFormat)
127	{
128	case BFMT_VideoFmt_eNTSC:
129	case BFMT_VideoFmt_eNTSC_J:
130	top_line = 20;
131	bot_line = 20;
132	idle_width = 304;
133	num_samples = 22;
134	hsync_delay = 0x49;
135	break;
136
137	/* TODO: The idle_width, hsync_delay, and num_samples settings are
138	* ---- not known for HTDV formats!
139	*/
140
141	#ifdef BVBI_P_HAS_COMPON_INPUT
142	case BFMT_VideoFmt_e1080i:
143	top_line = 19;
144	bot_line = 19;
145	idle_width = 392;
146	num_samples = 28;
147	hsync_delay = 0x89;
148	break;
149
150	case BFMT_VideoFmt_e1080i_50Hz:
151	top_line = 19;
152	bot_line = 19;
153	idle_width = 392;
154	num_samples = 28;
155	hsync_delay = 0x89;
156	break;
157
158	case BFMT_VideoFmt_e720p:
159	/* Something is wrong with VDEC front end? */
160	top_line = 23;
161	bot_line = 0;
162	idle_width = 296;
163	num_samples = 21;
164	hsync_delay = 0x8;
165	break;
166
167	case BFMT_VideoFmt_e720p_50Hz:
168	/* Something is wrong with VDEC front end? */
169	top_line = 23;
170	bot_line = 0;
171	idle_width = 296;
172	num_samples = 21;
173	hsync_delay = 0x8;
174	break;
175
176	case BFMT_VideoFmt_e480p:
177	/* Something is wrong with VDEC front end? */
178	/* top_line = 41; */
179	top_line = 40;
180	bot_line = 0;
181	idle_width = 264;
182	num_samples = 19;
183	/* This is optimal for 3563-D0. Other chipsets? */
184	hsync_delay = 0x51;
185	break;
186	#endif
187
188	default:
189	eErr = BERR_TRACE (BVBI_ERR_VFMT_CONFLICT);
190	goto done;
191	}
192
193	/* Top control register programming */
194	ulTop_ControlReg &= ~(
195	BCHP_MASK ( CGMSD_0_Top_Control, THRESHOLD ) \|
196	BCHP_MASK ( CGMSD_0_Top_Control, THRESHOLD_TECHNIQUE ) \|
197	BCHP_MASK ( CGMSD_0_Top_Control, BLANK_LEVEL ) \|
198	BCHP_MASK ( CGMSD_0_Top_Control, INERTIA ) \|
199	BCHP_MASK ( CGMSD_0_Top_Control, RAW_COUNT ) \|
200	BCHP_MASK ( CGMSD_0_Top_Control, VBI_LINE ) \|
201	BCHP_MASK ( CGMSD_0_Top_Control, BIT_ORDER ) \|
202	BCHP_MASK ( CGMSD_0_Top_Control, ENABLE ) );
203	ulTop_ControlReg \|= (
204	BCHP_FIELD_DATA ( CGMSD_0_Top_Control, THRESHOLD, 7 ) \|
205	BCHP_FIELD_ENUM ( CGMSD_0_Top_Control, THRESHOLD_TECHNIQUE, AUTO ) \|
206	BCHP_FIELD_DATA ( CGMSD_0_Top_Control, BLANK_LEVEL, 0x17 ) \|
207	BCHP_FIELD_ENUM ( CGMSD_0_Top_Control, INERTIA, NOISE_FREE ) \|
208	BCHP_FIELD_DATA ( CGMSD_0_Top_Control, RAW_COUNT, 13 ) \|
209	BCHP_FIELD_DATA ( CGMSD_0_Top_Control, VBI_LINE, top_line ) \|
210	BCHP_FIELD_ENUM ( CGMSD_0_Top_Control, BIT_ORDER, LSB_FIRST ) \|
211	BCHP_FIELD_ENUM ( CGMSD_0_Top_Control, ENABLE, CGMSA ) );
212
213	/* Bottom control register programming */
214	ulBot_ControlReg &= ~(
215	BCHP_MASK ( CGMSD_0_Bot_Control, THRESHOLD ) \|
216	BCHP_MASK ( CGMSD_0_Bot_Control, THRESHOLD_TECHNIQUE ) \|
217	BCHP_MASK ( CGMSD_0_Bot_Control, BLANK_LEVEL ) \|
218	BCHP_MASK ( CGMSD_0_Bot_Control, INERTIA ) \|
219	BCHP_MASK ( CGMSD_0_Bot_Control, RAW_COUNT ) \|
220	BCHP_MASK ( CGMSD_0_Bot_Control, VBI_LINE ) \|
221	BCHP_MASK ( CGMSD_0_Bot_Control, BIT_ORDER ) \|
222	BCHP_MASK ( CGMSD_0_Bot_Control, ENABLE ) );
223	ulBot_ControlReg \|= (
224	BCHP_FIELD_DATA ( CGMSD_0_Bot_Control, THRESHOLD, 7 ) \|
225	BCHP_FIELD_ENUM ( CGMSD_0_Bot_Control, THRESHOLD_TECHNIQUE, AUTO ) \|
226	BCHP_FIELD_DATA ( CGMSD_0_Bot_Control, BLANK_LEVEL, 0x17 ) \|
227	BCHP_FIELD_ENUM ( CGMSD_0_Bot_Control, INERTIA, NOISE_FREE ) \|
228	BCHP_FIELD_DATA ( CGMSD_0_Bot_Control, RAW_COUNT, 13 ) \|
229	BCHP_FIELD_DATA ( CGMSD_0_Bot_Control, VBI_LINE, bot_line ) \|
230	BCHP_FIELD_ENUM ( CGMSD_0_Bot_Control, BIT_ORDER, LSB_FIRST ) \|
231	BCHP_FIELD_ENUM ( CGMSD_0_Bot_Control, ENABLE, CGMSA ) );
232
233	/* Program and write top format register value */
234	ulTop_FormatReg = BREG_Read32 (hReg, H_Top_Format);
235	ulTop_FormatReg &= ~(
236	BCHP_MASK ( CGMSD_0_Top_Format, IDLE_WIDTH ) \|
237	BCHP_MASK ( CGMSD_0_Top_Format, NUM_SAMPLES ) \|
238	BCHP_MASK ( CGMSD_0_Top_Format, HSYNC_DELAY ) \|
239	BCHP_MASK ( CGMSD_0_Top_Format, HSYNC_EDGE ) );
240	ulTop_FormatReg \|= (
241	BCHP_FIELD_DATA ( CGMSD_0_Top_Format, IDLE_WIDTH, idle_width ) \|
242	BCHP_FIELD_DATA ( CGMSD_0_Top_Format, NUM_SAMPLES, num_samples ) \|
243	BCHP_FIELD_DATA ( CGMSD_0_Top_Format, HSYNC_DELAY, hsync_delay ) \|
244	BCHP_FIELD_ENUM ( CGMSD_0_Top_Format, HSYNC_EDGE, FALLING_EDGE ) );
245	BREG_Write32 ( hReg, H_Top_Format, ulTop_FormatReg );
246
247	/* Program and write bottom format register value */
248	ulBot_FormatReg = BREG_Read32 (hReg, H_Bot_Format);
249	ulBot_FormatReg &= ~(
250	BCHP_MASK ( CGMSD_0_Bot_Format, IDLE_WIDTH ) \|
251	BCHP_MASK ( CGMSD_0_Bot_Format, NUM_SAMPLES ) \|
252	BCHP_MASK ( CGMSD_0_Bot_Format, HSYNC_DELAY ) \|
253	BCHP_MASK ( CGMSD_0_Bot_Format, HSYNC_EDGE ) );
254	ulBot_FormatReg \|= (
255	BCHP_FIELD_DATA ( CGMSD_0_Bot_Format, IDLE_WIDTH, idle_width ) \|
256	BCHP_FIELD_DATA ( CGMSD_0_Bot_Format, NUM_SAMPLES, num_samples ) \|
257	BCHP_FIELD_DATA ( CGMSD_0_Bot_Format, HSYNC_DELAY, hsync_delay ) \|
258	BCHP_FIELD_ENUM ( CGMSD_0_Bot_Format, HSYNC_EDGE, FALLING_EDGE ) );
259	BREG_Write32 ( hReg, H_Bot_Format, ulBot_FormatReg );
260
261	}
262	else /* Decoding is not to be enabled */
263	{
264	/* Disable decoding in top field */
265	ulTop_ControlReg &=
266	~BCHP_MASK ( CGMSD_0_Top_Control, ENABLE );
267	ulTop_ControlReg \|=
268	BCHP_FIELD_ENUM ( CGMSD_0_Top_Control, ENABLE, DISABLED );
269
270	/* Disable decoding in bottom field */
271	ulBot_ControlReg &=
272	~BCHP_MASK ( CGMSD_0_Bot_Control, ENABLE );
273	ulBot_ControlReg \|=
274	BCHP_FIELD_ENUM ( CGMSD_0_Bot_Control, ENABLE, DISABLED );
275	}
276
277	/* Write top field control register */
278	BREG_Write32 ( hReg, H_Top_Control, ulTop_ControlReg );
279
280	/* Write bottom field control register */
281	BREG_Write32 ( hReg, H_Bot_Control, ulBot_ControlReg );
282
283	/* Clear status bits */
284	ulStatusReg = BREG_Read32 ( hReg, H_Status );
285	ulStatusReg &= ~(
286	BCHP_MASK ( CGMSD_0_Status, DATA_OVERRUN ) \|
287	BCHP_MASK ( CGMSD_0_Status, BOT_CRC ) \|
288	BCHP_MASK ( CGMSD_0_Status, TOP_CRC ) \|
289	BCHP_MASK ( CGMSD_0_Status, BOT_CHANGE ) \|
290	BCHP_MASK ( CGMSD_0_Status, TOP_CHANGE ) \|
291	BCHP_MASK ( CGMSD_0_Status, BOT_DATA ) \|
292	BCHP_MASK ( CGMSD_0_Status, TOP_DATA ) );
293	ulStatusReg \|= (
294	BCHP_FIELD_DATA ( CGMSD_0_Status, DATA_OVERRUN, 0x1 ) \|
295	BCHP_FIELD_DATA ( CGMSD_0_Status, BOT_CRC, 0x1 ) \|
296	BCHP_FIELD_DATA ( CGMSD_0_Status, TOP_CRC, 0x1 ) \|
297	BCHP_FIELD_DATA ( CGMSD_0_Status, BOT_CHANGE, 0x1 ) \|
298	BCHP_FIELD_DATA ( CGMSD_0_Status, TOP_CHANGE, 0x1 ) \|
299	BCHP_FIELD_DATA ( CGMSD_0_Status, BOT_DATA, 0x1 ) \|
300	BCHP_FIELD_DATA ( CGMSD_0_Status, TOP_DATA, 0x1 ) );
301	BREG_Write32 ( hReg, H_Status, ulStatusReg );
302
303	done:
304	BKNI_LeaveCriticalSection();
305
306	BDBG_LEAVE(BVBI_P_CGMS_Dec_Program);
307	return eErr;
308	}
309
310
311	uint32_t BVBI_P_CGMS_Decode_Data_isr (
312	BREG_Handle hReg,
313	BAVC_SourceId eSource,
314	BAVC_Polarity polarity,
315	uint32_t *pulData)
316	{
317	/*
318	Programming note: the implementation here assumes that the bitfield layout
319	within registers is the same for all CGMS decoder cores in the chip.
320
321	If a chip is built that has multiple CGMS decoder cores that are not
322	identical, then this routine will have to be redesigned.
323	*/
324	uint32_t H_Top_Data;
325	uint32_t H_Bot_Data;
326	uint32_t H_Status;
327	uint32_t ulStatusReg;
328	uint32_t ulStatusReg2;
329	uint32_t ulDataReg = 0;
330	uint32_t ulErrInfo = 0;
331
332	BDBG_ENTER(BVBI_P_CGMS_Decode_Data_isr);
333	/* Figure out which decoder core to use */
334	switch (eSource)
335	{
336	case BAVC_SourceId_eVdec0:
337	H_Top_Data = BCHP_CGMSD_0_Top_Data;
338	H_Bot_Data = BCHP_CGMSD_0_Bot_Data;
339	H_Status = BCHP_CGMSD_0_Status;
340	break;
341	#if (BVBI_P_NUM_VDEC > 1)
342	case BAVC_SourceId_eVdec1:
343	H_Top_Data = BCHP_CGMSD_1_Top_Data;
344	H_Bot_Data = BCHP_CGMSD_1_Bot_Data;
345	H_Status = BCHP_CGMSD_1_Status;
346	break;
347	#endif
348	default:
349	/* This should never happen! This parameter was checked by
350	BVBI_Decode_Create() */
351	BDBG_LEAVE(BVBI_P_CGMS_Decode_Data_isr);
352	return (-1);
353	break;
354	}
355
356	/* Pull status info out of the hardware */
357	ulStatusReg = BREG_Read32 ( hReg, H_Status );
358
359	/*
360	Programming note:
361	Because of PR 10115 on 7038 A0/B0 hardware, I can't be very selective about
362	how I clear hardware bits. I have to clear all conditions as they occur.
363
364	This scheme for clearing status bits requires that TOP field CGMS data be
365	processed by this function immediately after the TOP field VBI lines are
366	received in hardware. Fortunately, this is the alternative that most
367	users would prefer.
368	*/
369
370	/* If top field */
371	if ((polarity == BAVC_Polarity_eTopField) \|\|
372	(polarity == BAVC_Polarity_eFrame ) )
373	{
374	/* check to see if we found data in top field */
375	if ( BCHP_GET_FIELD_DATA (ulStatusReg, CGMSD_0_Status, TOP_DATA) )
376	{
377	/* read the data */
378	ulDataReg = BREG_Read32 ( hReg, H_Top_Data );
379
380	/* provide the decoded data to higher level software */
381	*pulData = ulDataReg;
382	}
383	else
384	{
385	/* Failed to find top data in top field, so complain */
386	ulErrInfo \|= BVBI_LINE_ERROR_CGMS_NODATA;
387	}
388
389	/* Inform of CRC error */
390	if ( BCHP_GET_FIELD_DATA (ulStatusReg, CGMSD_0_Status, TOP_CRC) != 0 )
391	{
392	ulErrInfo \|= BVBI_LINE_ERROR_CGMS_CRC;
393	}
394
395	ulStatusReg2 = ulStatusReg & (
396	BCHP_MASK (CGMSD_0_Status, DATA_OVERRUN) \|
397	BCHP_MASK (CGMSD_0_Status, TOP_CRC) \|
398	BCHP_MASK (CGMSD_0_Status, TOP_CHANGE) \|
399	BCHP_MASK (CGMSD_0_Status, TOP_DATA) );
400	}
401	else /* Bottom field */
402	{
403	/* check to see if we found data in bottom field */
404	if ( BCHP_GET_FIELD_DATA (ulStatusReg, CGMSD_0_Status, BOT_DATA) )
405	{
406	/* read the data */
407	ulDataReg = BREG_Read32 ( hReg, H_Bot_Data );
408
409	/* provide the decoded data to higher level software */
410	*pulData = ulDataReg;
411	}
412	else
413	{
414	/* Failed to find data in bottom field, so complain */
415	ulErrInfo \|= BVBI_LINE_ERROR_CGMS_NODATA;
416	}
417
418	/* Inform of CRC error */
419	if ( BCHP_GET_FIELD_DATA (ulStatusReg, CGMSD_0_Status, BOT_CRC) != 0 )
420	{
421	ulErrInfo \|= BVBI_LINE_ERROR_CGMS_CRC;
422	}
423	ulStatusReg2 = ulStatusReg & (
424	BCHP_MASK (CGMSD_0_Status, DATA_OVERRUN) \|
425	BCHP_MASK (CGMSD_0_Status, BOT_CRC) \|
426	BCHP_MASK (CGMSD_0_Status, BOT_CHANGE) \|
427	BCHP_MASK (CGMSD_0_Status, BOT_DATA) );
428	}
429
430	/* Inform of data overrun error */
431	if ( BCHP_GET_FIELD_DATA (
432	ulStatusReg, CGMSD_0_Status, DATA_OVERRUN) != 0 )
433	{
434	ulErrInfo \|= BVBI_LINE_ERROR_CGMS_OVERRUN;
435	}
436
437	/* Finally, clear status in hardware. */
438	BREG_Write32 ( hReg, H_Status, ulStatusReg2 );
439
440	BDBG_LEAVE(BVBI_P_CGMS_Decode_Data_isr);
441	return ulErrInfo;
442	}
443
444	#endif / } (BVBI_P_NUM_VDEC >= 1) /
445
446
447	/***************************************************************************
448	* Static (private) functions
449	***************************************************************************/

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source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/vbi/7552/bvbi_cgmsd.c

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