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bvbi_in656.c

Last change on this file was 2, checked in by phkim, 11 years ago

1.phkim

revision copy newcon3sk r27

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1	/***************************************************************************
2	* Copyright (c) 2003-2012, Broadcom Corporation
3	* All Rights Reserved
4	* Confidential Property of Broadcom Corporation
5	*
6	* THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
7	* AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR
8	* EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
9	*
10	* $brcm_Workfile: bvbi_in656.c $
11	* $brcm_Revision: Hydra_Software_Devel/6 $
12	* $brcm_Date: 2/20/12 2:53p $
13	*
14	* Module Description:
15	*
16	* This module provides access to the IN656 core for the VBI porting
17	* interface (BVBI). This module is private to BVBI.
18	*
19	* Revision History:
20	*
21	* $brcm_Log: /magnum/portinginterface/vbi/7420/bvbi_in656.c $
22	*
23	* Hydra_Software_Devel/6 2/20/12 2:53p darnstein
24	* SW7425-2434: more detail in error messages.
25	*
26	* Hydra_Software_Devel/5 2/20/12 12:57p darnstein
27	* SW7425-2434: when an unsupported video format is entered, the BDBG
28	* error message should be informative.
29	*
30	* Hydra_Software_Devel/4 12/21/09 7:00p darnstein
31	* SW7550-120: Add support for SECAM variants.
32	*
33	* Hydra_Software_Devel/3 8/26/09 1:33p darnstein
34	* SW7125-17: Integrate recent improvements from 7405 software.
35	*
36	* Hydra_Software_Devel/2 12/4/08 6:08p darnstein
37	* PR45819: 7420 software will now compile, but not link.
38	*
39	* Hydra_Software_Devel/1 12/4/08 3:00p darnstein
40	* PR45819: copy over from 7400 branch.
41	*
42	* Hydra_Software_Devel/2 12/3/08 7:56p darnstein
43	* PR45819: New, more modular form of most BVBI source files.
44	*
45	* Hydra_Software_Devel/18 4/2/08 7:55p darnstein
46	* PR38956: VBI software compiles now.
47	*
48	* Hydra_Software_Devel/17 10/31/07 3:51p darnstein
49	* PR34528: BVBI is ready for testing on 7325.
50	*
51	* Hydra_Software_Devel/16 4/20/07 3:36p darnstein
52	* PR29723: Compilation for 7405 chipset.
53	*
54	* Hydra_Software_Devel/15 1/2/07 4:20p darnstein
55	* PR26872: Mechanically add SECAM to all cases where PAL formats are
56	* accepted.
57	*
58	* Hydra_Software_Devel/14 8/31/06 2:10p darnstein
59	* PR23869: clean up the handling of multiple VECs and VDECs.
60	*
61	* Hydra_Software_Devel/13 8/18/06 6:51p darnstein
62	* PR23178: basic compile on 93563 is possible.
63	*
64	* Hydra_Software_Devel/12 8/15/06 1:08p darnstein
65	* PR23178: Include bchp_in656.h when needed.
66	*
67	* Hydra_Software_Devel/11 4/25/06 1:21p darnstein
68	* PR18010: silence compiler warnings for some chipsets. Reported by
69	* DLwin.
70	*
71	* Hydra_Software_Devel/10 9/23/05 2:47p darnstein
72	* PR13750: Proper use of BERR_TRACE and BERR_CODEs.
73	*
74	* Hydra_Software_Devel/9 9/19/05 2:56p darnstein
75	* PR17151: Check for chip name where needed. Also, convert to new scheme
76	* for testing chip revisions (BCHP_VER).
77	*
78	* Hydra_Software_Devel/8 7/7/05 3:34p darnstein
79	* PR 16008: The default settings struct for BVBI_Open() now allows the
80	* user to choose a buffer size for capturing ancillary data packets in
81	* incoming ITU-R 656 digital video.
82	*
83	* Hydra_Software_Devel/7 7/6/05 5:55p darnstein
84	* PR 16008: Input of closed caption data in SAA7113 ancillary data
85	* packets of ITU-R 656 digital video has been confirmed. SAA7114 input
86	* almost certainly needs some debugging though.
87	*
88	* Hydra_Software_Devel/6 5/18/05 6:04p agin
89	* PR14720: B2, C1, C2 compilation support.
90	*
91	* Hydra_Software_Devel/5 5/18/05 5:47p darnstein
92	* PR 11440: Progress towards ITU-R 656 input of VBI data.
93	*
94	* Hydra_Software_Devel/4 4/13/05 8:38p darnstein
95	* PR 14720: Modify #defines to account for 7038-B2 and 7038-C0 chip
96	* revisions. Compiles OK now. But untested!
97	*
98	* Hydra_Software_Devel/3 3/11/05 3:49p darnstein
99	* PR 14426: use new _0 names for VDEC cores.
100	*
101	* Hydra_Software_Devel/2 1/5/05 4:28p jasonh
102	* PR 13700: Fixed VBI compile issues for 7038 C0.
103	*
104	* Hydra_Software_Devel/1 7/21/04 2:40p darnstein
105	* PR9080: Finish merging ITU-R 656 software to main branch.
106	*
107	* I656/2 7/21/04 11:34a darnstein
108	* Fix up revision history (Clearcase).
109	*
110	***************************************************************************/
111
112	#include "bstd.h" /* standard types */
113	#include "bdbg.h" /* Dbglib */
114	#include "bvbi.h" /* VBI processing, this module. */
115	#include "bvbi_priv.h" /* VBI internal data structures */
116
117	#if (BVBI_P_NUM_IN656 >= 1) / { /
118
119	#include "bchp_in656_0.h" /* RDB info for IN656 registers */
120	#if (BVBI_P_NUM_IN656 >= 2)
121	#include "bchp_in656_1.h" /* RDB info for IN656 registers */
122	#endif
123
124	BDBG_MODULE(BVBI);
125
126
127	/***************************************************************************
128	* Forward declarations of static (private) functions
129	***************************************************************************/
130	static void BVBI_P_IN656_Dec_Init (BREG_Handle hReg, uint32_t ulCoreOffset);
131
132
133	/***************************************************************************
134	* Implementation of "BVBI_" API functions
135	***************************************************************************/
136
137
138	/***************************************************************************
139	* Implementation of supporting VBI_DEC functions that are not in API
140	***************************************************************************/
141
142
143	BERR_Code BVBI_P_IN656_Init( BVBI_P_Handle *pVbi )
144	{
145	uint32_t ulCoreOffset;
146
147	BDBG_ENTER(BVBI_P_IN656_Init);
148
149	/* Initialize IN656 core */
150	ulCoreOffset = 0x0;
151	BVBI_P_IN656_Dec_Init (pVbi->hReg, ulCoreOffset);
152	#if (BVBI_P_NUM_IN656 >= 2)
153	ulCoreOffset = BCHP_IN656_1_REV_ID - BCHP_IN656_0_REV_ID;
154	BVBI_P_IN656_Dec_Init (pVbi->hReg, ulCoreOffset);
155	#endif
156
157	BDBG_LEAVE(BVBI_P_IN656_Init);
158	return BERR_SUCCESS;
159	}
160
161
162	BERR_Code BVBI_P_IN656_Dec_Program (
163	BREG_Handle hReg,
164	BMEM_Handle hMem,
165	BAVC_SourceId eSource,
166	bool bActive,
167	BVBI_656Fmt anci656Fmt,
168	BVBI_P_SMPTE291Moptions* pMoptions,
169	BFMT_VideoFmt eVideoFormat,
170	uint8_t* topData,
171	uint8_t* botData)
172	{
173	/*
174	Programming note: the implementation here assumes that the bitfield layout
175	within registers is the same for all IN656 cores in the chip.
176
177	If a chip is built that has multiple IN656 decoder cores that are not
178	identical, then this routine will have to be redesigned.
179	*/
180	uint32_t offset;
181	uint32_t ulOffset;
182	uint32_t ulReg;
183	bool isPal;
184	BERR_Code eErr;
185
186	BDBG_ENTER(BVBI_P_IN656_Dec_Program);
187
188	/* Figure out which decoder core to use */
189	switch (eSource)
190	{
191	case BAVC_SourceId_e656In0:
192	ulOffset = 0;
193	break;
194	#if (BVBI_P_NUM_VDEC > 1)
195	case BAVC_SourceId_e656In1:
196	ulOffset = BCHP_IN656_1_REV_ID - BCHP_IN656_0_REV_ID;
197	break;
198	#endif
199	default:
200	/* This should never happen! This parameter was checked by
201	BVBI_Decode_Create() */
202	BDBG_LEAVE(BVBI_P_IN656_Dec_Program);
203	return BERR_TRACE (BERR_INVALID_PARAMETER);
204	break;
205	}
206
207	/* Determine whether PAL or NTSC */
208	switch (eVideoFormat)
209	{
210	case BFMT_VideoFmt_eNTSC:
211	case BFMT_VideoFmt_eNTSC_J:
212	case BFMT_VideoFmt_e1080i:
213	case BFMT_VideoFmt_e720p:
214	case BFMT_VideoFmt_e480p:
215	isPal = false;
216	break;
217
218	case BFMT_VideoFmt_ePAL_B:
219	case BFMT_VideoFmt_ePAL_B1:
220	case BFMT_VideoFmt_ePAL_D:
221	case BFMT_VideoFmt_ePAL_D1:
222	case BFMT_VideoFmt_ePAL_G:
223	case BFMT_VideoFmt_ePAL_H:
224	case BFMT_VideoFmt_ePAL_K:
225	case BFMT_VideoFmt_ePAL_I:
226	case BFMT_VideoFmt_ePAL_M:
227	case BFMT_VideoFmt_ePAL_N:
228	case BFMT_VideoFmt_ePAL_NC:
229	case BFMT_VideoFmt_eSECAM_L:
230	case BFMT_VideoFmt_eSECAM_B:
231	case BFMT_VideoFmt_eSECAM_G:
232	case BFMT_VideoFmt_eSECAM_D:
233	case BFMT_VideoFmt_eSECAM_K:
234	case BFMT_VideoFmt_eSECAM_H:
235	case BFMT_VideoFmt_e1080i_50Hz:
236	case BFMT_VideoFmt_e720p_50Hz:
237	case BFMT_VideoFmt_e576p_50Hz:
238	isPal = true;
239	break;
240
241	default:
242	BDBG_LEAVE(BVBI_P_IN656_Dec_Program);
243	BDBG_ERR(("BVBI_IN656: video format %d not supported", eVideoFormat));
244	return BERR_TRACE (BERR_INVALID_PARAMETER);
245	break;
246	}
247
248	/* Program the encapsulation method */
249	ulReg = BREG_Read32 (hReg, BCHP_IN656_0_STRM_CNTRL + ulOffset);
250	ulReg &= ~(
251	BCHP_MASK (IN656_0_STRM_CNTRL, SMPTE_COUNT_TYPE) \|
252	BCHP_MASK (IN656_0_STRM_CNTRL, TEST) \|
253	BCHP_MASK (IN656_0_STRM_CNTRL, MODE_FP) \|
254	BCHP_MASK (IN656_0_STRM_CNTRL, VCNT_LAST) \|
255	BCHP_MASK (IN656_0_STRM_CNTRL, VBLANK) \|
256	BCHP_MASK (IN656_0_STRM_CNTRL, TYPE) \|
257	BCHP_MASK (IN656_0_STRM_CNTRL, ANCILLARY_WIN) \|
258	BCHP_MASK (IN656_0_STRM_CNTRL, ANCILLARY_PKT) );
259	switch (anci656Fmt)
260	{
261	case BVBI_656Fmt_SAA7113:
262	ulReg \|= BCHP_FIELD_ENUM (IN656_0_STRM_CNTRL, TYPE, SAA7113);
263	break;
264	case BVBI_656Fmt_SAA7114A:
265	ulReg \|= BCHP_FIELD_ENUM (IN656_0_STRM_CNTRL, TYPE, SAA7114A);
266	break;
267	case BVBI_656Fmt_SAA7114B:
268	ulReg \|= BCHP_FIELD_ENUM (IN656_0_STRM_CNTRL, TYPE, SAA7114B);
269	break;
270	case BVBI_656Fmt_SAA7114C:
271	ulReg \|= BCHP_FIELD_ENUM (IN656_0_STRM_CNTRL, TYPE, SAA7114C);
272	break;
273	case BVBI_656Fmt_SAA7115:
274	ulReg \|= BCHP_FIELD_ENUM (IN656_0_STRM_CNTRL, TYPE, SAA7115);
275	break;
276	case BVBI_656Fmt_SMPTE291:
277	ulReg \|= BCHP_FIELD_ENUM (IN656_0_STRM_CNTRL, TYPE, SMPTE291);
278	if (pMoptions->bBrokenDataCount)
279	{
280	ulReg \|=
281	BCHP_FIELD_ENUM (IN656_0_STRM_CNTRL, SMPTE_COUNT_TYPE, BYTE);
282	}
283	else
284	{
285	ulReg \|=
286	BCHP_FIELD_ENUM (IN656_0_STRM_CNTRL, SMPTE_COUNT_TYPE, DWORD);
287	}
288	break;
289	default:
290	BDBG_LEAVE(BVBI_P_IN656_Dec_Program);
291	return BERR_TRACE (BERR_INVALID_PARAMETER);
292	break;
293	}
294
295	/* Put in a reasonable value for other attributes */
296	/* TODO: use enums when RDB and headers are fixed. */
297	ulReg \|= BCHP_FIELD_ENUM (IN656_0_STRM_CNTRL, TEST, BUS_0);
298	ulReg \|= BCHP_FIELD_ENUM (IN656_0_STRM_CNTRL, MODE_FP, AUTO);
299	ulReg \|= BCHP_FIELD_DATA (IN656_0_STRM_CNTRL, VCNT_LAST, 0x22);
300	ulReg \|= BCHP_FIELD_DATA (IN656_0_STRM_CNTRL, VBLANK, 0);
301	ulReg \|= BCHP_FIELD_ENUM (IN656_0_STRM_CNTRL, DATA_MSB_POLARITY, ONE);
302	ulReg \|= BCHP_FIELD_ENUM (IN656_0_STRM_CNTRL, ANCILLARY_WIN, ENABLE);
303
304	/* Turn on or off */
305	/* TODO: use enums when RDB and headers are fixed. */
306	ulReg &= ~BCHP_MASK (IN656_0_STRM_CNTRL, ANCILLARY_PKT);
307	if (bActive)
308	ulReg \|= BCHP_FIELD_DATA (IN656_0_STRM_CNTRL, ANCILLARY_PKT, 1);
309	else
310	ulReg \|= BCHP_FIELD_DATA (IN656_0_STRM_CNTRL, ANCILLARY_PKT, 0);
311
312	/* Done with one register */
313	BREG_Write32 (hReg, BCHP_IN656_0_STRM_CNTRL + ulOffset, ulReg);
314
315	/* Program the window for ancillary packet acceptance */
316	ulReg = BREG_Read32 (hReg, BCHP_IN656_0_STRM_WIN + ulOffset);
317	ulReg &= ~(
318	BCHP_MASK (IN656_0_STRM_WIN, END ) \|
319	BCHP_MASK (IN656_0_STRM_WIN, START ) );
320	ulReg \|= BCHP_FIELD_DATA (IN656_0_STRM_WIN, START, 0x16A);
321	ulReg \|= BCHP_FIELD_DATA (IN656_0_STRM_WIN, END, 0x1AD);
322	/*
323	if (isPal)
324	{
325	ulReg \|= BCHP_FIELD_DATA (IN656_0_STRM_WIN, END, 432);
326	}
327	*/
328	BREG_Write32 (hReg, BCHP_IN656_0_STRM_WIN + ulOffset, ulReg);
329
330	/* Tell the hardware where to put ancillary data packets that it finds */
331	eErr = BERR_TRACE (BMEM_ConvertAddressToOffset (hMem, topData, &offset));
332	if (eErr != BERR_SUCCESS)
333	{
334	BDBG_LEAVE(BVBI_P_IN656_Dec_Program);
335	return eErr;
336	}
337	BREG_Write32 (hReg, BCHP_IN656_0_FLD_0_PTR + ulOffset, offset);
338	eErr = BERR_TRACE (BMEM_ConvertAddressToOffset (hMem, botData, &offset));
339	if (eErr != BERR_SUCCESS)
340	{
341	BDBG_LEAVE(BVBI_P_IN656_Dec_Program);
342	return eErr;
343	}
344	BREG_Write32 ( hReg, BCHP_IN656_0_FLD_1_PTR + ulOffset, offset);
345
346	BDBG_LEAVE(BVBI_P_IN656_Dec_Program);
347	return BERR_SUCCESS;
348	}
349
350	BERR_Code BVBI_P_IN656_Decode_Data_isr (
351	BREG_Handle hReg,
352	BAVC_SourceId eSource,
353	BAVC_Polarity polarity,
354	bool* bDataFound)
355	{
356	/*
357	Programming note: the implementation here assumes that the bitfield layout
358	within registers is the same for all IN656 cores in the chip.
359
360	If a chip is built that has multiple IN656 decoder cores that are not
361	identical, then this routine will have to be redesigned.
362	*/
363	uint32_t ulOffset;
364	uint32_t ulErrors;
365	uint32_t ulWriteComplete;
366	uint32_t ulWriteCompleteMask;
367	uint32_t ulReg;
368	BERR_Code eErr;
369
370	BDBG_ENTER(BVBI_P_IN656_Decode_Data_isr);
371
372	/* Figure out which decoder core to use */
373	switch (eSource)
374	{
375	case BAVC_SourceId_e656In0:
376	ulOffset = 0;
377	break;
378	#if (BVBI_P_NUM_VDEC > 1)
379	case BAVC_SourceId_e656In1:
380	ulOffset = BCHP_IN656_1_REV_ID - BCHP_IN656_0_REV_ID;
381	break;
382	#endif
383	default:
384	/* This should never happen! This parameter was checked by
385	BVBI_Decode_Create() */
386	*bDataFound = false;
387	BDBG_LEAVE(BVBI_P_IN656_Decode_Data_isr);
388	return BERR_TRACE (BERR_INVALID_PARAMETER);
389	break;
390	}
391
392	/* Choose top vs bottom field */
393	switch (polarity)
394	{
395	case BAVC_Polarity_eTopField:
396	ulWriteCompleteMask = BCHP_MASK (IN656_0_WRITE_COMPLETE, F0_COMPLETE);
397	break;
398	case BAVC_Polarity_eBotField:
399	ulWriteCompleteMask = BCHP_MASK (IN656_0_WRITE_COMPLETE, F1_COMPLETE);
400	break;
401	default:
402	*bDataFound = false;
403	BDBG_LEAVE(BVBI_P_IN656_Decode_Data_isr);
404	return BERR_TRACE (BERR_INVALID_PARAMETER);
405	break;
406	}
407
408	/* Check and clear error status */
409	ulReg = BREG_Read32 (hReg, BCHP_IN656_0_ERROR_STATUS + ulOffset);
410	ulErrors = ulReg & (
411	BCHP_MASK (IN656_0_ERROR_STATUS, FIFO_FULL ) \|
412	BCHP_MASK (IN656_0_ERROR_STATUS, BAD_AP_PREFIX) \|
413	BCHP_MASK (IN656_0_ERROR_STATUS, BAD_SAV ) );
414	BREG_Write32 (hReg, BCHP_IN656_0_ERROR_STATUS + ulOffset, ulErrors);
415
416	/* Check and clear capture status */
417	ulReg = BREG_Read32 (hReg, BCHP_IN656_0_WRITE_COMPLETE + ulOffset);
418	ulWriteComplete = ulReg & ulWriteCompleteMask;
419	BREG_Write32 (
420	hReg, BCHP_IN656_0_WRITE_COMPLETE + ulOffset, ulWriteComplete);
421	*bDataFound = ((ulErrors == 0) && (ulWriteComplete != 0));
422
423	BDBG_LEAVE(BVBI_P_IN656_Decode_Data_isr);
424	eErr = (ulErrors == 0) ? BERR_SUCCESS : BVBI_ERR_FIELD_BADDATA;
425
426	return eErr;
427	}
428
429	/***************************************************************************
430	* Static (private) functions
431	***************************************************************************/
432
433	/***************************************************************************
434	*
435	*/
436	static void BVBI_P_IN656_Dec_Init (BREG_Handle hReg, uint32_t ulCoreOffset)
437	{
438	uint32_t ulReg;
439
440	BDBG_ENTER(BVBI_P_IN656_Dec_Init);
441
442	/* Reset the core */
443	ulReg = 0;
444	#if (BCHP_CHIP == 7405) \|\| (BCHP_CHIP == 7325) \|\| (BCHP_CHIP == 7125)
445	/* TODO: hit the reset register when it gets into RDB. */
446	#else
447	/* TODO: apply new reset scheme if necessary. */
448	BREG_Write32 (hReg, BCHP_IN656_0_RESET + ulCoreOffset, ulReg);
449	#endif
450
451	/* Disable the action of the core */
452	/* TODO: use enums when RDB and headers are fixed. */
453	ulReg = BREG_Read32 (hReg, BCHP_IN656_0_STRM_CNTRL + ulCoreOffset);
454	ulReg &= ~BCHP_MASK (IN656_0_STRM_CNTRL, ANCILLARY_PKT);
455	ulReg \|= BCHP_FIELD_DATA (IN656_0_STRM_CNTRL, ANCILLARY_PKT, 0);
456	BREG_Write32 (hReg, BCHP_IN656_0_STRM_CNTRL + ulCoreOffset, ulReg);
457
458	BDBG_LEAVE(BVBI_P_IN656_Dec_Init);
459	}
460
461	#endif / } /
462
463	/* End of file */

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source: svn/trunk/newcon3bcm2_21bu/magnum/portinginterface/vbi/7552/bvbi_in656.c

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