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io.h @ 2

Last change on this file since 2 was 2, checked in by phkim, 11 years ago

1.phkim

revision copy newcon3sk r27

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1	/*
2	* This file is subject to the terms and conditions of the GNU General Public
3	* License. See the file "COPYING" in the main directory of this archive
4	* for more details.
5	*
6	* Copyright (C) 1994, 1995 Waldorf GmbH
7	* Copyright (C) 1994 - 2000 Ralf Baechle
8	* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9	* Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
10	* Author: Maciej W. Rozycki <macro@mips.com>
11	*/
12	#ifndef _ASM_IO_H
13	#define _ASM_IO_H
14
15	#include <linux/kernel.h>
16	#include <linux/types.h>
17
18	#include <asm/addrspace.h>
19	#include <asm/byteorder.h>
20	#include <asm/cpu.h>
21	#include <asm/page.h>
22	#include <asm/pgtable-bits.h>
23	#include <asm/processor.h>
24
25	#include <mangle-port.h>
26
27	/*
28	* Slowdown I/O port space accesses for antique hardware.
29	*/
30	#undef CONF_SLOWDOWN_IO
31
32	/*
33	* Raw operations are never swapped in software. Otoh values that raw
34	* operations are working on may or may not have been swapped by the bus
35	* hardware. An example use would be for flash memory that's used for
36	* execute in place.
37	*/
38	# define __raw_ioswabb(x) (x)
39	# define __raw_ioswabw(x) (x)
40	# define __raw_ioswabl(x) (x)
41	# define __raw_ioswabq(x) (x)
42
43	/*
44	* Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
45	* less sane hardware forces software to fiddle with this...
46	*/
47	#if defined(CONFIG_SWAP_IO_SPACE)
48
49	# define ioswabb(x) (x)
50	# ifdef CONFIG_SGI_IP22
51	/*
52	* IP22 seems braindead enough to swap 16bits values in hardware, but
53	* not 32bits. Go figure... Can't tell without documentation.
54	*/
55	# define ioswabw(x) (x)
56	# else
57	# define ioswabw(x) le16_to_cpu(x)
58	# endif
59	# define ioswabl(x) le32_to_cpu(x)
60	# define ioswabq(x) le64_to_cpu(x)
61
62	#else
63
64	# define ioswabb(x) (x)
65	# define ioswabw(x) (x)
66	# define ioswabl(x) (x)
67	# define ioswabq(x) (x)
68
69	#endif
70
71	/*
72	* Native bus accesses never swapped.
73	*/
74	#define bus_ioswabb(x) (x)
75	#define bus_ioswabw(x) (x)
76	#define bus_ioswabl(x) (x)
77	#define bus_ioswabq(x) (x)
78
79	#define __bus_ioswabq bus_ioswabq
80
81	#define IO_SPACE_LIMIT 0xffff
82
83	/*
84	* On MIPS I/O ports are memory mapped, so we access them using normal
85	* load/store instructions. mips_io_port_base is the virtual address to
86	* which all ports are being mapped. For sake of efficiency some code
87	* assumes that this is an address that can be loaded with a single lui
88	* instruction, so the lower 16 bits must be zero. Should be true on
89	* on any sane architecture; generic code does not use this assumption.
90	*/
91	extern const unsigned long mips_io_port_base;
92
93	#define set_io_port_base(base) \
94	do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
95
96	/*
97	* Thanks to James van Artsdalen for a better timing-fix than
98	* the two short jumps: using outb's to a nonexistent port seems
99	* to guarantee better timings even on fast machines.
100	*
101	* On the other hand, I'd like to be sure of a non-existent port:
102	* I feel a bit unsafe about using 0x80 (should be safe, though)
103	*
104	* Linus
105	*
106	*/
107
108	#define __SLOW_DOWN_IO \
109	__asm__ __volatile__( \
110	"sb\t$0,0x80(%0)" \
111	: : "r" (mips_io_port_base));
112
113	#ifdef CONF_SLOWDOWN_IO
114	#ifdef REALLY_SLOW_IO
115	#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
116	#else
117	#define SLOW_DOWN_IO __SLOW_DOWN_IO
118	#endif
119	#else
120	#define SLOW_DOWN_IO
121	#endif
122
123	/*
124	* virt_to_phys - map virtual addresses to physical
125	* @address: address to remap
126	*
127	* The returned physical address is the physical (CPU) mapping for
128	* the memory address given. It is only valid to use this function on
129	* addresses directly mapped or allocated via kmalloc.
130	*
131	* This function does not give bus mappings for DMA transfers. In
132	* almost all conceivable cases a device driver should not be using
133	* this function
134	*/
135	static inline unsigned long virt_to_phys(volatile void * address)
136	{
137	return (unsigned long)address - PAGE_OFFSET;
138	}
139
140	/*
141	* phys_to_virt - map physical address to virtual
142	* @address: address to remap
143	*
144	* The returned virtual address is a current CPU mapping for
145	* the memory address given. It is only valid to use this function on
146	* addresses that have a kernel mapping
147	*
148	* This function does not handle bus mappings for DMA transfers. In
149	* almost all conceivable cases a device driver should not be using
150	* this function
151	*/
152	static inline void * phys_to_virt(unsigned long address)
153	{
154	return (void *)(address + PAGE_OFFSET);
155	}
156
157	/*
158	* ISA I/O bus memory addresses are 1:1 with the physical address.
159	*/
160	static inline unsigned long isa_virt_to_bus(volatile void * address)
161	{
162	return (unsigned long)address - PAGE_OFFSET;
163	}
164
165	static inline void * isa_bus_to_virt(unsigned long address)
166	{
167	return (void *)(address + PAGE_OFFSET);
168	}
169
170	#define isa_page_to_bus page_to_phys
171
172	/*
173	* However PCI ones are not necessarily 1:1 and therefore these interfaces
174	* are forbidden in portable PCI drivers.
175	*
176	* Allow them for x86 for legacy drivers, though.
177	*/
178	#define virt_to_bus virt_to_phys
179	#define bus_to_virt phys_to_virt
180
181	/*
182	* isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
183	* for the processor. This implies the assumption that there is only
184	* one of these busses.
185	*/
186	extern unsigned long isa_slot_offset;
187
188	/*
189	* Change "struct page" to physical address.
190	*/
191	#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
192
193	extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags);
194	extern void __iounmap(volatile void *addr);
195
196	static inline void * __ioremap_mode(phys_t offset, unsigned long size,
197	unsigned long flags)
198	{
199	if (cpu_has_64bit_addresses) {
200	__u64 base = UNCAC_BASE;
201
202	/*
203	* R10000 supports a 2 bit uncached attribute therefore
204	* UNCAC_BASE may not equal IO_BASE.
205	*/
206	if (flags == _CACHE_UNCACHED)
207	base = (__u64) IO_BASE;
208	return (void *) (unsigned long) (base + offset);
209	}
210
211	return __ioremap(offset, size, flags);
212	}
213
214	/*
215	* ioremap - map bus memory into CPU space
216	* @offset: bus address of the memory
217	* @size: size of the resource to map
218	*
219	* ioremap performs a platform specific sequence of operations to
220	* make bus memory CPU accessible via the readb/readw/readl/writeb/
221	* writew/writel functions and the other mmio helpers. The returned
222	* address is not guaranteed to be usable directly as a virtual
223	* address.
224	*/
225	#define ioremap(offset, size) \
226	__ioremap_mode((offset), (size), _CACHE_UNCACHED)
227
228	/*
229	* ioremap_nocache - map bus memory into CPU space
230	* @offset: bus address of the memory
231	* @size: size of the resource to map
232	*
233	* ioremap_nocache performs a platform specific sequence of operations to
234	* make bus memory CPU accessible via the readb/readw/readl/writeb/
235	* writew/writel functions and the other mmio helpers. The returned
236	* address is not guaranteed to be usable directly as a virtual
237	* address.
238	*
239	* This version of ioremap ensures that the memory is marked uncachable
240	* on the CPU as well as honouring existing caching rules from things like
241	* the PCI bus. Note that there are other caches and buffers on many
242	* busses. In paticular driver authors should read up on PCI writes
243	*
244	* It's useful if some control registers are in such an area and
245	* write combining or read caching is not desirable:
246	*/
247	#define ioremap_nocache(offset, size) \
248	__ioremap_mode((offset), (size), _CACHE_UNCACHED)
249
250	/*
251	* These two are MIPS specific ioremap variant. ioremap_cacheable_cow
252	* requests a cachable mapping, ioremap_uncached_accelerated requests a
253	* mapping using the uncached accelerated mode which isn't supported on
254	* all processors.
255	*/
256	#define ioremap_cacheable_cow(offset, size) \
257	__ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
258	#define ioremap_uncached_accelerated(offset, size) \
259	__ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
260
261	static inline void iounmap(volatile void *addr)
262	{
263	if (cpu_has_64bit_addresses)
264	return;
265
266	__iounmap(addr);
267	}
268
269
270	#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
271	\
272	static inline void pfx##write##bwlq(type val, \
273	volatile void *mem) \
274	{ \
275	volatile type *__mem; \
276	type __val; \
277	\
278	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
279	\
280	__val = pfx##ioswab##bwlq(val); \
281	\
282	if (sizeof(type) != sizeof(__u64) \|\| sizeof(__u64) == sizeof(long)) \
283	*__mem = __val; \
284	else if (cpu_has_64bits) { \
285	unsigned long __flags; \
286	type __tmp; \
287	\
288	if (irq) \
289	local_irq_save(__flags); \
290	__asm__ __volatile__( \
291	".set mips3" "\t\t# __writeq""\n\t" \
292	"dsll32 %L0, %L0, 0" "\n\t" \
293	"dsrl32 %L0, %L0, 0" "\n\t" \
294	"dsll32 %M0, %M0, 0" "\n\t" \
295	"or %L0, %L0, %M0" "\n\t" \
296	"sd %L0, %2" "\n\t" \
297	".set mips0" "\n" \
298	: "=r" (__tmp) \
299	: "0" (__val), "m" (*__mem)); \
300	if (irq) \
301	local_irq_restore(__flags); \
302	} else \
303	BUG(); \
304	} \
305	\
306	static inline type pfx##read##bwlq(volatile void *mem) \
307	{ \
308	volatile type *__mem; \
309	type __val; \
310	\
311	__mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
312	\
313	if (sizeof(type) != sizeof(__u64) \|\| sizeof(__u64) == sizeof(long)) \
314	__val = *__mem; \
315	else if (cpu_has_64bits) { \
316	unsigned long __flags; \
317	\
318	local_irq_save(__flags); \
319	__asm__ __volatile__( \
320	".set mips3" "\t\t# __readq" "\n\t" \
321	"ld %L0, %1" "\n\t" \
322	"dsra32 %M0, %L0, 0" "\n\t" \
323	"sll %L0, %L0, 0" "\n\t" \
324	".set mips0" "\n" \
325	: "=r" (__val) \
326	: "m" (*__mem)); \
327	local_irq_restore(__flags); \
328	} else { \
329	__val = 0; \
330	BUG(); \
331	} \
332	\
333	return pfx##ioswab##bwlq(__val); \
334	}
335
336	#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
337	\
338	static inline void pfx##out##bwlq##p(type val, unsigned long port) \
339	{ \
340	volatile type *__addr; \
341	type __val; \
342	\
343	port = __swizzle_addr_##bwlq(port); \
344	__addr = (void *)(mips_io_port_base + port); \
345	\
346	__val = pfx##ioswab##bwlq(val); \
347	\
348	if (sizeof(type) != sizeof(__u64)) { \
349	*__addr = __val; \
350	slow; \
351	} else \
352	BUILD_BUG(); \
353	} \
354	\
355	static inline type pfx##in##bwlq##p(unsigned long port) \
356	{ \
357	volatile type *__addr; \
358	type __val; \
359	\
360	port = __swizzle_addr_##bwlq(port); \
361	__addr = (void *)(mips_io_port_base + port); \
362	\
363	if (sizeof(type) != sizeof(__u64)) { \
364	__val = *__addr; \
365	slow; \
366	} else { \
367	__val = 0; \
368	BUILD_BUG(); \
369	} \
370	\
371	return pfx##ioswab##bwlq(__val); \
372	}
373
374	#define __BUILD_MEMORY_PFX(bus, bwlq, type) \
375	\
376	__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
377
378	#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
379	\
380	__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
381	__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
382
383	#define BUILDIO(bwlq, type) \
384	\
385	__BUILD_MEMORY_PFX(, bwlq, type) \
386	__BUILD_MEMORY_PFX(__raw_, bwlq, type) \
387	__BUILD_MEMORY_PFX(bus_, bwlq, type) \
388	__BUILD_IOPORT_PFX(, bwlq, type) \
389	__BUILD_IOPORT_PFX(__raw_, bwlq, type)
390
391	#define __BUILDIO(bwlq, type) \
392	\
393	__BUILD_MEMORY_SINGLE(__bus_, bwlq, type, 0)
394
395	BUILDIO(b, __u8)
396	BUILDIO(w, __u16)
397	BUILDIO(l, __u32)
398	BUILDIO(q, __u64)
399
400	__BUILDIO(q, __u64)
401
402	#define readb_relaxed readb
403	#define readw_relaxed readw
404	#define readl_relaxed readl
405	#define readq_relaxed readq
406
407	/*
408	* Some code tests for these symbols
409	*/
410	#define readq readq
411	#define writeq writeq
412
413	#define __BUILD_MEMORY_STRING(bwlq, type) \
414	\
415	static inline void writes##bwlq(volatile void mem, void addr, \
416	unsigned int count) \
417	{ \
418	volatile type *__addr = addr; \
419	\
420	while (count--) { \
421	__raw_write##bwlq(*__addr, mem); \
422	__addr++; \
423	} \
424	} \
425	\
426	static inline void reads##bwlq(volatile void mem, void addr, \
427	unsigned int count) \
428	{ \
429	volatile type *__addr = addr; \
430	\
431	while (count--) { \
432	*__addr = __raw_read##bwlq(mem); \
433	__addr++; \
434	} \
435	}
436
437	#define __BUILD_IOPORT_STRING(bwlq, type) \
438	\
439	static inline void outs##bwlq(unsigned long port, void *addr, \
440	unsigned int count) \
441	{ \
442	volatile type *__addr = addr; \
443	\
444	while (count--) { \
445	__raw_out##bwlq(*__addr, port); \
446	__addr++; \
447	} \
448	} \
449	\
450	static inline void ins##bwlq(unsigned long port, void *addr, \
451	unsigned int count) \
452	{ \
453	volatile type *__addr = addr; \
454	\
455	while (count--) { \
456	*__addr = __raw_in##bwlq(port); \
457	__addr++; \
458	} \
459	}
460
461	#define BUILDSTRING(bwlq, type) \
462	\
463	__BUILD_MEMORY_STRING(bwlq, type) \
464	__BUILD_IOPORT_STRING(bwlq, type)
465
466	BUILDSTRING(b, __u8)
467	BUILDSTRING(w, __u16)
468	BUILDSTRING(l, __u32)
469	BUILDSTRING(q, __u64)
470
471
472	/* Depends on MIPS II instruction set */
473	#define mmiowb() asm volatile ("sync" ::: "memory")
474
475	#define memset_io(a,b,c) memset((void *)(a),(b),(c))
476	#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
477	#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
478
479	/*
480	* Memory Mapped I/O
481	*/
482	#define ioread8(addr) readb(addr)
483	#define ioread16(addr) readw(addr)
484	#define ioread32(addr) readl(addr)
485
486	#define iowrite8(b,addr) writeb(b,addr)
487	#define iowrite16(w,addr) writew(w,addr)
488	#define iowrite32(l,addr) writel(l,addr)
489
490	#define ioread8_rep(a,b,c) readsb(a,b,c)
491	#define ioread16_rep(a,b,c) readsw(a,b,c)
492	#define ioread32_rep(a,b,c) readsl(a,b,c)
493
494	#define iowrite8_rep(a,b,c) writesb(a,b,c)
495	#define iowrite16_rep(a,b,c) writesw(a,b,c)
496	#define iowrite32_rep(a,b,c) writesl(a,b,c)
497
498	/* Create a virtual mapping cookie for an IO port range */
499	extern void *ioport_map(unsigned long port, unsigned int nr);
500	extern void ioport_unmap(void *);
501
502	/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
503	struct pci_dev;
504	extern void pci_iomap(struct pci_dev dev, int bar, unsigned long max);
505	extern void pci_iounmap(struct pci_dev dev, void );
506
507	/*
508	* ISA space is 'always mapped' on currently supported MIPS systems, no need
509	* to explicitly ioremap() it. The fact that the ISA IO space is mapped
510	* to PAGE_OFFSET is pure coincidence - it does not mean ISA values
511	* are physical addresses. The following constant pointer can be
512	* used as the IO-area pointer (it can be iounmapped as well, so the
513	* analogy with PCI is quite large):
514	*/
515	#define __ISA_IO_base ((char *)(isa_slot_offset))
516
517	#define isa_readb(a) readb(__ISA_IO_base + (a))
518	#define isa_readw(a) readw(__ISA_IO_base + (a))
519	#define isa_readl(a) readl(__ISA_IO_base + (a))
520	#define isa_readq(a) readq(__ISA_IO_base + (a))
521	#define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a))
522	#define isa_writew(w,a) writew(w,__ISA_IO_base + (a))
523	#define isa_writel(l,a) writel(l,__ISA_IO_base + (a))
524	#define isa_writeq(q,a) writeq(q,__ISA_IO_base + (a))
525	#define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c))
526	#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
527	#define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c))
528
529	/*
530	* We don't have csum_partial_copy_fromio() yet, so we cheat here and
531	* just copy it. The net code will then do the checksum later.
532	*/
533	#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
534	#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
535
536	/*
537	* check_signature - find BIOS signatures
538	* @io_addr: mmio address to check
539	* @signature: signature block
540	* @length: length of signature
541	*
542	* Perform a signature comparison with the mmio address io_addr. This
543	* address should have been obtained by ioremap.
544	* Returns 1 on a match.
545	*/
546	static inline int check_signature(char *io_addr,
547	const unsigned char *signature, int length)
548	{
549	int retval = 0;
550	do {
551	if (readb(io_addr) != *signature)
552	goto out;
553	io_addr++;
554	signature++;
555	length--;
556	} while (length);
557	retval = 1;
558	out:
559	return retval;
560	}
561
562	/*
563	* The caches on some architectures aren't dma-coherent and have need to
564	* handle this in software. There are three types of operations that
565	* can be applied to dma buffers.
566	*
567	* - dma_cache_wback_inv(start, size) makes caches and coherent by
568	* writing the content of the caches back to memory, if necessary.
569	* The function also invalidates the affected part of the caches as
570	* necessary before DMA transfers from outside to memory.
571	* - dma_cache_wback(start, size) makes caches and coherent by
572	* writing the content of the caches back to memory, if necessary.
573	* The function also invalidates the affected part of the caches as
574	* necessary before DMA transfers from outside to memory.
575	* - dma_cache_inv(start, size) invalidates the affected parts of the
576	* caches. Dirty lines of the caches may be written back or simply
577	* be discarded. This operation is necessary before dma operations
578	* to the memory.
579	*/
580	#ifdef CONFIG_DMA_NONCOHERENT
581
582	extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
583	extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
584	extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
585
586	#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size)
587	#define dma_cache_wback(start, size) _dma_cache_wback(start,size)
588	#define dma_cache_inv(start, size) _dma_cache_inv(start,size)
589
590	#else /* Sane hardware */
591
592	#define dma_cache_wback_inv(start,size) \
593	do { (void) (start); (void) (size); } while (0)
594	#define dma_cache_wback(start,size) \
595	do { (void) (start); (void) (size); } while (0)
596	#define dma_cache_inv(start,size) \
597	do { (void) (start); (void) (size); } while (0)
598
599	#endif /* CONFIG_DMA_NONCOHERENT */
600
601	/*
602	* Read a 32-bit register that requires a 64-bit read cycle on the bus.
603	* Avoid interrupt mucking, just adjust the address for 4-byte access.
604	* Assume the addresses are 8-byte aligned.
605	*/
606	#ifdef __MIPSEB__
607	#define __CSR_32_ADJUST 4
608	#else
609	#define __CSR_32_ADJUST 0
610	#endif
611
612	#define csr_out32(v,a) ((volatile __u32 )((unsigned long)(a) + __CSR_32_ADJUST) = (v))
613	#define csr_in32(a) ((volatile __u32 )((unsigned long)(a) + __CSR_32_ADJUST))
614
615	/*
616	* Convert a physical pointer to a virtual kernel pointer for /dev/mem
617	* access
618	*/
619	#define xlate_dev_mem_ptr(p) __va(p)
620
621	/*
622	* Convert a virtual cached pointer to an uncached pointer
623	*/
624	#define xlate_dev_kmem_ptr(p) p
625
626	#endif /* _ASM_IO_H */

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source: svn/trunk/newcon3bcm2_21bu/toolchain/mips-linux-uclibc/include/asm/io.h @ 2

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