| 1 | /* |
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| 2 | * This file is subject to the terms and conditions of the GNU General Public |
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| 3 | * License. See the file "COPYING" in the main directory of this archive |
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| 4 | * for more details. |
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| 5 | * |
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| 6 | * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle |
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| 7 | * Copyright (C) 2000 Silicon Graphics, Inc. |
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| 8 | * Modified for further R[236]000 support by Paul M. Antoine, 1996. |
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| 9 | * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com |
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| 10 | * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. |
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| 11 | * Copyright (C) 2003 Maciej W. Rozycki |
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| 12 | */ |
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| 13 | #ifndef _ASM_MIPSREGS_H |
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| 14 | #define _ASM_MIPSREGS_H |
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| 15 | |
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| 16 | #include <linux/linkage.h> |
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| 17 | |
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| 18 | /* |
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| 19 | * The following macros are especially useful for __asm__ |
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| 20 | * inline assembler. |
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| 21 | */ |
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| 22 | #ifndef __STR |
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| 23 | #define __STR(x) #x |
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| 24 | #endif |
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| 25 | #ifndef STR |
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| 26 | #define STR(x) __STR(x) |
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| 27 | #endif |
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| 28 | |
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| 29 | /* |
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| 30 | * Configure language |
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| 31 | */ |
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| 32 | #ifdef __ASSEMBLY__ |
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| 33 | #define _ULCAST_ |
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| 34 | #else |
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| 35 | #define _ULCAST_ (unsigned long) |
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| 36 | #endif |
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| 37 | |
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| 38 | /* |
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| 39 | * Coprocessor 0 register names |
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| 40 | */ |
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| 41 | #define CP0_INDEX $0 |
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| 42 | #define CP0_RANDOM $1 |
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| 43 | #define CP0_ENTRYLO0 $2 |
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| 44 | #define CP0_ENTRYLO1 $3 |
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| 45 | #define CP0_CONF $3 |
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| 46 | #define CP0_CONTEXT $4 |
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| 47 | #define CP0_PAGEMASK $5 |
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| 48 | #define CP0_WIRED $6 |
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| 49 | #define CP0_INFO $7 |
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| 50 | #define CP0_BADVADDR $8 |
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| 51 | #define CP0_COUNT $9 |
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| 52 | #define CP0_ENTRYHI $10 |
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| 53 | #define CP0_COMPARE $11 |
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| 54 | #define CP0_STATUS $12 |
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| 55 | #define CP0_CAUSE $13 |
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| 56 | #define CP0_EPC $14 |
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| 57 | #define CP0_PRID $15 |
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| 58 | #define CP0_CONFIG $16 |
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| 59 | #define CP0_LLADDR $17 |
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| 60 | #define CP0_WATCHLO $18 |
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| 61 | #define CP0_WATCHHI $19 |
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| 62 | #define CP0_XCONTEXT $20 |
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| 63 | #define CP0_FRAMEMASK $21 |
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| 64 | #define CP0_DIAGNOSTIC $22 |
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| 65 | #define CP0_DEBUG $23 |
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| 66 | #define CP0_DEPC $24 |
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| 67 | #define CP0_PERFORMANCE $25 |
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| 68 | #define CP0_ECC $26 |
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| 69 | #define CP0_CACHEERR $27 |
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| 70 | #define CP0_TAGLO $28 |
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| 71 | #define CP0_TAGHI $29 |
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| 72 | #define CP0_ERROREPC $30 |
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| 73 | #define CP0_DESAVE $31 |
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| 74 | |
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| 75 | /* |
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| 76 | * R4640/R4650 cp0 register names. These registers are listed |
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| 77 | * here only for completeness; without MMU these CPUs are not useable |
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| 78 | * by Linux. A future ELKS port might take make Linux run on them |
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| 79 | * though ... |
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| 80 | */ |
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| 81 | #define CP0_IBASE $0 |
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| 82 | #define CP0_IBOUND $1 |
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| 83 | #define CP0_DBASE $2 |
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| 84 | #define CP0_DBOUND $3 |
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| 85 | #define CP0_CALG $17 |
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| 86 | #define CP0_IWATCH $18 |
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| 87 | #define CP0_DWATCH $19 |
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| 88 | |
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| 89 | /* |
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| 90 | * Coprocessor 0 Set 1 register names |
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| 91 | */ |
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| 92 | #define CP0_S1_DERRADDR0 $26 |
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| 93 | #define CP0_S1_DERRADDR1 $27 |
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| 94 | #define CP0_S1_INTCONTROL $20 |
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| 95 | |
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| 96 | /* |
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| 97 | * TX39 Series |
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| 98 | */ |
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| 99 | #define CP0_TX39_CACHE $7 |
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| 100 | |
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| 101 | /* |
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| 102 | * Coprocessor 1 (FPU) register names |
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| 103 | */ |
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| 104 | #define CP1_REVISION $0 |
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| 105 | #define CP1_STATUS $31 |
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| 106 | |
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| 107 | /* |
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| 108 | * FPU Status Register Values |
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| 109 | */ |
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| 110 | /* |
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| 111 | * Status Register Values |
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| 112 | */ |
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| 113 | |
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| 114 | #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ |
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| 115 | #define FPU_CSR_COND 0x00800000 /* $fcc0 */ |
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| 116 | #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ |
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| 117 | #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ |
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| 118 | #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ |
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| 119 | #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ |
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| 120 | #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ |
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| 121 | #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ |
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| 122 | #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ |
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| 123 | #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ |
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| 124 | |
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| 125 | /* |
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| 126 | * X the exception cause indicator |
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| 127 | * E the exception enable |
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| 128 | * S the sticky/flag bit |
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| 129 | */ |
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| 130 | #define FPU_CSR_ALL_X 0x0003f000 |
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| 131 | #define FPU_CSR_UNI_X 0x00020000 |
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| 132 | #define FPU_CSR_INV_X 0x00010000 |
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| 133 | #define FPU_CSR_DIV_X 0x00008000 |
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| 134 | #define FPU_CSR_OVF_X 0x00004000 |
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| 135 | #define FPU_CSR_UDF_X 0x00002000 |
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| 136 | #define FPU_CSR_INE_X 0x00001000 |
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| 137 | |
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| 138 | #define FPU_CSR_ALL_E 0x00000f80 |
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| 139 | #define FPU_CSR_INV_E 0x00000800 |
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| 140 | #define FPU_CSR_DIV_E 0x00000400 |
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| 141 | #define FPU_CSR_OVF_E 0x00000200 |
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| 142 | #define FPU_CSR_UDF_E 0x00000100 |
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| 143 | #define FPU_CSR_INE_E 0x00000080 |
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| 144 | |
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| 145 | #define FPU_CSR_ALL_S 0x0000007c |
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| 146 | #define FPU_CSR_INV_S 0x00000040 |
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| 147 | #define FPU_CSR_DIV_S 0x00000020 |
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| 148 | #define FPU_CSR_OVF_S 0x00000010 |
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| 149 | #define FPU_CSR_UDF_S 0x00000008 |
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| 150 | #define FPU_CSR_INE_S 0x00000004 |
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| 151 | |
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| 152 | /* rounding mode */ |
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| 153 | #define FPU_CSR_RN 0x0 /* nearest */ |
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| 154 | #define FPU_CSR_RZ 0x1 /* towards zero */ |
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| 155 | #define FPU_CSR_RU 0x2 /* towards +Infinity */ |
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| 156 | #define FPU_CSR_RD 0x3 /* towards -Infinity */ |
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| 157 | |
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| 158 | |
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| 159 | /* |
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| 160 | * Values for PageMask register |
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| 161 | */ |
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| 162 | #ifdef CONFIG_CPU_VR41XX |
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| 163 | |
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| 164 | /* Why doesn't stupidity hurt ... */ |
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| 165 | |
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| 166 | #define PM_1K 0x00000000 |
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| 167 | #define PM_4K 0x00001800 |
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| 168 | #define PM_16K 0x00007800 |
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| 169 | #define PM_64K 0x0001f800 |
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| 170 | #define PM_256K 0x0007f800 |
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| 171 | |
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| 172 | #else |
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| 173 | |
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| 174 | #define PM_4K 0x00000000 |
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| 175 | #define PM_16K 0x00006000 |
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| 176 | #define PM_64K 0x0001e000 |
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| 177 | #define PM_256K 0x0007e000 |
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| 178 | #define PM_1M 0x001fe000 |
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| 179 | #define PM_4M 0x007fe000 |
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| 180 | #define PM_16M 0x01ffe000 |
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| 181 | #define PM_64M 0x07ffe000 |
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| 182 | #define PM_256M 0x1fffe000 |
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| 183 | |
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| 184 | #endif |
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| 185 | |
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| 186 | /* |
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| 187 | * Default page size for a given kernel configuration |
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| 188 | */ |
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| 189 | #ifdef CONFIG_PAGE_SIZE_4KB |
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| 190 | #define PM_DEFAULT_MASK PM_4K |
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| 191 | #elif defined(CONFIG_PAGE_SIZE_16KB) |
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| 192 | #define PM_DEFAULT_MASK PM_16K |
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| 193 | #elif defined(CONFIG_PAGE_SIZE_64KB) |
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| 194 | #define PM_DEFAULT_MASK PM_64K |
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| 195 | #else |
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| 196 | #error Bad page size configuration! |
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| 197 | #endif |
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| 198 | |
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| 199 | |
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| 200 | /* |
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| 201 | * Values used for computation of new tlb entries |
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| 202 | */ |
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| 203 | #define PL_4K 12 |
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| 204 | #define PL_16K 14 |
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| 205 | #define PL_64K 16 |
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| 206 | #define PL_256K 18 |
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| 207 | #define PL_1M 20 |
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| 208 | #define PL_4M 22 |
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| 209 | #define PL_16M 24 |
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| 210 | #define PL_64M 26 |
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| 211 | #define PL_256M 28 |
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| 212 | |
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| 213 | /* |
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| 214 | * R4x00 interrupt enable / cause bits |
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| 215 | */ |
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| 216 | #define IE_SW0 (_ULCAST_(1) << 8) |
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| 217 | #define IE_SW1 (_ULCAST_(1) << 9) |
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| 218 | #define IE_IRQ0 (_ULCAST_(1) << 10) |
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| 219 | #define IE_IRQ1 (_ULCAST_(1) << 11) |
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| 220 | #define IE_IRQ2 (_ULCAST_(1) << 12) |
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| 221 | #define IE_IRQ3 (_ULCAST_(1) << 13) |
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| 222 | #define IE_IRQ4 (_ULCAST_(1) << 14) |
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| 223 | #define IE_IRQ5 (_ULCAST_(1) << 15) |
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| 224 | |
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| 225 | /* |
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| 226 | * R4x00 interrupt cause bits |
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| 227 | */ |
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| 228 | #define C_SW0 (_ULCAST_(1) << 8) |
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| 229 | #define C_SW1 (_ULCAST_(1) << 9) |
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| 230 | #define C_IRQ0 (_ULCAST_(1) << 10) |
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| 231 | #define C_IRQ1 (_ULCAST_(1) << 11) |
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| 232 | #define C_IRQ2 (_ULCAST_(1) << 12) |
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| 233 | #define C_IRQ3 (_ULCAST_(1) << 13) |
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| 234 | #define C_IRQ4 (_ULCAST_(1) << 14) |
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| 235 | #define C_IRQ5 (_ULCAST_(1) << 15) |
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| 236 | |
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| 237 | /* |
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| 238 | * Bitfields in the R4xx0 cp0 status register |
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| 239 | */ |
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| 240 | #define ST0_IE 0x00000001 |
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| 241 | #define ST0_EXL 0x00000002 |
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| 242 | #define ST0_ERL 0x00000004 |
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| 243 | #define ST0_KSU 0x00000018 |
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| 244 | # define KSU_USER 0x00000010 |
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| 245 | # define KSU_SUPERVISOR 0x00000008 |
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| 246 | # define KSU_KERNEL 0x00000000 |
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| 247 | #define ST0_UX 0x00000020 |
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| 248 | #define ST0_SX 0x00000040 |
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| 249 | #define ST0_KX 0x00000080 |
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| 250 | #define ST0_DE 0x00010000 |
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| 251 | #define ST0_CE 0x00020000 |
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| 252 | |
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| 253 | /* |
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| 254 | * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate |
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| 255 | * cacheops in userspace. This bit exists only on RM7000 and RM9000 |
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| 256 | * processors. |
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| 257 | */ |
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| 258 | #define ST0_CO 0x08000000 |
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| 259 | |
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| 260 | /* |
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| 261 | * Bitfields in the R[23]000 cp0 status register. |
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| 262 | */ |
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| 263 | #define ST0_IEC 0x00000001 |
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| 264 | #define ST0_KUC 0x00000002 |
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| 265 | #define ST0_IEP 0x00000004 |
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| 266 | #define ST0_KUP 0x00000008 |
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| 267 | #define ST0_IEO 0x00000010 |
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| 268 | #define ST0_KUO 0x00000020 |
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| 269 | /* bits 6 & 7 are reserved on R[23]000 */ |
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| 270 | #define ST0_ISC 0x00010000 |
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| 271 | #define ST0_SWC 0x00020000 |
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| 272 | #define ST0_CM 0x00080000 |
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| 273 | |
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| 274 | /* |
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| 275 | * Bits specific to the R4640/R4650 |
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| 276 | */ |
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| 277 | #define ST0_UM (_ULCAST_(1) << 4) |
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| 278 | #define ST0_IL (_ULCAST_(1) << 23) |
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| 279 | #define ST0_DL (_ULCAST_(1) << 24) |
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| 280 | |
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| 281 | /* |
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| 282 | * Bitfields in the TX39 family CP0 Configuration Register 3 |
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| 283 | */ |
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| 284 | #define TX39_CONF_ICS_SHIFT 19 |
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| 285 | #define TX39_CONF_ICS_MASK 0x00380000 |
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| 286 | #define TX39_CONF_ICS_1KB 0x00000000 |
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| 287 | #define TX39_CONF_ICS_2KB 0x00080000 |
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| 288 | #define TX39_CONF_ICS_4KB 0x00100000 |
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| 289 | #define TX39_CONF_ICS_8KB 0x00180000 |
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| 290 | #define TX39_CONF_ICS_16KB 0x00200000 |
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| 291 | |
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| 292 | #define TX39_CONF_DCS_SHIFT 16 |
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| 293 | #define TX39_CONF_DCS_MASK 0x00070000 |
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| 294 | #define TX39_CONF_DCS_1KB 0x00000000 |
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| 295 | #define TX39_CONF_DCS_2KB 0x00010000 |
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| 296 | #define TX39_CONF_DCS_4KB 0x00020000 |
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| 297 | #define TX39_CONF_DCS_8KB 0x00030000 |
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| 298 | #define TX39_CONF_DCS_16KB 0x00040000 |
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| 299 | |
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| 300 | #define TX39_CONF_CWFON 0x00004000 |
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| 301 | #define TX39_CONF_WBON 0x00002000 |
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| 302 | #define TX39_CONF_RF_SHIFT 10 |
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| 303 | #define TX39_CONF_RF_MASK 0x00000c00 |
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| 304 | #define TX39_CONF_DOZE 0x00000200 |
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| 305 | #define TX39_CONF_HALT 0x00000100 |
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| 306 | #define TX39_CONF_LOCK 0x00000080 |
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| 307 | #define TX39_CONF_ICE 0x00000020 |
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| 308 | #define TX39_CONF_DCE 0x00000010 |
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| 309 | #define TX39_CONF_IRSIZE_SHIFT 2 |
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| 310 | #define TX39_CONF_IRSIZE_MASK 0x0000000c |
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| 311 | #define TX39_CONF_DRSIZE_SHIFT 0 |
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| 312 | #define TX39_CONF_DRSIZE_MASK 0x00000003 |
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| 313 | |
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| 314 | /* |
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| 315 | * Status register bits available in all MIPS CPUs. |
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| 316 | */ |
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| 317 | #define ST0_IM 0x0000ff00 |
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| 318 | #define STATUSB_IP0 8 |
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| 319 | #define STATUSF_IP0 (_ULCAST_(1) << 8) |
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| 320 | #define STATUSB_IP1 9 |
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| 321 | #define STATUSF_IP1 (_ULCAST_(1) << 9) |
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| 322 | #define STATUSB_IP2 10 |
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| 323 | #define STATUSF_IP2 (_ULCAST_(1) << 10) |
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| 324 | #define STATUSB_IP3 11 |
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| 325 | #define STATUSF_IP3 (_ULCAST_(1) << 11) |
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| 326 | #define STATUSB_IP4 12 |
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| 327 | #define STATUSF_IP4 (_ULCAST_(1) << 12) |
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| 328 | #define STATUSB_IP5 13 |
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| 329 | #define STATUSF_IP5 (_ULCAST_(1) << 13) |
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| 330 | #define STATUSB_IP6 14 |
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| 331 | #define STATUSF_IP6 (_ULCAST_(1) << 14) |
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| 332 | #define STATUSB_IP7 15 |
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| 333 | #define STATUSF_IP7 (_ULCAST_(1) << 15) |
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| 334 | #define STATUSB_IP8 0 |
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| 335 | #define STATUSF_IP8 (_ULCAST_(1) << 0) |
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| 336 | #define STATUSB_IP9 1 |
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| 337 | #define STATUSF_IP9 (_ULCAST_(1) << 1) |
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| 338 | #define STATUSB_IP10 2 |
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| 339 | #define STATUSF_IP10 (_ULCAST_(1) << 2) |
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| 340 | #define STATUSB_IP11 3 |
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| 341 | #define STATUSF_IP11 (_ULCAST_(1) << 3) |
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| 342 | #define STATUSB_IP12 4 |
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| 343 | #define STATUSF_IP12 (_ULCAST_(1) << 4) |
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| 344 | #define STATUSB_IP13 5 |
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| 345 | #define STATUSF_IP13 (_ULCAST_(1) << 5) |
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| 346 | #define STATUSB_IP14 6 |
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| 347 | #define STATUSF_IP14 (_ULCAST_(1) << 6) |
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| 348 | #define STATUSB_IP15 7 |
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| 349 | #define STATUSF_IP15 (_ULCAST_(1) << 7) |
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| 350 | #define ST0_CH 0x00040000 |
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| 351 | #define ST0_SR 0x00100000 |
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| 352 | #define ST0_TS 0x00200000 |
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| 353 | #define ST0_BEV 0x00400000 |
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| 354 | #define ST0_RE 0x02000000 |
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| 355 | #define ST0_FR 0x04000000 |
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| 356 | #define ST0_CU 0xf0000000 |
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| 357 | #define ST0_CU0 0x10000000 |
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| 358 | #define ST0_CU1 0x20000000 |
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| 359 | #define ST0_CU2 0x40000000 |
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| 360 | #define ST0_CU3 0x80000000 |
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| 361 | #define ST0_XX 0x80000000 /* MIPS IV naming */ |
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| 362 | |
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| 363 | /* |
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| 364 | * Bitfields and bit numbers in the coprocessor 0 cause register. |
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| 365 | * |
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| 366 | * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. |
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| 367 | */ |
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| 368 | #define CAUSEB_EXCCODE 2 |
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| 369 | #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) |
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| 370 | #define CAUSEB_IP 8 |
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| 371 | #define CAUSEF_IP (_ULCAST_(255) << 8) |
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| 372 | #define CAUSEB_IP0 8 |
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| 373 | #define CAUSEF_IP0 (_ULCAST_(1) << 8) |
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| 374 | #define CAUSEB_IP1 9 |
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| 375 | #define CAUSEF_IP1 (_ULCAST_(1) << 9) |
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| 376 | #define CAUSEB_IP2 10 |
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| 377 | #define CAUSEF_IP2 (_ULCAST_(1) << 10) |
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| 378 | #define CAUSEB_IP3 11 |
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| 379 | #define CAUSEF_IP3 (_ULCAST_(1) << 11) |
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| 380 | #define CAUSEB_IP4 12 |
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| 381 | #define CAUSEF_IP4 (_ULCAST_(1) << 12) |
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| 382 | #define CAUSEB_IP5 13 |
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| 383 | #define CAUSEF_IP5 (_ULCAST_(1) << 13) |
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| 384 | #define CAUSEB_IP6 14 |
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| 385 | #define CAUSEF_IP6 (_ULCAST_(1) << 14) |
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| 386 | #define CAUSEB_IP7 15 |
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| 387 | #define CAUSEF_IP7 (_ULCAST_(1) << 15) |
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| 388 | #define CAUSEB_IV 23 |
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| 389 | #define CAUSEF_IV (_ULCAST_(1) << 23) |
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| 390 | #define CAUSEB_CE 28 |
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| 391 | #define CAUSEF_CE (_ULCAST_(3) << 28) |
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| 392 | #define CAUSEB_BD 31 |
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| 393 | #define CAUSEF_BD (_ULCAST_(1) << 31) |
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| 394 | |
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| 395 | /* |
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| 396 | * Bits in the coprocessor 0 config register. |
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| 397 | */ |
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| 398 | /* Generic bits. */ |
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| 399 | #define CONF_CM_CACHABLE_NO_WA 0 |
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| 400 | #define CONF_CM_CACHABLE_WA 1 |
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| 401 | #define CONF_CM_UNCACHED 2 |
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| 402 | #define CONF_CM_CACHABLE_NONCOHERENT 3 |
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| 403 | #define CONF_CM_CACHABLE_CE 4 |
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| 404 | #define CONF_CM_CACHABLE_COW 5 |
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| 405 | #define CONF_CM_CACHABLE_CUW 6 |
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| 406 | #define CONF_CM_CACHABLE_ACCELERATED 7 |
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| 407 | #define CONF_CM_CMASK 7 |
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| 408 | #define CONF_BE (_ULCAST_(1) << 15) |
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| 409 | |
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| 410 | /* Bits common to various processors. */ |
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| 411 | #define CONF_CU (_ULCAST_(1) << 3) |
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| 412 | #define CONF_DB (_ULCAST_(1) << 4) |
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| 413 | #define CONF_IB (_ULCAST_(1) << 5) |
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| 414 | #define CONF_DC (_ULCAST_(7) << 6) |
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| 415 | #define CONF_IC (_ULCAST_(7) << 9) |
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| 416 | #define CONF_EB (_ULCAST_(1) << 13) |
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| 417 | #define CONF_EM (_ULCAST_(1) << 14) |
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| 418 | #define CONF_SM (_ULCAST_(1) << 16) |
|---|
| 419 | #define CONF_SC (_ULCAST_(1) << 17) |
|---|
| 420 | #define CONF_EW (_ULCAST_(3) << 18) |
|---|
| 421 | #define CONF_EP (_ULCAST_(15)<< 24) |
|---|
| 422 | #define CONF_EC (_ULCAST_(7) << 28) |
|---|
| 423 | #define CONF_CM (_ULCAST_(1) << 31) |
|---|
| 424 | |
|---|
| 425 | /* Bits specific to the R4xx0. */ |
|---|
| 426 | #define R4K_CONF_SW (_ULCAST_(1) << 20) |
|---|
| 427 | #define R4K_CONF_SS (_ULCAST_(1) << 21) |
|---|
| 428 | #define R4K_CONF_SB (_ULCAST_(3) << 22) |
|---|
| 429 | |
|---|
| 430 | /* Bits specific to the R5000. */ |
|---|
| 431 | #define R5K_CONF_SE (_ULCAST_(1) << 12) |
|---|
| 432 | #define R5K_CONF_SS (_ULCAST_(3) << 20) |
|---|
| 433 | |
|---|
| 434 | /* Bits specific to the R10000. */ |
|---|
| 435 | #define R10K_CONF_DN (_ULCAST_(3) << 3) |
|---|
| 436 | #define R10K_CONF_CT (_ULCAST_(1) << 5) |
|---|
| 437 | #define R10K_CONF_PE (_ULCAST_(1) << 6) |
|---|
| 438 | #define R10K_CONF_PM (_ULCAST_(3) << 7) |
|---|
| 439 | #define R10K_CONF_EC (_ULCAST_(15)<< 9) |
|---|
| 440 | #define R10K_CONF_SB (_ULCAST_(1) << 13) |
|---|
| 441 | #define R10K_CONF_SK (_ULCAST_(1) << 14) |
|---|
| 442 | #define R10K_CONF_SS (_ULCAST_(7) << 16) |
|---|
| 443 | #define R10K_CONF_SC (_ULCAST_(7) << 19) |
|---|
| 444 | #define R10K_CONF_DC (_ULCAST_(7) << 26) |
|---|
| 445 | #define R10K_CONF_IC (_ULCAST_(7) << 29) |
|---|
| 446 | |
|---|
| 447 | /* Bits specific to the VR41xx. */ |
|---|
| 448 | #define VR41_CONF_CS (_ULCAST_(1) << 12) |
|---|
| 449 | #define VR41_CONF_M16 (_ULCAST_(1) << 20) |
|---|
| 450 | #define VR41_CONF_AD (_ULCAST_(1) << 23) |
|---|
| 451 | |
|---|
| 452 | /* Bits specific to the R30xx. */ |
|---|
| 453 | #define R30XX_CONF_FDM (_ULCAST_(1) << 19) |
|---|
| 454 | #define R30XX_CONF_REV (_ULCAST_(1) << 22) |
|---|
| 455 | #define R30XX_CONF_AC (_ULCAST_(1) << 23) |
|---|
| 456 | #define R30XX_CONF_RF (_ULCAST_(1) << 24) |
|---|
| 457 | #define R30XX_CONF_HALT (_ULCAST_(1) << 25) |
|---|
| 458 | #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) |
|---|
| 459 | #define R30XX_CONF_DBR (_ULCAST_(1) << 29) |
|---|
| 460 | #define R30XX_CONF_SB (_ULCAST_(1) << 30) |
|---|
| 461 | #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) |
|---|
| 462 | |
|---|
| 463 | /* Bits specific to the TX49. */ |
|---|
| 464 | #define TX49_CONF_DC (_ULCAST_(1) << 16) |
|---|
| 465 | #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ |
|---|
| 466 | #define TX49_CONF_HALT (_ULCAST_(1) << 18) |
|---|
| 467 | #define TX49_CONF_CWFON (_ULCAST_(1) << 27) |
|---|
| 468 | |
|---|
| 469 | /* Bits specific to the MIPS32/64 PRA. */ |
|---|
| 470 | #define MIPS_CONF_MT (_ULCAST_(7) << 7) |
|---|
| 471 | #define MIPS_CONF_AR (_ULCAST_(7) << 10) |
|---|
| 472 | #define MIPS_CONF_AT (_ULCAST_(3) << 13) |
|---|
| 473 | #define MIPS_CONF_M (_ULCAST_(1) << 31) |
|---|
| 474 | |
|---|
| 475 | /* |
|---|
| 476 | * R10000 performance counter definitions. |
|---|
| 477 | * |
|---|
| 478 | * FIXME: The R10000 performance counter opens a nice way to implement CPU |
|---|
| 479 | * time accounting with a precission of one cycle. I don't have |
|---|
| 480 | * R10000 silicon but just a manual, so ... |
|---|
| 481 | */ |
|---|
| 482 | |
|---|
| 483 | /* |
|---|
| 484 | * Events counted by counter #0 |
|---|
| 485 | */ |
|---|
| 486 | #define CE0_CYCLES 0 |
|---|
| 487 | #define CE0_INSN_ISSUED 1 |
|---|
| 488 | #define CE0_LPSC_ISSUED 2 |
|---|
| 489 | #define CE0_S_ISSUED 3 |
|---|
| 490 | #define CE0_SC_ISSUED 4 |
|---|
| 491 | #define CE0_SC_FAILED 5 |
|---|
| 492 | #define CE0_BRANCH_DECODED 6 |
|---|
| 493 | #define CE0_QW_WB_SECONDARY 7 |
|---|
| 494 | #define CE0_CORRECTED_ECC_ERRORS 8 |
|---|
| 495 | #define CE0_ICACHE_MISSES 9 |
|---|
| 496 | #define CE0_SCACHE_I_MISSES 10 |
|---|
| 497 | #define CE0_SCACHE_I_WAY_MISSPREDICTED 11 |
|---|
| 498 | #define CE0_EXT_INTERVENTIONS_REQ 12 |
|---|
| 499 | #define CE0_EXT_INVALIDATE_REQ 13 |
|---|
| 500 | #define CE0_VIRTUAL_COHERENCY_COND 14 |
|---|
| 501 | #define CE0_INSN_GRADUATED 15 |
|---|
| 502 | |
|---|
| 503 | /* |
|---|
| 504 | * Events counted by counter #1 |
|---|
| 505 | */ |
|---|
| 506 | #define CE1_CYCLES 0 |
|---|
| 507 | #define CE1_INSN_GRADUATED 1 |
|---|
| 508 | #define CE1_LPSC_GRADUATED 2 |
|---|
| 509 | #define CE1_S_GRADUATED 3 |
|---|
| 510 | #define CE1_SC_GRADUATED 4 |
|---|
| 511 | #define CE1_FP_INSN_GRADUATED 5 |
|---|
| 512 | #define CE1_QW_WB_PRIMARY 6 |
|---|
| 513 | #define CE1_TLB_REFILL 7 |
|---|
| 514 | #define CE1_BRANCH_MISSPREDICTED 8 |
|---|
| 515 | #define CE1_DCACHE_MISS 9 |
|---|
| 516 | #define CE1_SCACHE_D_MISSES 10 |
|---|
| 517 | #define CE1_SCACHE_D_WAY_MISSPREDICTED 11 |
|---|
| 518 | #define CE1_EXT_INTERVENTION_HITS 12 |
|---|
| 519 | #define CE1_EXT_INVALIDATE_REQ 13 |
|---|
| 520 | #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 |
|---|
| 521 | #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 |
|---|
| 522 | |
|---|
| 523 | /* |
|---|
| 524 | * These flags define in which privilege mode the counters count events |
|---|
| 525 | */ |
|---|
| 526 | #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ |
|---|
| 527 | #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ |
|---|
| 528 | #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ |
|---|
| 529 | #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ |
|---|
| 530 | |
|---|
| 531 | #ifndef __ASSEMBLY__ |
|---|
| 532 | |
|---|
| 533 | /* |
|---|
| 534 | * Functions to access the R10000 performance counters. These are basically |
|---|
| 535 | * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit |
|---|
| 536 | * performance counter number encoded into bits 1 ... 5 of the instruction. |
|---|
| 537 | * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware |
|---|
| 538 | * disassembler these will look like an access to sel 0 or 1. |
|---|
| 539 | */ |
|---|
| 540 | #define read_r10k_perf_cntr(counter) \ |
|---|
| 541 | ({ \ |
|---|
| 542 | unsigned int __res; \ |
|---|
| 543 | __asm__ __volatile__( \ |
|---|
| 544 | "mfpc\t%0, %1" \ |
|---|
| 545 | : "=r" (__res) \ |
|---|
| 546 | : "i" (counter)); \ |
|---|
| 547 | \ |
|---|
| 548 | __res; \ |
|---|
| 549 | }) |
|---|
| 550 | |
|---|
| 551 | #define write_r10k_perf_cntr(counter,val) \ |
|---|
| 552 | do { \ |
|---|
| 553 | __asm__ __volatile__( \ |
|---|
| 554 | "mtpc\t%0, %1" \ |
|---|
| 555 | : \ |
|---|
| 556 | : "r" (val), "i" (counter)); \ |
|---|
| 557 | } while (0) |
|---|
| 558 | |
|---|
| 559 | #define read_r10k_perf_event(counter) \ |
|---|
| 560 | ({ \ |
|---|
| 561 | unsigned int __res; \ |
|---|
| 562 | __asm__ __volatile__( \ |
|---|
| 563 | "mfps\t%0, %1" \ |
|---|
| 564 | : "=r" (__res) \ |
|---|
| 565 | : "i" (counter)); \ |
|---|
| 566 | \ |
|---|
| 567 | __res; \ |
|---|
| 568 | }) |
|---|
| 569 | |
|---|
| 570 | #define write_r10k_perf_cntl(counter,val) \ |
|---|
| 571 | do { \ |
|---|
| 572 | __asm__ __volatile__( \ |
|---|
| 573 | "mtps\t%0, %1" \ |
|---|
| 574 | : \ |
|---|
| 575 | : "r" (val), "i" (counter)); \ |
|---|
| 576 | } while (0) |
|---|
| 577 | |
|---|
| 578 | |
|---|
| 579 | /* |
|---|
| 580 | * Macros to access the system control coprocessor |
|---|
| 581 | */ |
|---|
| 582 | |
|---|
| 583 | #define __read_32bit_c0_register(source, sel) \ |
|---|
| 584 | ({ int __res; \ |
|---|
| 585 | if (sel == 0) \ |
|---|
| 586 | __asm__ __volatile__( \ |
|---|
| 587 | "mfc0\t%0, " #source "\n\t" \ |
|---|
| 588 | : "=r" (__res)); \ |
|---|
| 589 | else \ |
|---|
| 590 | __asm__ __volatile__( \ |
|---|
| 591 | ".set\tmips32\n\t" \ |
|---|
| 592 | "mfc0\t%0, " #source ", " #sel "\n\t" \ |
|---|
| 593 | ".set\tmips0\n\t" \ |
|---|
| 594 | : "=r" (__res)); \ |
|---|
| 595 | __res; \ |
|---|
| 596 | }) |
|---|
| 597 | |
|---|
| 598 | #define __read_64bit_c0_register(source, sel) \ |
|---|
| 599 | ({ unsigned long long __res; \ |
|---|
| 600 | if (sizeof(unsigned long) == 4) \ |
|---|
| 601 | __res = __read_64bit_c0_split(source, sel); \ |
|---|
| 602 | else if (sel == 0) \ |
|---|
| 603 | __asm__ __volatile__( \ |
|---|
| 604 | ".set\tmips3\n\t" \ |
|---|
| 605 | "dmfc0\t%0, " #source "\n\t" \ |
|---|
| 606 | ".set\tmips0" \ |
|---|
| 607 | : "=r" (__res)); \ |
|---|
| 608 | else \ |
|---|
| 609 | __asm__ __volatile__( \ |
|---|
| 610 | ".set\tmips64\n\t" \ |
|---|
| 611 | "dmfc0\t%0, " #source ", " #sel "\n\t" \ |
|---|
| 612 | ".set\tmips0" \ |
|---|
| 613 | : "=r" (__res)); \ |
|---|
| 614 | __res; \ |
|---|
| 615 | }) |
|---|
| 616 | |
|---|
| 617 | #define __write_32bit_c0_register(register, sel, value) \ |
|---|
| 618 | do { \ |
|---|
| 619 | if (sel == 0) \ |
|---|
| 620 | __asm__ __volatile__( \ |
|---|
| 621 | "mtc0\t%z0, " #register "\n\t" \ |
|---|
| 622 | : : "Jr" ((unsigned int)value)); \ |
|---|
| 623 | else \ |
|---|
| 624 | __asm__ __volatile__( \ |
|---|
| 625 | ".set\tmips32\n\t" \ |
|---|
| 626 | "mtc0\t%z0, " #register ", " #sel "\n\t" \ |
|---|
| 627 | ".set\tmips0" \ |
|---|
| 628 | : : "Jr" ((unsigned int)value)); \ |
|---|
| 629 | } while (0) |
|---|
| 630 | |
|---|
| 631 | #define __write_64bit_c0_register(register, sel, value) \ |
|---|
| 632 | do { \ |
|---|
| 633 | if (sizeof(unsigned long) == 4) \ |
|---|
| 634 | __write_64bit_c0_split(register, sel, value); \ |
|---|
| 635 | else if (sel == 0) \ |
|---|
| 636 | __asm__ __volatile__( \ |
|---|
| 637 | ".set\tmips3\n\t" \ |
|---|
| 638 | "dmtc0\t%z0, " #register "\n\t" \ |
|---|
| 639 | ".set\tmips0" \ |
|---|
| 640 | : : "Jr" (value)); \ |
|---|
| 641 | else \ |
|---|
| 642 | __asm__ __volatile__( \ |
|---|
| 643 | ".set\tmips64\n\t" \ |
|---|
| 644 | "dmtc0\t%z0, " #register ", " #sel "\n\t" \ |
|---|
| 645 | ".set\tmips0" \ |
|---|
| 646 | : : "Jr" (value)); \ |
|---|
| 647 | } while (0) |
|---|
| 648 | |
|---|
| 649 | #define __read_ulong_c0_register(reg, sel) \ |
|---|
| 650 | ((sizeof(unsigned long) == 4) ? \ |
|---|
| 651 | (unsigned long) __read_32bit_c0_register(reg, sel) : \ |
|---|
| 652 | (unsigned long) __read_64bit_c0_register(reg, sel)) |
|---|
| 653 | |
|---|
| 654 | #define __write_ulong_c0_register(reg, sel, val) \ |
|---|
| 655 | do { \ |
|---|
| 656 | if (sizeof(unsigned long) == 4) \ |
|---|
| 657 | __write_32bit_c0_register(reg, sel, val); \ |
|---|
| 658 | else \ |
|---|
| 659 | __write_64bit_c0_register(reg, sel, val); \ |
|---|
| 660 | } while (0) |
|---|
| 661 | |
|---|
| 662 | /* |
|---|
| 663 | * On RM7000/RM9000 these are uses to access cop0 set 1 registers |
|---|
| 664 | */ |
|---|
| 665 | #define __read_32bit_c0_ctrl_register(source) \ |
|---|
| 666 | ({ int __res; \ |
|---|
| 667 | __asm__ __volatile__( \ |
|---|
| 668 | "cfc0\t%0, " #source "\n\t" \ |
|---|
| 669 | : "=r" (__res)); \ |
|---|
| 670 | __res; \ |
|---|
| 671 | }) |
|---|
| 672 | |
|---|
| 673 | #define __write_32bit_c0_ctrl_register(register, value) \ |
|---|
| 674 | do { \ |
|---|
| 675 | __asm__ __volatile__( \ |
|---|
| 676 | "ctc0\t%z0, " #register "\n\t" \ |
|---|
| 677 | : : "Jr" ((unsigned int)value)); \ |
|---|
| 678 | } while (0) |
|---|
| 679 | |
|---|
| 680 | /* |
|---|
| 681 | * These versions are only needed for systems with more than 38 bits of |
|---|
| 682 | * physical address space running the 32-bit kernel. That's none atm :-) |
|---|
| 683 | */ |
|---|
| 684 | #define __read_64bit_c0_split(source, sel) \ |
|---|
| 685 | ({ \ |
|---|
| 686 | unsigned long long val; \ |
|---|
| 687 | unsigned long flags; \ |
|---|
| 688 | \ |
|---|
| 689 | local_irq_save(flags); \ |
|---|
| 690 | if (sel == 0) \ |
|---|
| 691 | __asm__ __volatile__( \ |
|---|
| 692 | ".set\tmips64\n\t" \ |
|---|
| 693 | "dmfc0\t%M0, " #source "\n\t" \ |
|---|
| 694 | "dsll\t%L0, %M0, 32\n\t" \ |
|---|
| 695 | "dsrl\t%M0, %M0, 32\n\t" \ |
|---|
| 696 | "dsrl\t%L0, %L0, 32\n\t" \ |
|---|
| 697 | ".set\tmips0" \ |
|---|
| 698 | : "=r" (val)); \ |
|---|
| 699 | else \ |
|---|
| 700 | __asm__ __volatile__( \ |
|---|
| 701 | ".set\tmips64\n\t" \ |
|---|
| 702 | "dmfc0\t%M0, " #source ", " #sel "\n\t" \ |
|---|
| 703 | "dsll\t%L0, %M0, 32\n\t" \ |
|---|
| 704 | "dsrl\t%M0, %M0, 32\n\t" \ |
|---|
| 705 | "dsrl\t%L0, %L0, 32\n\t" \ |
|---|
| 706 | ".set\tmips0" \ |
|---|
| 707 | : "=r" (val)); \ |
|---|
| 708 | local_irq_restore(flags); \ |
|---|
| 709 | \ |
|---|
| 710 | val; \ |
|---|
| 711 | }) |
|---|
| 712 | |
|---|
| 713 | #define __write_64bit_c0_split(source, sel, val) \ |
|---|
| 714 | do { \ |
|---|
| 715 | unsigned long flags; \ |
|---|
| 716 | \ |
|---|
| 717 | local_irq_save(flags); \ |
|---|
| 718 | if (sel == 0) \ |
|---|
| 719 | __asm__ __volatile__( \ |
|---|
| 720 | ".set\tmips64\n\t" \ |
|---|
| 721 | "dsll\t%L0, %L0, 32\n\t" \ |
|---|
| 722 | "dsrl\t%L0, %L0, 32\n\t" \ |
|---|
| 723 | "dsll\t%M0, %M0, 32\n\t" \ |
|---|
| 724 | "or\t%L0, %L0, %M0\n\t" \ |
|---|
| 725 | "dmtc0\t%L0, " #source "\n\t" \ |
|---|
| 726 | ".set\tmips0" \ |
|---|
| 727 | : : "r" (val)); \ |
|---|
| 728 | else \ |
|---|
| 729 | __asm__ __volatile__( \ |
|---|
| 730 | ".set\tmips64\n\t" \ |
|---|
| 731 | "dsll\t%L0, %L0, 32\n\t" \ |
|---|
| 732 | "dsrl\t%L0, %L0, 32\n\t" \ |
|---|
| 733 | "dsll\t%M0, %M0, 32\n\t" \ |
|---|
| 734 | "or\t%L0, %L0, %M0\n\t" \ |
|---|
| 735 | "dmtc0\t%L0, " #source ", " #sel "\n\t" \ |
|---|
| 736 | ".set\tmips0" \ |
|---|
| 737 | : : "r" (val)); \ |
|---|
| 738 | local_irq_restore(flags); \ |
|---|
| 739 | } while (0) |
|---|
| 740 | |
|---|
| 741 | #define read_c0_index() __read_32bit_c0_register($0, 0) |
|---|
| 742 | #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) |
|---|
| 743 | |
|---|
| 744 | #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) |
|---|
| 745 | #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) |
|---|
| 746 | |
|---|
| 747 | #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) |
|---|
| 748 | #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) |
|---|
| 749 | |
|---|
| 750 | #define read_c0_conf() __read_32bit_c0_register($3, 0) |
|---|
| 751 | #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) |
|---|
| 752 | |
|---|
| 753 | #define read_c0_context() __read_ulong_c0_register($4, 0) |
|---|
| 754 | #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) |
|---|
| 755 | |
|---|
| 756 | #define read_c0_pagemask() __read_32bit_c0_register($5, 0) |
|---|
| 757 | #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) |
|---|
| 758 | |
|---|
| 759 | #define read_c0_wired() __read_32bit_c0_register($6, 0) |
|---|
| 760 | #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) |
|---|
| 761 | |
|---|
| 762 | #define read_c0_info() __read_32bit_c0_register($7, 0) |
|---|
| 763 | |
|---|
| 764 | #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ |
|---|
| 765 | #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) |
|---|
| 766 | |
|---|
| 767 | #define read_c0_count() __read_32bit_c0_register($9, 0) |
|---|
| 768 | #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) |
|---|
| 769 | |
|---|
| 770 | #define read_c0_entryhi() __read_ulong_c0_register($10, 0) |
|---|
| 771 | #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) |
|---|
| 772 | |
|---|
| 773 | #define read_c0_compare() __read_32bit_c0_register($11, 0) |
|---|
| 774 | #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) |
|---|
| 775 | |
|---|
| 776 | #define read_c0_status() __read_32bit_c0_register($12, 0) |
|---|
| 777 | #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) |
|---|
| 778 | |
|---|
| 779 | #define read_c0_cause() __read_32bit_c0_register($13, 0) |
|---|
| 780 | #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) |
|---|
| 781 | |
|---|
| 782 | #define read_c0_epc() __read_ulong_c0_register($14, 0) |
|---|
| 783 | #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) |
|---|
| 784 | |
|---|
| 785 | #define read_c0_prid() __read_32bit_c0_register($15, 0) |
|---|
| 786 | |
|---|
| 787 | #define read_c0_config() __read_32bit_c0_register($16, 0) |
|---|
| 788 | #define read_c0_config1() __read_32bit_c0_register($16, 1) |
|---|
| 789 | #define read_c0_config2() __read_32bit_c0_register($16, 2) |
|---|
| 790 | #define read_c0_config3() __read_32bit_c0_register($16, 3) |
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| 791 | #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) |
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| 792 | #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) |
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| 793 | #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) |
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| 794 | #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) |
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| 795 | |
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| 796 | /* |
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| 797 | * The WatchLo register. There may be upto 8 of them. |
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| 798 | */ |
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| 799 | #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) |
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| 800 | #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) |
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| 801 | #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) |
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| 802 | #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) |
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| 803 | #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) |
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| 804 | #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) |
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| 805 | #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) |
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| 806 | #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) |
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| 807 | #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) |
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| 808 | #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) |
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| 809 | #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) |
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| 810 | #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) |
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| 811 | #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) |
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| 812 | #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) |
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| 813 | #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) |
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| 814 | #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) |
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| 815 | |
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| 816 | /* |
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| 817 | * The WatchHi register. There may be upto 8 of them. |
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| 818 | */ |
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| 819 | #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) |
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| 820 | #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) |
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| 821 | #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) |
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| 822 | #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) |
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| 823 | #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) |
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| 824 | #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) |
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| 825 | #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) |
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| 826 | #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) |
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| 827 | |
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| 828 | #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) |
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| 829 | #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) |
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| 830 | #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) |
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| 831 | #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) |
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| 832 | #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) |
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| 833 | #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) |
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| 834 | #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) |
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| 835 | #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) |
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| 836 | |
|---|
| 837 | #define read_c0_xcontext() __read_ulong_c0_register($20, 0) |
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| 838 | #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) |
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| 839 | |
|---|
| 840 | #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) |
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| 841 | #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) |
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| 842 | |
|---|
| 843 | #define read_c0_framemask() __read_32bit_c0_register($21, 0) |
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| 844 | #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) |
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| 845 | |
|---|
| 846 | /* RM9000 PerfControl performance counter control register */ |
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| 847 | #define read_c0_perfcontrol() __read_32bit_c0_register($22, 0) |
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| 848 | #define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val) |
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| 849 | |
|---|
| 850 | #define read_c0_diag() __read_32bit_c0_register($22, 0) |
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| 851 | #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) |
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| 852 | |
|---|
| 853 | #define read_c0_diag1() __read_32bit_c0_register($22, 1) |
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| 854 | #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) |
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| 855 | |
|---|
| 856 | #define read_c0_diag2() __read_32bit_c0_register($22, 2) |
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| 857 | #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) |
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| 858 | |
|---|
| 859 | #define read_c0_diag3() __read_32bit_c0_register($22, 3) |
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| 860 | #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) |
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| 861 | |
|---|
| 862 | #define read_c0_diag4() __read_32bit_c0_register($22, 4) |
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| 863 | #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) |
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| 864 | |
|---|
| 865 | #define read_c0_diag5() __read_32bit_c0_register($22, 5) |
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| 866 | #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) |
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| 867 | |
|---|
| 868 | #define read_c0_debug() __read_32bit_c0_register($23, 0) |
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| 869 | #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) |
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| 870 | |
|---|
| 871 | #define read_c0_depc() __read_ulong_c0_register($24, 0) |
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| 872 | #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) |
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| 873 | |
|---|
| 874 | /* |
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| 875 | * MIPS32 / MIPS64 performance counters |
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| 876 | */ |
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| 877 | #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) |
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| 878 | #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) |
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| 879 | #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) |
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| 880 | #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) |
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| 881 | #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) |
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| 882 | #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) |
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| 883 | #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) |
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| 884 | #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) |
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| 885 | #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) |
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| 886 | #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) |
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| 887 | #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) |
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| 888 | #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) |
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| 889 | #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) |
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| 890 | #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) |
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| 891 | #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) |
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| 892 | #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) |
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| 893 | |
|---|
| 894 | /* RM9000 PerfCount performance counter register */ |
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| 895 | #define read_c0_perfcount() __read_64bit_c0_register($25, 0) |
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| 896 | #define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val) |
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| 897 | |
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| 898 | #define read_c0_ecc() __read_32bit_c0_register($26, 0) |
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| 899 | #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) |
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| 900 | |
|---|
| 901 | #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) |
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| 902 | #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) |
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| 903 | |
|---|
| 904 | #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) |
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| 905 | |
|---|
| 906 | #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) |
|---|
| 907 | #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) |
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| 908 | |
|---|
| 909 | #define read_c0_taglo() __read_32bit_c0_register($28, 0) |
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| 910 | #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) |
|---|
| 911 | |
|---|
| 912 | #define read_c0_taghi() __read_32bit_c0_register($29, 0) |
|---|
| 913 | #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) |
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| 914 | |
|---|
| 915 | #define read_c0_errorepc() __read_ulong_c0_register($30, 0) |
|---|
| 916 | #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) |
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| 917 | |
|---|
| 918 | /* |
|---|
| 919 | * Macros to access the floating point coprocessor control registers |
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| 920 | */ |
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| 921 | #define read_32bit_cp1_register(source) \ |
|---|
| 922 | ({ int __res; \ |
|---|
| 923 | __asm__ __volatile__( \ |
|---|
| 924 | ".set\tpush\n\t" \ |
|---|
| 925 | ".set\treorder\n\t" \ |
|---|
| 926 | "cfc1\t%0,"STR(source)"\n\t" \ |
|---|
| 927 | ".set\tpop" \ |
|---|
| 928 | : "=r" (__res)); \ |
|---|
| 929 | __res;}) |
|---|
| 930 | |
|---|
| 931 | /* |
|---|
| 932 | * TLB operations. |
|---|
| 933 | * |
|---|
| 934 | * It is responsibility of the caller to take care of any TLB hazards. |
|---|
| 935 | */ |
|---|
| 936 | static inline void tlb_probe(void) |
|---|
| 937 | { |
|---|
| 938 | __asm__ __volatile__( |
|---|
| 939 | ".set noreorder\n\t" |
|---|
| 940 | "tlbp\n\t" |
|---|
| 941 | ".set reorder"); |
|---|
| 942 | } |
|---|
| 943 | |
|---|
| 944 | static inline void tlb_read(void) |
|---|
| 945 | { |
|---|
| 946 | __asm__ __volatile__( |
|---|
| 947 | ".set noreorder\n\t" |
|---|
| 948 | "tlbr\n\t" |
|---|
| 949 | ".set reorder"); |
|---|
| 950 | } |
|---|
| 951 | |
|---|
| 952 | static inline void tlb_write_indexed(void) |
|---|
| 953 | { |
|---|
| 954 | __asm__ __volatile__( |
|---|
| 955 | ".set noreorder\n\t" |
|---|
| 956 | "tlbwi\n\t" |
|---|
| 957 | ".set reorder"); |
|---|
| 958 | } |
|---|
| 959 | |
|---|
| 960 | static inline void tlb_write_random(void) |
|---|
| 961 | { |
|---|
| 962 | __asm__ __volatile__( |
|---|
| 963 | ".set noreorder\n\t" |
|---|
| 964 | "tlbwr\n\t" |
|---|
| 965 | ".set reorder"); |
|---|
| 966 | } |
|---|
| 967 | |
|---|
| 968 | /* |
|---|
| 969 | * Manipulate bits in a c0 register. |
|---|
| 970 | */ |
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| 971 | #define __BUILD_SET_C0(name) \ |
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| 972 | static inline unsigned int \ |
|---|
| 973 | set_c0_##name(unsigned int set) \ |
|---|
| 974 | { \ |
|---|
| 975 | unsigned int res; \ |
|---|
| 976 | \ |
|---|
| 977 | res = read_c0_##name(); \ |
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| 978 | res |= set; \ |
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| 979 | write_c0_##name(res); \ |
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| 980 | \ |
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| 981 | return res; \ |
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| 982 | } \ |
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| 983 | \ |
|---|
| 984 | static inline unsigned int \ |
|---|
| 985 | clear_c0_##name(unsigned int clear) \ |
|---|
| 986 | { \ |
|---|
| 987 | unsigned int res; \ |
|---|
| 988 | \ |
|---|
| 989 | res = read_c0_##name(); \ |
|---|
| 990 | res &= ~clear; \ |
|---|
| 991 | write_c0_##name(res); \ |
|---|
| 992 | \ |
|---|
| 993 | return res; \ |
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| 994 | } \ |
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| 995 | \ |
|---|
| 996 | static inline unsigned int \ |
|---|
| 997 | change_c0_##name(unsigned int change, unsigned int new) \ |
|---|
| 998 | { \ |
|---|
| 999 | unsigned int res; \ |
|---|
| 1000 | \ |
|---|
| 1001 | res = read_c0_##name(); \ |
|---|
| 1002 | res &= ~change; \ |
|---|
| 1003 | res |= (new & change); \ |
|---|
| 1004 | write_c0_##name(res); \ |
|---|
| 1005 | \ |
|---|
| 1006 | return res; \ |
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| 1007 | } |
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| 1008 | |
|---|
| 1009 | __BUILD_SET_C0(status) |
|---|
| 1010 | __BUILD_SET_C0(cause) |
|---|
| 1011 | __BUILD_SET_C0(config) |
|---|
| 1012 | __BUILD_SET_C0(intcontrol) |
|---|
| 1013 | |
|---|
| 1014 | #endif /* !__ASSEMBLY__ */ |
|---|
| 1015 | |
|---|
| 1016 | #endif /* _ASM_MIPSREGS_H */ |
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