| 1 | /* ********************************************************************* |
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| 2 | * SB1250 Board Support Package |
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| 3 | * |
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| 4 | * Register Definitions File: sb1250_regs.h |
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| 5 | * |
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| 6 | * This module contains the addresses of the on-chip peripherals |
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| 7 | * on the SB1250. |
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| 8 | * |
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| 9 | * SB1250 specification level: 01/02/2002 |
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| 10 | * |
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| 11 | * Author: Mitch Lichtenberg |
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| 12 | * |
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| 13 | ********************************************************************* |
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| 14 | * |
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| 15 | * Copyright 2000,2001,2002,2003 |
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| 16 | * Broadcom Corporation. All rights reserved. |
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| 17 | * |
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| 18 | * This program is free software; you can redistribute it and/or |
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| 19 | * modify it under the terms of the GNU General Public License as |
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| 20 | * published by the Free Software Foundation; either version 2 of |
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| 21 | * the License, or (at your option) any later version. |
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| 22 | * |
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| 23 | * This program is distributed in the hope that it will be useful, |
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| 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 26 | * GNU General Public License for more details. |
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| 27 | * |
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| 28 | * You should have received a copy of the GNU General Public License |
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| 29 | * along with this program; if not, write to the Free Software |
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| 30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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| 31 | * MA 02111-1307 USA |
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| 32 | ********************************************************************* */ |
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| 33 | |
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| 34 | |
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| 35 | #ifndef _SB1250_REGS_H |
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| 36 | #define _SB1250_REGS_H |
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| 37 | |
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| 38 | #include "sb1250_defs.h" |
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| 39 | |
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| 40 | |
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| 41 | /* ********************************************************************* |
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| 42 | * Some general notes: |
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| 43 | * |
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| 44 | * For the most part, when there is more than one peripheral |
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| 45 | * of the same type on the SOC, the constants below will be |
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| 46 | * offsets from the base of each peripheral. For example, |
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| 47 | * the MAC registers are described as offsets from the first |
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| 48 | * MAC register, and there will be a MAC_REGISTER() macro |
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| 49 | * to calculate the base address of a given MAC. |
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| 50 | * |
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| 51 | * The information in this file is based on the SB1250 SOC |
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| 52 | * manual version 0.2, July 2000. |
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| 53 | ********************************************************************* */ |
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| 54 | |
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| 55 | |
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| 56 | /* ********************************************************************* |
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| 57 | * Memory Controller Registers |
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| 58 | ********************************************************************* */ |
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| 59 | |
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| 60 | /* |
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| 61 | * XXX: can't remove MC base 0 if 112x, since it's used by other macros, |
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| 62 | * since there is one reg there (but it could get its addr/offset constant). |
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| 63 | */ |
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| 64 | #define A_MC_BASE_0 0x0010051000 |
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| 65 | #define A_MC_BASE_1 0x0010052000 |
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| 66 | #define MC_REGISTER_SPACING 0x1000 |
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| 67 | |
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| 68 | #define A_MC_BASE(ctlid) ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0) |
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| 69 | #define A_MC_REGISTER(ctlid,reg) (A_MC_BASE(ctlid)+(reg)) |
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| 70 | |
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| 71 | #define R_MC_CONFIG 0x0000000100 |
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| 72 | #define R_MC_DRAMCMD 0x0000000120 |
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| 73 | #define R_MC_DRAMMODE 0x0000000140 |
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| 74 | #define R_MC_TIMING1 0x0000000160 |
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| 75 | #define R_MC_TIMING2 0x0000000180 |
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| 76 | #define R_MC_CS_START 0x00000001A0 |
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| 77 | #define R_MC_CS_END 0x00000001C0 |
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| 78 | #define R_MC_CS_INTERLEAVE 0x00000001E0 |
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| 79 | #define S_MC_CS_STARTEND 16 |
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| 80 | |
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| 81 | #define R_MC_CSX_BASE 0x0000000200 |
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| 82 | #define R_MC_CSX_ROW 0x0000000000 /* relative to CSX_BASE, above */ |
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| 83 | #define R_MC_CSX_COL 0x0000000020 /* relative to CSX_BASE, above */ |
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| 84 | #define R_MC_CSX_BA 0x0000000040 /* relative to CSX_BASE, above */ |
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| 85 | #define MC_CSX_SPACING 0x0000000060 /* relative to CSX_BASE, above */ |
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| 86 | |
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| 87 | #define R_MC_CS0_ROW 0x0000000200 |
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| 88 | #define R_MC_CS0_COL 0x0000000220 |
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| 89 | #define R_MC_CS0_BA 0x0000000240 |
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| 90 | #define R_MC_CS1_ROW 0x0000000260 |
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| 91 | #define R_MC_CS1_COL 0x0000000280 |
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| 92 | #define R_MC_CS1_BA 0x00000002A0 |
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| 93 | #define R_MC_CS2_ROW 0x00000002C0 |
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| 94 | #define R_MC_CS2_COL 0x00000002E0 |
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| 95 | #define R_MC_CS2_BA 0x0000000300 |
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| 96 | #define R_MC_CS3_ROW 0x0000000320 |
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| 97 | #define R_MC_CS3_COL 0x0000000340 |
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| 98 | #define R_MC_CS3_BA 0x0000000360 |
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| 99 | #define R_MC_CS_ATTR 0x0000000380 |
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| 100 | #define R_MC_TEST_DATA 0x0000000400 |
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| 101 | #define R_MC_TEST_ECC 0x0000000420 |
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| 102 | #define R_MC_MCLK_CFG 0x0000000500 |
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| 103 | |
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| 104 | /* ********************************************************************* |
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| 105 | * L2 Cache Control Registers |
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| 106 | ********************************************************************* */ |
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| 107 | |
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| 108 | #define A_L2_READ_TAG 0x0010040018 |
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| 109 | #define A_L2_ECC_TAG 0x0010040038 |
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| 110 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 111 | #define A_L2_READ_MISC 0x0010040058 |
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| 112 | #endif /* 1250 PASS3 || 112x PASS1 */ |
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| 113 | #define A_L2_WAY_DISABLE 0x0010041000 |
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| 114 | #define A_L2_MAKEDISABLE(x) (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8)) |
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| 115 | #define A_L2_MGMT_TAG_BASE 0x00D0000000 |
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| 116 | |
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| 117 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 118 | #define A_L2_CACHE_DISABLE 0x0010042000 |
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| 119 | #define A_L2_MAKECACHEDISABLE(x) (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8)) |
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| 120 | #define A_L2_MISC_CONFIG 0x0010043000 |
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| 121 | #endif /* 1250 PASS2 || 112x PASS1 */ |
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| 122 | |
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| 123 | /* Backward-compatibility definitions. */ |
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| 124 | /* XXX: discourage people from using these constants. */ |
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| 125 | #define A_L2_READ_ADDRESS A_L2_READ_TAG |
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| 126 | #define A_L2_EEC_ADDRESS A_L2_ECC_TAG |
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| 127 | |
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| 128 | |
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| 129 | /* ********************************************************************* |
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| 130 | * PCI Interface Registers |
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| 131 | ********************************************************************* */ |
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| 132 | |
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| 133 | #define A_PCI_TYPE00_HEADER 0x00DE000000 |
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| 134 | #define A_PCI_TYPE01_HEADER 0x00DE000800 |
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| 135 | |
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| 136 | |
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| 137 | /* ********************************************************************* |
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| 138 | * Ethernet DMA and MACs |
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| 139 | ********************************************************************* */ |
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| 140 | |
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| 141 | #define A_MAC_BASE_0 0x0010064000 |
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| 142 | #define A_MAC_BASE_1 0x0010065000 |
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| 143 | #if SIBYTE_HDR_FEATURE_CHIP(1250) |
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| 144 | #define A_MAC_BASE_2 0x0010066000 |
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| 145 | #endif /* 1250 */ |
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| 146 | |
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| 147 | #define MAC_SPACING 0x1000 |
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| 148 | #define MAC_DMA_TXRX_SPACING 0x0400 |
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| 149 | #define MAC_DMA_CHANNEL_SPACING 0x0100 |
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| 150 | #define DMA_RX 0 |
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| 151 | #define DMA_TX 1 |
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| 152 | #define MAC_NUM_DMACHAN 2 /* channels per direction */ |
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| 153 | |
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| 154 | /* XXX: not correct; depends on SOC type. */ |
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| 155 | #define MAC_NUM_PORTS 3 |
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| 156 | |
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| 157 | #define A_MAC_CHANNEL_BASE(macnum) \ |
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| 158 | (A_MAC_BASE_0 + \ |
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| 159 | MAC_SPACING*(macnum)) |
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| 160 | |
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| 161 | #define A_MAC_REGISTER(macnum,reg) \ |
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| 162 | (A_MAC_BASE_0 + \ |
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| 163 | MAC_SPACING*(macnum) + (reg)) |
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| 164 | |
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| 165 | |
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| 166 | #define R_MAC_DMA_CHANNELS 0x800 /* Relative to A_MAC_CHANNEL_BASE */ |
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| 167 | |
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| 168 | #define A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) \ |
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| 169 | ((A_MAC_CHANNEL_BASE(macnum)) + \ |
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| 170 | R_MAC_DMA_CHANNELS + \ |
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| 171 | (MAC_DMA_TXRX_SPACING*(txrx)) + \ |
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| 172 | (MAC_DMA_CHANNEL_SPACING*(chan))) |
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| 173 | |
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| 174 | #define R_MAC_DMA_CHANNEL_BASE(txrx,chan) \ |
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| 175 | (R_MAC_DMA_CHANNELS + \ |
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| 176 | (MAC_DMA_TXRX_SPACING*(txrx)) + \ |
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| 177 | (MAC_DMA_CHANNEL_SPACING*(chan))) |
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| 178 | |
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| 179 | #define A_MAC_DMA_REGISTER(macnum,txrx,chan,reg) \ |
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| 180 | (A_MAC_DMA_CHANNEL_BASE(macnum,txrx,chan) + \ |
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| 181 | (reg)) |
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| 182 | |
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| 183 | #define R_MAC_DMA_REGISTER(txrx,chan,reg) \ |
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| 184 | (R_MAC_DMA_CHANNEL_BASE(txrx,chan) + \ |
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| 185 | (reg)) |
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| 186 | |
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| 187 | /* |
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| 188 | * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE |
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| 189 | */ |
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| 190 | |
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| 191 | #define R_MAC_DMA_CONFIG0 0x00000000 |
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| 192 | #define R_MAC_DMA_CONFIG1 0x00000008 |
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| 193 | #define R_MAC_DMA_DSCR_BASE 0x00000010 |
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| 194 | #define R_MAC_DMA_DSCR_CNT 0x00000018 |
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| 195 | #define R_MAC_DMA_CUR_DSCRA 0x00000020 |
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| 196 | #define R_MAC_DMA_CUR_DSCRB 0x00000028 |
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| 197 | #define R_MAC_DMA_CUR_DSCRADDR 0x00000030 |
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| 198 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 199 | #define R_MAC_DMA_OODPKTLOST_RX 0x00000038 /* rx only */ |
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| 200 | #endif /* 1250 PASS3 || 112x PASS1 */ |
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| 201 | |
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| 202 | /* |
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| 203 | * RMON Counters |
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| 204 | */ |
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| 205 | |
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| 206 | #define R_MAC_RMON_TX_BYTES 0x00000000 |
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| 207 | #define R_MAC_RMON_COLLISIONS 0x00000008 |
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| 208 | #define R_MAC_RMON_LATE_COL 0x00000010 |
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| 209 | #define R_MAC_RMON_EX_COL 0x00000018 |
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| 210 | #define R_MAC_RMON_FCS_ERROR 0x00000020 |
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| 211 | #define R_MAC_RMON_TX_ABORT 0x00000028 |
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| 212 | /* Counter #6 (0x30) now reserved */ |
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| 213 | #define R_MAC_RMON_TX_BAD 0x00000038 |
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| 214 | #define R_MAC_RMON_TX_GOOD 0x00000040 |
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| 215 | #define R_MAC_RMON_TX_RUNT 0x00000048 |
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| 216 | #define R_MAC_RMON_TX_OVERSIZE 0x00000050 |
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| 217 | #define R_MAC_RMON_RX_BYTES 0x00000080 |
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| 218 | #define R_MAC_RMON_RX_MCAST 0x00000088 |
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| 219 | #define R_MAC_RMON_RX_BCAST 0x00000090 |
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| 220 | #define R_MAC_RMON_RX_BAD 0x00000098 |
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| 221 | #define R_MAC_RMON_RX_GOOD 0x000000A0 |
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| 222 | #define R_MAC_RMON_RX_RUNT 0x000000A8 |
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| 223 | #define R_MAC_RMON_RX_OVERSIZE 0x000000B0 |
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| 224 | #define R_MAC_RMON_RX_FCS_ERROR 0x000000B8 |
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| 225 | #define R_MAC_RMON_RX_LENGTH_ERROR 0x000000C0 |
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| 226 | #define R_MAC_RMON_RX_CODE_ERROR 0x000000C8 |
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| 227 | #define R_MAC_RMON_RX_ALIGN_ERROR 0x000000D0 |
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| 228 | |
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| 229 | /* Updated to spec 0.2 */ |
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| 230 | #define R_MAC_CFG 0x00000100 |
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| 231 | #define R_MAC_THRSH_CFG 0x00000108 |
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| 232 | #define R_MAC_VLANTAG 0x00000110 |
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| 233 | #define R_MAC_FRAMECFG 0x00000118 |
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| 234 | #define R_MAC_EOPCNT 0x00000120 |
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| 235 | #define R_MAC_FIFO_PTRS 0x00000130 |
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| 236 | #define R_MAC_ADFILTER_CFG 0x00000200 |
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| 237 | #define R_MAC_ETHERNET_ADDR 0x00000208 |
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| 238 | #define R_MAC_PKT_TYPE 0x00000210 |
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| 239 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 240 | #define R_MAC_ADMASK0 0x00000218 |
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| 241 | #define R_MAC_ADMASK1 0x00000220 |
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| 242 | #endif /* 1250 PASS3 || 112x PASS1 */ |
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| 243 | #define R_MAC_HASH_BASE 0x00000240 |
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| 244 | #define R_MAC_ADDR_BASE 0x00000280 |
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| 245 | #define R_MAC_CHLO0_BASE 0x00000300 |
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| 246 | #define R_MAC_CHUP0_BASE 0x00000320 |
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| 247 | #define R_MAC_ENABLE 0x00000400 |
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| 248 | #define R_MAC_STATUS 0x00000408 |
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| 249 | #define R_MAC_INT_MASK 0x00000410 |
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| 250 | #define R_MAC_TXD_CTL 0x00000420 |
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| 251 | #define R_MAC_MDIO 0x00000428 |
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| 252 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 253 | #define R_MAC_STATUS1 0x00000430 |
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| 254 | #endif /* 1250 PASS2 || 112x PASS1 */ |
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| 255 | #define R_MAC_DEBUG_STATUS 0x00000448 |
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| 256 | |
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| 257 | #define MAC_HASH_COUNT 8 |
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| 258 | #define MAC_ADDR_COUNT 8 |
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| 259 | #define MAC_CHMAP_COUNT 4 |
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| 260 | |
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| 261 | |
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| 262 | /* ********************************************************************* |
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| 263 | * DUART Registers |
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| 264 | ********************************************************************* */ |
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| 265 | |
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| 266 | |
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| 267 | #define R_DUART_NUM_PORTS 2 |
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| 268 | |
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| 269 | #define A_DUART 0x0010060000 |
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| 270 | |
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| 271 | #define A_DUART_REG(r) |
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| 272 | |
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| 273 | #define DUART_CHANREG_SPACING 0x100 |
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| 274 | #define A_DUART_CHANREG(chan,reg) (A_DUART + DUART_CHANREG_SPACING*(chan) + (reg)) |
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| 275 | #define R_DUART_CHANREG(chan,reg) (DUART_CHANREG_SPACING*(chan) + (reg)) |
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| 276 | |
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| 277 | #define R_DUART_MODE_REG_1 0x100 |
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| 278 | #define R_DUART_MODE_REG_2 0x110 |
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| 279 | #define R_DUART_STATUS 0x120 |
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| 280 | #define R_DUART_CLK_SEL 0x130 |
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| 281 | #define R_DUART_CMD 0x150 |
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| 282 | #define R_DUART_RX_HOLD 0x160 |
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| 283 | #define R_DUART_TX_HOLD 0x170 |
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| 284 | |
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| 285 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 286 | #define R_DUART_FULL_CTL 0x140 |
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| 287 | #define R_DUART_OPCR_X 0x180 |
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| 288 | #define R_DUART_AUXCTL_X 0x190 |
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| 289 | #endif /* 1250 PASS2 || 112x PASS1 */ |
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| 290 | |
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| 291 | |
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| 292 | /* |
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| 293 | * The IMR and ISR can't be addressed with A_DUART_CHANREG, |
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| 294 | * so use this macro instead. |
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| 295 | */ |
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| 296 | |
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| 297 | #define R_DUART_AUX_CTRL 0x310 |
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| 298 | #define R_DUART_ISR_A 0x320 |
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| 299 | #define R_DUART_IMR_A 0x330 |
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| 300 | #define R_DUART_ISR_B 0x340 |
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| 301 | #define R_DUART_IMR_B 0x350 |
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| 302 | #define R_DUART_OUT_PORT 0x360 |
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| 303 | #define R_DUART_OPCR 0x370 |
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| 304 | |
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| 305 | #define R_DUART_SET_OPR 0x3B0 |
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| 306 | #define R_DUART_CLEAR_OPR 0x3C0 |
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| 307 | |
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| 308 | #define DUART_IMRISR_SPACING 0x20 |
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| 309 | |
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| 310 | #define R_DUART_IMRREG(chan) (R_DUART_IMR_A + (chan)*DUART_IMRISR_SPACING) |
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| 311 | #define R_DUART_ISRREG(chan) (R_DUART_ISR_A + (chan)*DUART_IMRISR_SPACING) |
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| 312 | |
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| 313 | #define A_DUART_IMRREG(chan) (A_DUART + R_DUART_IMRREG(chan)) |
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| 314 | #define A_DUART_ISRREG(chan) (A_DUART + R_DUART_ISRREG(chan)) |
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| 315 | |
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| 316 | |
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| 317 | |
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| 318 | |
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| 319 | /* |
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| 320 | * These constants are the absolute addresses. |
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| 321 | */ |
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| 322 | |
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| 323 | #define A_DUART_MODE_REG_1_A 0x0010060100 |
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| 324 | #define A_DUART_MODE_REG_2_A 0x0010060110 |
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| 325 | #define A_DUART_STATUS_A 0x0010060120 |
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| 326 | #define A_DUART_CLK_SEL_A 0x0010060130 |
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| 327 | #define A_DUART_CMD_A 0x0010060150 |
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| 328 | #define A_DUART_RX_HOLD_A 0x0010060160 |
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| 329 | #define A_DUART_TX_HOLD_A 0x0010060170 |
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| 330 | |
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| 331 | #define A_DUART_MODE_REG_1_B 0x0010060200 |
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| 332 | #define A_DUART_MODE_REG_2_B 0x0010060210 |
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| 333 | #define A_DUART_STATUS_B 0x0010060220 |
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| 334 | #define A_DUART_CLK_SEL_B 0x0010060230 |
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| 335 | #define A_DUART_CMD_B 0x0010060250 |
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| 336 | #define A_DUART_RX_HOLD_B 0x0010060260 |
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| 337 | #define A_DUART_TX_HOLD_B 0x0010060270 |
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| 338 | |
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| 339 | #define A_DUART_INPORT_CHNG 0x0010060300 |
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| 340 | #define A_DUART_AUX_CTRL 0x0010060310 |
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| 341 | #define A_DUART_ISR_A 0x0010060320 |
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| 342 | #define A_DUART_IMR_A 0x0010060330 |
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| 343 | #define A_DUART_ISR_B 0x0010060340 |
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| 344 | #define A_DUART_IMR_B 0x0010060350 |
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| 345 | #define A_DUART_OUT_PORT 0x0010060360 |
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| 346 | #define A_DUART_OPCR 0x0010060370 |
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| 347 | #define A_DUART_IN_PORT 0x0010060380 |
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| 348 | #define A_DUART_ISR 0x0010060390 |
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| 349 | #define A_DUART_IMR 0x00100603A0 |
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| 350 | #define A_DUART_SET_OPR 0x00100603B0 |
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| 351 | #define A_DUART_CLEAR_OPR 0x00100603C0 |
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| 352 | #define A_DUART_INPORT_CHNG_A 0x00100603D0 |
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| 353 | #define A_DUART_INPORT_CHNG_B 0x00100603E0 |
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| 354 | |
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| 355 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 356 | #define A_DUART_FULL_CTL_A 0x0010060140 |
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| 357 | #define A_DUART_FULL_CTL_B 0x0010060240 |
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| 358 | |
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| 359 | #define A_DUART_OPCR_A 0x0010060180 |
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| 360 | #define A_DUART_OPCR_B 0x0010060280 |
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| 361 | |
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| 362 | #define A_DUART_INPORT_CHNG_DEBUG 0x00100603F0 |
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| 363 | #endif /* 1250 PASS2 || 112x PASS1 */ |
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| 364 | |
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| 365 | |
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| 366 | /* ********************************************************************* |
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| 367 | * Synchronous Serial Registers |
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| 368 | ********************************************************************* */ |
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| 369 | |
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| 370 | |
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| 371 | #define A_SER_BASE_0 0x0010060400 |
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| 372 | #define A_SER_BASE_1 0x0010060800 |
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| 373 | #define SER_SPACING 0x400 |
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| 374 | |
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| 375 | #define SER_DMA_TXRX_SPACING 0x80 |
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| 376 | |
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| 377 | #define SER_NUM_PORTS 2 |
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| 378 | |
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| 379 | #define A_SER_CHANNEL_BASE(sernum) \ |
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| 380 | (A_SER_BASE_0 + \ |
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| 381 | SER_SPACING*(sernum)) |
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| 382 | |
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| 383 | #define A_SER_REGISTER(sernum,reg) \ |
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| 384 | (A_SER_BASE_0 + \ |
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| 385 | SER_SPACING*(sernum) + (reg)) |
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| 386 | |
|---|
| 387 | |
|---|
| 388 | #define R_SER_DMA_CHANNELS 0 /* Relative to A_SER_BASE_x */ |
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| 389 | |
|---|
| 390 | #define A_SER_DMA_CHANNEL_BASE(sernum,txrx) \ |
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| 391 | ((A_SER_CHANNEL_BASE(sernum)) + \ |
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| 392 | R_SER_DMA_CHANNELS + \ |
|---|
| 393 | (SER_DMA_TXRX_SPACING*(txrx))) |
|---|
| 394 | |
|---|
| 395 | #define A_SER_DMA_REGISTER(sernum,txrx,reg) \ |
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| 396 | (A_SER_DMA_CHANNEL_BASE(sernum,txrx) + \ |
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| 397 | (reg)) |
|---|
| 398 | |
|---|
| 399 | |
|---|
| 400 | /* |
|---|
| 401 | * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE |
|---|
| 402 | */ |
|---|
| 403 | |
|---|
| 404 | #define R_SER_DMA_CONFIG0 0x00000000 |
|---|
| 405 | #define R_SER_DMA_CONFIG1 0x00000008 |
|---|
| 406 | #define R_SER_DMA_DSCR_BASE 0x00000010 |
|---|
| 407 | #define R_SER_DMA_DSCR_CNT 0x00000018 |
|---|
| 408 | #define R_SER_DMA_CUR_DSCRA 0x00000020 |
|---|
| 409 | #define R_SER_DMA_CUR_DSCRB 0x00000028 |
|---|
| 410 | #define R_SER_DMA_CUR_DSCRADDR 0x00000030 |
|---|
| 411 | |
|---|
| 412 | #define R_SER_DMA_CONFIG0_RX 0x00000000 |
|---|
| 413 | #define R_SER_DMA_CONFIG1_RX 0x00000008 |
|---|
| 414 | #define R_SER_DMA_DSCR_BASE_RX 0x00000010 |
|---|
| 415 | #define R_SER_DMA_DSCR_COUNT_RX 0x00000018 |
|---|
| 416 | #define R_SER_DMA_CUR_DSCR_A_RX 0x00000020 |
|---|
| 417 | #define R_SER_DMA_CUR_DSCR_B_RX 0x00000028 |
|---|
| 418 | #define R_SER_DMA_CUR_DSCR_ADDR_RX 0x00000030 |
|---|
| 419 | |
|---|
| 420 | #define R_SER_DMA_CONFIG0_TX 0x00000080 |
|---|
| 421 | #define R_SER_DMA_CONFIG1_TX 0x00000088 |
|---|
| 422 | #define R_SER_DMA_DSCR_BASE_TX 0x00000090 |
|---|
| 423 | #define R_SER_DMA_DSCR_COUNT_TX 0x00000098 |
|---|
| 424 | #define R_SER_DMA_CUR_DSCR_A_TX 0x000000A0 |
|---|
| 425 | #define R_SER_DMA_CUR_DSCR_B_TX 0x000000A8 |
|---|
| 426 | #define R_SER_DMA_CUR_DSCR_ADDR_TX 0x000000B0 |
|---|
| 427 | |
|---|
| 428 | #define R_SER_MODE 0x00000100 |
|---|
| 429 | #define R_SER_MINFRM_SZ 0x00000108 |
|---|
| 430 | #define R_SER_MAXFRM_SZ 0x00000110 |
|---|
| 431 | #define R_SER_ADDR 0x00000118 |
|---|
| 432 | #define R_SER_USR0_ADDR 0x00000120 |
|---|
| 433 | #define R_SER_USR1_ADDR 0x00000128 |
|---|
| 434 | #define R_SER_USR2_ADDR 0x00000130 |
|---|
| 435 | #define R_SER_USR3_ADDR 0x00000138 |
|---|
| 436 | #define R_SER_CMD 0x00000140 |
|---|
| 437 | #define R_SER_TX_RD_THRSH 0x00000160 |
|---|
| 438 | #define R_SER_TX_WR_THRSH 0x00000168 |
|---|
| 439 | #define R_SER_RX_RD_THRSH 0x00000170 |
|---|
| 440 | #define R_SER_LINE_MODE 0x00000178 |
|---|
| 441 | #define R_SER_DMA_ENABLE 0x00000180 |
|---|
| 442 | #define R_SER_INT_MASK 0x00000190 |
|---|
| 443 | #define R_SER_STATUS 0x00000188 |
|---|
| 444 | #define R_SER_STATUS_DEBUG 0x000001A8 |
|---|
| 445 | #define R_SER_RX_TABLE_BASE 0x00000200 |
|---|
| 446 | #define SER_RX_TABLE_COUNT 16 |
|---|
| 447 | #define R_SER_TX_TABLE_BASE 0x00000300 |
|---|
| 448 | #define SER_TX_TABLE_COUNT 16 |
|---|
| 449 | |
|---|
| 450 | /* RMON Counters */ |
|---|
| 451 | #define R_SER_RMON_TX_BYTE_LO 0x000001C0 |
|---|
| 452 | #define R_SER_RMON_TX_BYTE_HI 0x000001C8 |
|---|
| 453 | #define R_SER_RMON_RX_BYTE_LO 0x000001D0 |
|---|
| 454 | #define R_SER_RMON_RX_BYTE_HI 0x000001D8 |
|---|
| 455 | #define R_SER_RMON_TX_UNDERRUN 0x000001E0 |
|---|
| 456 | #define R_SER_RMON_RX_OVERFLOW 0x000001E8 |
|---|
| 457 | #define R_SER_RMON_RX_ERRORS 0x000001F0 |
|---|
| 458 | #define R_SER_RMON_RX_BADADDR 0x000001F8 |
|---|
| 459 | |
|---|
| 460 | /* ********************************************************************* |
|---|
| 461 | * Generic Bus Registers |
|---|
| 462 | ********************************************************************* */ |
|---|
| 463 | |
|---|
| 464 | #define IO_EXT_CFG_COUNT 8 |
|---|
| 465 | |
|---|
| 466 | #define A_IO_EXT_BASE 0x0010061000 |
|---|
| 467 | #define A_IO_EXT_REG(r) (A_IO_EXT_BASE + (r)) |
|---|
| 468 | |
|---|
| 469 | #define A_IO_EXT_CFG_BASE 0x0010061000 |
|---|
| 470 | #define A_IO_EXT_MULT_SIZE_BASE 0x0010061100 |
|---|
| 471 | #define A_IO_EXT_START_ADDR_BASE 0x0010061200 |
|---|
| 472 | #define A_IO_EXT_TIME_CFG0_BASE 0x0010061600 |
|---|
| 473 | #define A_IO_EXT_TIME_CFG1_BASE 0x0010061700 |
|---|
| 474 | |
|---|
| 475 | #define IO_EXT_REGISTER_SPACING 8 |
|---|
| 476 | #define A_IO_EXT_CS_BASE(cs) (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs)) |
|---|
| 477 | #define R_IO_EXT_REG(reg,cs) ((cs)*IO_EXT_REGISTER_SPACING + (reg)) |
|---|
| 478 | |
|---|
| 479 | #define R_IO_EXT_CFG 0x0000 |
|---|
| 480 | #define R_IO_EXT_MULT_SIZE 0x0100 |
|---|
| 481 | #define R_IO_EXT_START_ADDR 0x0200 |
|---|
| 482 | #define R_IO_EXT_TIME_CFG0 0x0600 |
|---|
| 483 | #define R_IO_EXT_TIME_CFG1 0x0700 |
|---|
| 484 | |
|---|
| 485 | |
|---|
| 486 | #define A_IO_INTERRUPT_STATUS 0x0010061A00 |
|---|
| 487 | #define A_IO_INTERRUPT_DATA0 0x0010061A10 |
|---|
| 488 | #define A_IO_INTERRUPT_DATA1 0x0010061A18 |
|---|
| 489 | #define A_IO_INTERRUPT_DATA2 0x0010061A20 |
|---|
| 490 | #define A_IO_INTERRUPT_DATA3 0x0010061A28 |
|---|
| 491 | #define A_IO_INTERRUPT_ADDR0 0x0010061A30 |
|---|
| 492 | #define A_IO_INTERRUPT_ADDR1 0x0010061A40 |
|---|
| 493 | #define A_IO_INTERRUPT_PARITY 0x0010061A50 |
|---|
| 494 | #define A_IO_PCMCIA_CFG 0x0010061A60 |
|---|
| 495 | #define A_IO_PCMCIA_STATUS 0x0010061A70 |
|---|
| 496 | #define A_IO_DRIVE_0 0x0010061300 |
|---|
| 497 | #define A_IO_DRIVE_1 0x0010061308 |
|---|
| 498 | #define A_IO_DRIVE_2 0x0010061310 |
|---|
| 499 | #define A_IO_DRIVE_3 0x0010061318 |
|---|
| 500 | #define A_IO_DRIVE_BASE A_IO_DRIVE_0 |
|---|
| 501 | #define IO_DRIVE_REGISTER_SPACING 8 |
|---|
| 502 | #define R_IO_DRIVE(x) ((x)*IO_DRIVE_REGISTER_SPACING) |
|---|
| 503 | #define A_IO_DRIVE(x) (A_IO_DRIVE_BASE + R_IO_DRIVE(x)) |
|---|
| 504 | |
|---|
| 505 | #define R_IO_INTERRUPT_STATUS 0x0A00 |
|---|
| 506 | #define R_IO_INTERRUPT_DATA0 0x0A10 |
|---|
| 507 | #define R_IO_INTERRUPT_DATA1 0x0A18 |
|---|
| 508 | #define R_IO_INTERRUPT_DATA2 0x0A20 |
|---|
| 509 | #define R_IO_INTERRUPT_DATA3 0x0A28 |
|---|
| 510 | #define R_IO_INTERRUPT_ADDR0 0x0A30 |
|---|
| 511 | #define R_IO_INTERRUPT_ADDR1 0x0A40 |
|---|
| 512 | #define R_IO_INTERRUPT_PARITY 0x0A50 |
|---|
| 513 | #define R_IO_PCMCIA_CFG 0x0A60 |
|---|
| 514 | #define R_IO_PCMCIA_STATUS 0x0A70 |
|---|
| 515 | |
|---|
| 516 | /* ********************************************************************* |
|---|
| 517 | * GPIO Registers |
|---|
| 518 | ********************************************************************* */ |
|---|
| 519 | |
|---|
| 520 | #define A_GPIO_CLR_EDGE 0x0010061A80 |
|---|
| 521 | #define A_GPIO_INT_TYPE 0x0010061A88 |
|---|
| 522 | #define A_GPIO_INPUT_INVERT 0x0010061A90 |
|---|
| 523 | #define A_GPIO_GLITCH 0x0010061A98 |
|---|
| 524 | #define A_GPIO_READ 0x0010061AA0 |
|---|
| 525 | #define A_GPIO_DIRECTION 0x0010061AA8 |
|---|
| 526 | #define A_GPIO_PIN_CLR 0x0010061AB0 |
|---|
| 527 | #define A_GPIO_PIN_SET 0x0010061AB8 |
|---|
| 528 | |
|---|
| 529 | #define A_GPIO_BASE 0x0010061A80 |
|---|
| 530 | |
|---|
| 531 | #define R_GPIO_CLR_EDGE 0x00 |
|---|
| 532 | #define R_GPIO_INT_TYPE 0x08 |
|---|
| 533 | #define R_GPIO_INPUT_INVERT 0x10 |
|---|
| 534 | #define R_GPIO_GLITCH 0x18 |
|---|
| 535 | #define R_GPIO_READ 0x20 |
|---|
| 536 | #define R_GPIO_DIRECTION 0x28 |
|---|
| 537 | #define R_GPIO_PIN_CLR 0x30 |
|---|
| 538 | #define R_GPIO_PIN_SET 0x38 |
|---|
| 539 | |
|---|
| 540 | /* ********************************************************************* |
|---|
| 541 | * SMBus Registers |
|---|
| 542 | ********************************************************************* */ |
|---|
| 543 | |
|---|
| 544 | #define A_SMB_XTRA_0 0x0010060000 |
|---|
| 545 | #define A_SMB_XTRA_1 0x0010060008 |
|---|
| 546 | #define A_SMB_FREQ_0 0x0010060010 |
|---|
| 547 | #define A_SMB_FREQ_1 0x0010060018 |
|---|
| 548 | #define A_SMB_STATUS_0 0x0010060020 |
|---|
| 549 | #define A_SMB_STATUS_1 0x0010060028 |
|---|
| 550 | #define A_SMB_CMD_0 0x0010060030 |
|---|
| 551 | #define A_SMB_CMD_1 0x0010060038 |
|---|
| 552 | #define A_SMB_START_0 0x0010060040 |
|---|
| 553 | #define A_SMB_START_1 0x0010060048 |
|---|
| 554 | #define A_SMB_DATA_0 0x0010060050 |
|---|
| 555 | #define A_SMB_DATA_1 0x0010060058 |
|---|
| 556 | #define A_SMB_CONTROL_0 0x0010060060 |
|---|
| 557 | #define A_SMB_CONTROL_1 0x0010060068 |
|---|
| 558 | #define A_SMB_PEC_0 0x0010060070 |
|---|
| 559 | #define A_SMB_PEC_1 0x0010060078 |
|---|
| 560 | |
|---|
| 561 | #define A_SMB_0 0x0010060000 |
|---|
| 562 | #define A_SMB_1 0x0010060008 |
|---|
| 563 | #define SMB_REGISTER_SPACING 0x8 |
|---|
| 564 | #define A_SMB_BASE(idx) (A_SMB_0+(idx)*SMB_REGISTER_SPACING) |
|---|
| 565 | #define A_SMB_REGISTER(idx,reg) (A_SMB_BASE(idx)+(reg)) |
|---|
| 566 | |
|---|
| 567 | #define R_SMB_XTRA 0x0000000000 |
|---|
| 568 | #define R_SMB_FREQ 0x0000000010 |
|---|
| 569 | #define R_SMB_STATUS 0x0000000020 |
|---|
| 570 | #define R_SMB_CMD 0x0000000030 |
|---|
| 571 | #define R_SMB_START 0x0000000040 |
|---|
| 572 | #define R_SMB_DATA 0x0000000050 |
|---|
| 573 | #define R_SMB_CONTROL 0x0000000060 |
|---|
| 574 | #define R_SMB_PEC 0x0000000070 |
|---|
| 575 | |
|---|
| 576 | /* ********************************************************************* |
|---|
| 577 | * Timer Registers |
|---|
| 578 | ********************************************************************* */ |
|---|
| 579 | |
|---|
| 580 | /* |
|---|
| 581 | * Watchdog timers |
|---|
| 582 | */ |
|---|
| 583 | |
|---|
| 584 | #define A_SCD_WDOG_0 0x0010020050 |
|---|
| 585 | #define A_SCD_WDOG_1 0x0010020150 |
|---|
| 586 | #define SCD_WDOG_SPACING 0x100 |
|---|
| 587 | #define SCD_NUM_WDOGS 2 |
|---|
| 588 | #define A_SCD_WDOG_BASE(w) (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w)) |
|---|
| 589 | #define A_SCD_WDOG_REGISTER(w,r) (A_SCD_WDOG_BASE(w) + (r)) |
|---|
| 590 | |
|---|
| 591 | #define R_SCD_WDOG_INIT 0x0000000000 |
|---|
| 592 | #define R_SCD_WDOG_CNT 0x0000000008 |
|---|
| 593 | #define R_SCD_WDOG_CFG 0x0000000010 |
|---|
| 594 | |
|---|
| 595 | #define A_SCD_WDOG_INIT_0 0x0010020050 |
|---|
| 596 | #define A_SCD_WDOG_CNT_0 0x0010020058 |
|---|
| 597 | #define A_SCD_WDOG_CFG_0 0x0010020060 |
|---|
| 598 | |
|---|
| 599 | #define A_SCD_WDOG_INIT_1 0x0010020150 |
|---|
| 600 | #define A_SCD_WDOG_CNT_1 0x0010020158 |
|---|
| 601 | #define A_SCD_WDOG_CFG_1 0x0010020160 |
|---|
| 602 | |
|---|
| 603 | /* |
|---|
| 604 | * Generic timers |
|---|
| 605 | */ |
|---|
| 606 | |
|---|
| 607 | #define A_SCD_TIMER_0 0x0010020070 |
|---|
| 608 | #define A_SCD_TIMER_1 0x0010020078 |
|---|
| 609 | #define A_SCD_TIMER_2 0x0010020170 |
|---|
| 610 | #define A_SCD_TIMER_3 0x0010020178 |
|---|
| 611 | #define SCD_NUM_TIMERS 4 |
|---|
| 612 | #define A_SCD_TIMER_BASE(w) (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1)) |
|---|
| 613 | #define A_SCD_TIMER_REGISTER(w,r) (A_SCD_TIMER_BASE(w) + (r)) |
|---|
| 614 | |
|---|
| 615 | #define R_SCD_TIMER_INIT 0x0000000000 |
|---|
| 616 | #define R_SCD_TIMER_CNT 0x0000000010 |
|---|
| 617 | #define R_SCD_TIMER_CFG 0x0000000020 |
|---|
| 618 | |
|---|
| 619 | #define A_SCD_TIMER_INIT_0 0x0010020070 |
|---|
| 620 | #define A_SCD_TIMER_CNT_0 0x0010020080 |
|---|
| 621 | #define A_SCD_TIMER_CFG_0 0x0010020090 |
|---|
| 622 | |
|---|
| 623 | #define A_SCD_TIMER_INIT_1 0x0010020078 |
|---|
| 624 | #define A_SCD_TIMER_CNT_1 0x0010020088 |
|---|
| 625 | #define A_SCD_TIMER_CFG_1 0x0010020098 |
|---|
| 626 | |
|---|
| 627 | #define A_SCD_TIMER_INIT_2 0x0010020170 |
|---|
| 628 | #define A_SCD_TIMER_CNT_2 0x0010020180 |
|---|
| 629 | #define A_SCD_TIMER_CFG_2 0x0010020190 |
|---|
| 630 | |
|---|
| 631 | #define A_SCD_TIMER_INIT_3 0x0010020178 |
|---|
| 632 | #define A_SCD_TIMER_CNT_3 0x0010020188 |
|---|
| 633 | #define A_SCD_TIMER_CFG_3 0x0010020198 |
|---|
| 634 | |
|---|
| 635 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
|---|
| 636 | #define A_SCD_SCRATCH 0x0010020C10 |
|---|
| 637 | |
|---|
| 638 | #define A_SCD_ZBBUS_CYCLE_COUNT 0x0010030000 |
|---|
| 639 | #define A_SCD_ZBBUS_CYCLE_CP0 0x0010020C00 |
|---|
| 640 | #define A_SCD_ZBBUS_CYCLE_CP1 0x0010020C08 |
|---|
| 641 | #endif /* 1250 PASS2 || 112x PASS1 */ |
|---|
| 642 | |
|---|
| 643 | |
|---|
| 644 | /* ********************************************************************* |
|---|
| 645 | * System Control Registers |
|---|
| 646 | ********************************************************************* */ |
|---|
| 647 | |
|---|
| 648 | #define A_SCD_SYSTEM_REVISION 0x0010020000 |
|---|
| 649 | #define A_SCD_SYSTEM_CFG 0x0010020008 |
|---|
| 650 | #define A_SCD_SYSTEM_MANUF 0x0010038000 |
|---|
| 651 | |
|---|
| 652 | /* ********************************************************************* |
|---|
| 653 | * System Address Trap Registers |
|---|
| 654 | ********************************************************************* */ |
|---|
| 655 | |
|---|
| 656 | #define A_ADDR_TRAP_INDEX 0x00100200B0 |
|---|
| 657 | #define A_ADDR_TRAP_REG 0x00100200B8 |
|---|
| 658 | #define A_ADDR_TRAP_UP_0 0x0010020400 |
|---|
| 659 | #define A_ADDR_TRAP_UP_1 0x0010020408 |
|---|
| 660 | #define A_ADDR_TRAP_UP_2 0x0010020410 |
|---|
| 661 | #define A_ADDR_TRAP_UP_3 0x0010020418 |
|---|
| 662 | #define A_ADDR_TRAP_DOWN_0 0x0010020420 |
|---|
| 663 | #define A_ADDR_TRAP_DOWN_1 0x0010020428 |
|---|
| 664 | #define A_ADDR_TRAP_DOWN_2 0x0010020430 |
|---|
| 665 | #define A_ADDR_TRAP_DOWN_3 0x0010020438 |
|---|
| 666 | #define A_ADDR_TRAP_CFG_0 0x0010020440 |
|---|
| 667 | #define A_ADDR_TRAP_CFG_1 0x0010020448 |
|---|
| 668 | #define A_ADDR_TRAP_CFG_2 0x0010020450 |
|---|
| 669 | #define A_ADDR_TRAP_CFG_3 0x0010020458 |
|---|
| 670 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
|---|
| 671 | #define A_ADDR_TRAP_REG_DEBUG 0x0010020460 |
|---|
| 672 | #endif /* 1250 PASS2 || 112x PASS1 */ |
|---|
| 673 | |
|---|
| 674 | |
|---|
| 675 | /* ********************************************************************* |
|---|
| 676 | * System Interrupt Mapper Registers |
|---|
| 677 | ********************************************************************* */ |
|---|
| 678 | |
|---|
| 679 | #define A_IMR_CPU0_BASE 0x0010020000 |
|---|
| 680 | #define A_IMR_CPU1_BASE 0x0010022000 |
|---|
| 681 | #define IMR_REGISTER_SPACING 0x2000 |
|---|
| 682 | #define IMR_REGISTER_SPACING_SHIFT 13 |
|---|
| 683 | |
|---|
| 684 | #define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING) |
|---|
| 685 | #define A_IMR_REGISTER(cpu,reg) (A_IMR_MAPPER(cpu)+(reg)) |
|---|
| 686 | |
|---|
| 687 | #define R_IMR_INTERRUPT_DIAG 0x0010 |
|---|
| 688 | #define R_IMR_INTERRUPT_MASK 0x0028 |
|---|
| 689 | #define R_IMR_INTERRUPT_TRACE 0x0038 |
|---|
| 690 | #define R_IMR_INTERRUPT_SOURCE_STATUS 0x0040 |
|---|
| 691 | #define R_IMR_LDT_INTERRUPT_SET 0x0048 |
|---|
| 692 | #define R_IMR_LDT_INTERRUPT 0x0018 |
|---|
| 693 | #define R_IMR_LDT_INTERRUPT_CLR 0x0020 |
|---|
| 694 | #define R_IMR_MAILBOX_CPU 0x00c0 |
|---|
| 695 | #define R_IMR_ALIAS_MAILBOX_CPU 0x1000 |
|---|
| 696 | #define R_IMR_MAILBOX_SET_CPU 0x00C8 |
|---|
| 697 | #define R_IMR_ALIAS_MAILBOX_SET_CPU 0x1008 |
|---|
| 698 | #define R_IMR_MAILBOX_CLR_CPU 0x00D0 |
|---|
| 699 | #define R_IMR_INTERRUPT_STATUS_BASE 0x0100 |
|---|
| 700 | #define R_IMR_INTERRUPT_STATUS_COUNT 7 |
|---|
| 701 | #define R_IMR_INTERRUPT_MAP_BASE 0x0200 |
|---|
| 702 | #define R_IMR_INTERRUPT_MAP_COUNT 64 |
|---|
| 703 | |
|---|
| 704 | /* ********************************************************************* |
|---|
| 705 | * System Performance Counter Registers |
|---|
| 706 | ********************************************************************* */ |
|---|
| 707 | |
|---|
| 708 | #define A_SCD_PERF_CNT_CFG 0x00100204C0 |
|---|
| 709 | #define A_SCD_PERF_CNT_0 0x00100204D0 |
|---|
| 710 | #define A_SCD_PERF_CNT_1 0x00100204D8 |
|---|
| 711 | #define A_SCD_PERF_CNT_2 0x00100204E0 |
|---|
| 712 | #define A_SCD_PERF_CNT_3 0x00100204E8 |
|---|
| 713 | |
|---|
| 714 | /* ********************************************************************* |
|---|
| 715 | * System Bus Watcher Registers |
|---|
| 716 | ********************************************************************* */ |
|---|
| 717 | |
|---|
| 718 | #define A_SCD_BUS_ERR_STATUS 0x0010020880 |
|---|
| 719 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
|---|
| 720 | #define A_SCD_BUS_ERR_STATUS_DEBUG 0x00100208D0 |
|---|
| 721 | #endif /* 1250 PASS2 || 112x PASS1 */ |
|---|
| 722 | #define A_BUS_ERR_DATA_0 0x00100208A0 |
|---|
| 723 | #define A_BUS_ERR_DATA_1 0x00100208A8 |
|---|
| 724 | #define A_BUS_ERR_DATA_2 0x00100208B0 |
|---|
| 725 | #define A_BUS_ERR_DATA_3 0x00100208B8 |
|---|
| 726 | #define A_BUS_L2_ERRORS 0x00100208C0 |
|---|
| 727 | #define A_BUS_MEM_IO_ERRORS 0x00100208C8 |
|---|
| 728 | |
|---|
| 729 | /* ********************************************************************* |
|---|
| 730 | * System Debug Controller Registers |
|---|
| 731 | ********************************************************************* */ |
|---|
| 732 | |
|---|
| 733 | #define A_SCD_JTAG_BASE 0x0010000000 |
|---|
| 734 | |
|---|
| 735 | /* ********************************************************************* |
|---|
| 736 | * System Trace Buffer Registers |
|---|
| 737 | ********************************************************************* */ |
|---|
| 738 | |
|---|
| 739 | #define A_SCD_TRACE_CFG 0x0010020A00 |
|---|
| 740 | #define A_SCD_TRACE_READ 0x0010020A08 |
|---|
| 741 | #define A_SCD_TRACE_EVENT_0 0x0010020A20 |
|---|
| 742 | #define A_SCD_TRACE_EVENT_1 0x0010020A28 |
|---|
| 743 | #define A_SCD_TRACE_EVENT_2 0x0010020A30 |
|---|
| 744 | #define A_SCD_TRACE_EVENT_3 0x0010020A38 |
|---|
| 745 | #define A_SCD_TRACE_SEQUENCE_0 0x0010020A40 |
|---|
| 746 | #define A_SCD_TRACE_SEQUENCE_1 0x0010020A48 |
|---|
| 747 | #define A_SCD_TRACE_SEQUENCE_2 0x0010020A50 |
|---|
| 748 | #define A_SCD_TRACE_SEQUENCE_3 0x0010020A58 |
|---|
| 749 | #define A_SCD_TRACE_EVENT_4 0x0010020A60 |
|---|
| 750 | #define A_SCD_TRACE_EVENT_5 0x0010020A68 |
|---|
| 751 | #define A_SCD_TRACE_EVENT_6 0x0010020A70 |
|---|
| 752 | #define A_SCD_TRACE_EVENT_7 0x0010020A78 |
|---|
| 753 | #define A_SCD_TRACE_SEQUENCE_4 0x0010020A80 |
|---|
| 754 | #define A_SCD_TRACE_SEQUENCE_5 0x0010020A88 |
|---|
| 755 | #define A_SCD_TRACE_SEQUENCE_6 0x0010020A90 |
|---|
| 756 | #define A_SCD_TRACE_SEQUENCE_7 0x0010020A98 |
|---|
| 757 | |
|---|
| 758 | /* ********************************************************************* |
|---|
| 759 | * System Generic DMA Registers |
|---|
| 760 | ********************************************************************* */ |
|---|
| 761 | |
|---|
| 762 | #define A_DM_0 0x0010020B00 |
|---|
| 763 | #define A_DM_1 0x0010020B20 |
|---|
| 764 | #define A_DM_2 0x0010020B40 |
|---|
| 765 | #define A_DM_3 0x0010020B60 |
|---|
| 766 | #define DM_REGISTER_SPACING 0x20 |
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| 767 | #define DM_NUM_CHANNELS 4 |
|---|
| 768 | #define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING)) |
|---|
| 769 | #define A_DM_REGISTER(idx,reg) (A_DM_BASE(idx) + (reg)) |
|---|
| 770 | |
|---|
| 771 | #define R_DM_DSCR_BASE 0x0000000000 |
|---|
| 772 | #define R_DM_DSCR_COUNT 0x0000000008 |
|---|
| 773 | #define R_DM_CUR_DSCR_ADDR 0x0000000010 |
|---|
| 774 | #define R_DM_DSCR_BASE_DEBUG 0x0000000018 |
|---|
| 775 | |
|---|
| 776 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) |
|---|
| 777 | #define A_DM_PARTIAL_0 0x0010020ba0 |
|---|
| 778 | #define A_DM_PARTIAL_1 0x0010020ba8 |
|---|
| 779 | #define A_DM_PARTIAL_2 0x0010020bb0 |
|---|
| 780 | #define A_DM_PARTIAL_3 0x0010020bb8 |
|---|
| 781 | #define DM_PARTIAL_REGISTER_SPACING 0x8 |
|---|
| 782 | #define A_DM_PARTIAL(idx) (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING)) |
|---|
| 783 | #endif /* 1250 PASS3 || 112x PASS1 */ |
|---|
| 784 | |
|---|
| 785 | #if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) |
|---|
| 786 | #define A_DM_CRC_0 0x0010020b80 |
|---|
| 787 | #define A_DM_CRC_1 0x0010020b90 |
|---|
| 788 | #define DM_CRC_REGISTER_SPACING 0x10 |
|---|
| 789 | #define DM_CRC_NUM_CHANNELS 2 |
|---|
| 790 | #define A_DM_CRC_BASE(idx) (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING)) |
|---|
| 791 | #define A_DM_CRC_REGISTER(idx,reg) (A_DM_CRC_BASE(idx) + (reg)) |
|---|
| 792 | |
|---|
| 793 | #define R_CRC_DEF_0 0x00 |
|---|
| 794 | #define R_CTCP_DEF_0 0x08 |
|---|
| 795 | #endif /* 1250 PASS3 || 112x PASS1 */ |
|---|
| 796 | |
|---|
| 797 | /* ********************************************************************* |
|---|
| 798 | * Physical Address Map |
|---|
| 799 | ********************************************************************* */ |
|---|
| 800 | |
|---|
| 801 | #define A_PHYS_MEMORY_0 _SB_MAKE64(0x0000000000) |
|---|
| 802 | #define A_PHYS_MEMORY_SIZE _SB_MAKE64((256*1024*1024)) |
|---|
| 803 | #define A_PHYS_SYSTEM_CTL _SB_MAKE64(0x0010000000) |
|---|
| 804 | #define A_PHYS_IO_SYSTEM _SB_MAKE64(0x0010060000) |
|---|
| 805 | #define A_PHYS_GENBUS _SB_MAKE64(0x0010090000) |
|---|
| 806 | #define A_PHYS_GENBUS_END _SB_MAKE64(0x0040000000) |
|---|
| 807 | #define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000) |
|---|
| 808 | #define A_PHYS_LDTPCI_IO_MATCH_BITS_32 _SB_MAKE64(0x0060000000) |
|---|
| 809 | #define A_PHYS_MEMORY_1 _SB_MAKE64(0x0080000000) |
|---|
| 810 | #define A_PHYS_MEMORY_2 _SB_MAKE64(0x0090000000) |
|---|
| 811 | #define A_PHYS_MEMORY_3 _SB_MAKE64(0x00C0000000) |
|---|
| 812 | #define A_PHYS_L2_CACHE_TEST _SB_MAKE64(0x00D0000000) |
|---|
| 813 | #define A_PHYS_LDT_SPECIAL_MATCH_BYTES _SB_MAKE64(0x00D8000000) |
|---|
| 814 | #define A_PHYS_LDTPCI_IO_MATCH_BYTES _SB_MAKE64(0x00DC000000) |
|---|
| 815 | #define A_PHYS_LDTPCI_CFG_MATCH_BYTES _SB_MAKE64(0x00DE000000) |
|---|
| 816 | #define A_PHYS_LDT_SPECIAL_MATCH_BITS _SB_MAKE64(0x00F8000000) |
|---|
| 817 | #define A_PHYS_LDTPCI_IO_MATCH_BITS _SB_MAKE64(0x00FC000000) |
|---|
| 818 | #define A_PHYS_LDTPCI_CFG_MATCH_BITS _SB_MAKE64(0x00FE000000) |
|---|
| 819 | #define A_PHYS_MEMORY_EXP _SB_MAKE64(0x0100000000) |
|---|
| 820 | #define A_PHYS_MEMORY_EXP_SIZE _SB_MAKE64((508*1024*1024*1024)) |
|---|
| 821 | #define A_PHYS_LDT_EXP _SB_MAKE64(0x8000000000) |
|---|
| 822 | #define A_PHYS_PCI_FULLACCESS_BYTES _SB_MAKE64(0xF000000000) |
|---|
| 823 | #define A_PHYS_PCI_FULLACCESS_BITS _SB_MAKE64(0xF100000000) |
|---|
| 824 | #define A_PHYS_RESERVED _SB_MAKE64(0xF200000000) |
|---|
| 825 | #define A_PHYS_RESERVED_SPECIAL_LDT _SB_MAKE64(0xFD00000000) |
|---|
| 826 | |
|---|
| 827 | #define A_PHYS_L2CACHE_WAY_SIZE _SB_MAKE64(0x0000020000) |
|---|
| 828 | #define PHYS_L2CACHE_NUM_WAYS 4 |
|---|
| 829 | #define A_PHYS_L2CACHE_TOTAL_SIZE _SB_MAKE64(0x0000080000) |
|---|
| 830 | #define A_PHYS_L2CACHE_WAY0 _SB_MAKE64(0x00D0180000) |
|---|
| 831 | #define A_PHYS_L2CACHE_WAY1 _SB_MAKE64(0x00D01A0000) |
|---|
| 832 | #define A_PHYS_L2CACHE_WAY2 _SB_MAKE64(0x00D01C0000) |
|---|
| 833 | #define A_PHYS_L2CACHE_WAY3 _SB_MAKE64(0x00D01E0000) |
|---|
| 834 | |
|---|
| 835 | |
|---|
| 836 | #endif |
|---|
