| 1 | /* ********************************************************************* |
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| 2 | * SB1250 Board Support Package |
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| 3 | * |
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| 4 | * UART Constants File: sb1250_uart.h |
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| 5 | * |
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| 6 | * This module contains constants and macros useful for |
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| 7 | * manipulating the SB1250's UARTs |
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| 8 | * |
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| 9 | * SB1250 specification level: User's manual 1/02/02 |
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| 10 | * |
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| 11 | * Author: Mitch Lichtenberg |
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| 12 | * |
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| 13 | ********************************************************************* |
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| 14 | * |
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| 15 | * Copyright 2000,2001,2002,2003 |
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| 16 | * Broadcom Corporation. All rights reserved. |
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| 17 | * |
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| 18 | * This program is free software; you can redistribute it and/or |
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| 19 | * modify it under the terms of the GNU General Public License as |
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| 20 | * published by the Free Software Foundation; either version 2 of |
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| 21 | * the License, or (at your option) any later version. |
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| 22 | * |
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| 23 | * This program is distributed in the hope that it will be useful, |
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| 24 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 25 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 26 | * GNU General Public License for more details. |
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| 27 | * |
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| 28 | * You should have received a copy of the GNU General Public License |
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| 29 | * along with this program; if not, write to the Free Software |
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| 30 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
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| 31 | * MA 02111-1307 USA |
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| 32 | ********************************************************************* */ |
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| 33 | |
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| 34 | |
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| 35 | #ifndef _SB1250_UART_H |
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| 36 | #define _SB1250_UART_H |
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| 37 | |
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| 38 | #include "sb1250_defs.h" |
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| 39 | |
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| 40 | /* ********************************************************************** |
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| 41 | * DUART Registers |
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| 42 | ********************************************************************** */ |
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| 43 | |
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| 44 | /* |
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| 45 | * DUART Mode Register #1 (Table 10-3) |
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| 46 | * Register: DUART_MODE_REG_1_A |
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| 47 | * Register: DUART_MODE_REG_1_B |
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| 48 | */ |
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| 49 | |
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| 50 | #define S_DUART_BITS_PER_CHAR 0 |
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| 51 | #define M_DUART_BITS_PER_CHAR _SB_MAKEMASK(2,S_DUART_BITS_PER_CHAR) |
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| 52 | #define V_DUART_BITS_PER_CHAR(x) _SB_MAKEVALUE(x,S_DUART_BITS_PER_CHAR) |
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| 53 | |
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| 54 | #define K_DUART_BITS_PER_CHAR_RSV0 0 |
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| 55 | #define K_DUART_BITS_PER_CHAR_RSV1 1 |
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| 56 | #define K_DUART_BITS_PER_CHAR_7 2 |
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| 57 | #define K_DUART_BITS_PER_CHAR_8 3 |
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| 58 | |
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| 59 | #define V_DUART_BITS_PER_CHAR_RSV0 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0) |
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| 60 | #define V_DUART_BITS_PER_CHAR_RSV1 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1) |
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| 61 | #define V_DUART_BITS_PER_CHAR_7 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7) |
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| 62 | #define V_DUART_BITS_PER_CHAR_8 V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8) |
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| 63 | |
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| 64 | |
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| 65 | #define M_DUART_PARITY_TYPE_EVEN 0x00 |
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| 66 | #define M_DUART_PARITY_TYPE_ODD _SB_MAKEMASK1(2) |
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| 67 | |
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| 68 | #define S_DUART_PARITY_MODE 3 |
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| 69 | #define M_DUART_PARITY_MODE _SB_MAKEMASK(2,S_DUART_PARITY_MODE) |
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| 70 | #define V_DUART_PARITY_MODE(x) _SB_MAKEVALUE(x,S_DUART_PARITY_MODE) |
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| 71 | |
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| 72 | #define K_DUART_PARITY_MODE_ADD 0 |
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| 73 | #define K_DUART_PARITY_MODE_ADD_FIXED 1 |
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| 74 | #define K_DUART_PARITY_MODE_NONE 2 |
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| 75 | |
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| 76 | #define V_DUART_PARITY_MODE_ADD V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD) |
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| 77 | #define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED) |
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| 78 | #define V_DUART_PARITY_MODE_NONE V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE) |
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| 79 | |
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| 80 | #define M_DUART_ERR_MODE _SB_MAKEMASK1(5) /* must be zero */ |
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| 81 | |
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| 82 | #define M_DUART_RX_IRQ_SEL_RXRDY 0 |
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| 83 | #define M_DUART_RX_IRQ_SEL_RXFULL _SB_MAKEMASK1(6) |
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| 84 | |
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| 85 | #define M_DUART_RX_RTS_ENA _SB_MAKEMASK1(7) |
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| 86 | |
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| 87 | /* |
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| 88 | * DUART Mode Register #2 (Table 10-4) |
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| 89 | * Register: DUART_MODE_REG_2_A |
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| 90 | * Register: DUART_MODE_REG_2_B |
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| 91 | */ |
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| 92 | |
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| 93 | #define M_DUART_MODE_RESERVED1 _SB_MAKEMASK(3,0) /* ignored */ |
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| 94 | |
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| 95 | #define M_DUART_STOP_BIT_LEN_2 _SB_MAKEMASK1(3) |
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| 96 | #define M_DUART_STOP_BIT_LEN_1 0 |
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| 97 | |
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| 98 | #define M_DUART_TX_CTS_ENA _SB_MAKEMASK1(4) |
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| 99 | |
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| 100 | |
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| 101 | #define M_DUART_MODE_RESERVED2 _SB_MAKEMASK1(5) /* must be zero */ |
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| 102 | |
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| 103 | #define S_DUART_CHAN_MODE 6 |
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| 104 | #define M_DUART_CHAN_MODE _SB_MAKEMASK(2,S_DUART_CHAN_MODE) |
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| 105 | #define V_DUART_CHAN_MODE(x) _SB_MAKEVALUE(x,S_DUART_CHAN_MODE) |
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| 106 | |
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| 107 | #define K_DUART_CHAN_MODE_NORMAL 0 |
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| 108 | #define K_DUART_CHAN_MODE_LCL_LOOP 2 |
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| 109 | #define K_DUART_CHAN_MODE_REM_LOOP 3 |
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| 110 | |
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| 111 | #define V_DUART_CHAN_MODE_NORMAL V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL) |
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| 112 | #define V_DUART_CHAN_MODE_LCL_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP) |
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| 113 | #define V_DUART_CHAN_MODE_REM_LOOP V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP) |
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| 114 | |
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| 115 | /* |
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| 116 | * DUART Command Register (Table 10-5) |
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| 117 | * Register: DUART_CMD_A |
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| 118 | * Register: DUART_CMD_B |
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| 119 | */ |
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| 120 | |
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| 121 | #define M_DUART_RX_EN _SB_MAKEMASK1(0) |
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| 122 | #define M_DUART_RX_DIS _SB_MAKEMASK1(1) |
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| 123 | #define M_DUART_TX_EN _SB_MAKEMASK1(2) |
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| 124 | #define M_DUART_TX_DIS _SB_MAKEMASK1(3) |
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| 125 | |
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| 126 | #define S_DUART_MISC_CMD 4 |
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| 127 | #define M_DUART_MISC_CMD _SB_MAKEMASK(3,S_DUART_MISC_CMD) |
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| 128 | #define V_DUART_MISC_CMD(x) _SB_MAKEVALUE(x,S_DUART_MISC_CMD) |
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| 129 | |
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| 130 | #define K_DUART_MISC_CMD_NOACTION0 0 |
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| 131 | #define K_DUART_MISC_CMD_NOACTION1 1 |
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| 132 | #define K_DUART_MISC_CMD_RESET_RX 2 |
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| 133 | #define K_DUART_MISC_CMD_RESET_TX 3 |
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| 134 | #define K_DUART_MISC_CMD_NOACTION4 4 |
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| 135 | #define K_DUART_MISC_CMD_RESET_BREAK_INT 5 |
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| 136 | #define K_DUART_MISC_CMD_START_BREAK 6 |
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| 137 | #define K_DUART_MISC_CMD_STOP_BREAK 7 |
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| 138 | |
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| 139 | #define V_DUART_MISC_CMD_NOACTION0 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0) |
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| 140 | #define V_DUART_MISC_CMD_NOACTION1 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1) |
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| 141 | #define V_DUART_MISC_CMD_RESET_RX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX) |
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| 142 | #define V_DUART_MISC_CMD_RESET_TX V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX) |
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| 143 | #define V_DUART_MISC_CMD_NOACTION4 V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4) |
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| 144 | #define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT) |
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| 145 | #define V_DUART_MISC_CMD_START_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK) |
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| 146 | #define V_DUART_MISC_CMD_STOP_BREAK V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK) |
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| 147 | |
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| 148 | #define M_DUART_CMD_RESERVED _SB_MAKEMASK1(7) |
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| 149 | |
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| 150 | /* |
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| 151 | * DUART Status Register (Table 10-6) |
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| 152 | * Register: DUART_STATUS_A |
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| 153 | * Register: DUART_STATUS_B |
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| 154 | * READ-ONLY |
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| 155 | */ |
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| 156 | |
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| 157 | #define M_DUART_RX_RDY _SB_MAKEMASK1(0) |
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| 158 | #define M_DUART_RX_FFUL _SB_MAKEMASK1(1) |
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| 159 | #define M_DUART_TX_RDY _SB_MAKEMASK1(2) |
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| 160 | #define M_DUART_TX_EMT _SB_MAKEMASK1(3) |
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| 161 | #define M_DUART_OVRUN_ERR _SB_MAKEMASK1(4) |
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| 162 | #define M_DUART_PARITY_ERR _SB_MAKEMASK1(5) |
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| 163 | #define M_DUART_FRM_ERR _SB_MAKEMASK1(6) |
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| 164 | #define M_DUART_RCVD_BRK _SB_MAKEMASK1(7) |
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| 165 | |
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| 166 | /* |
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| 167 | * DUART Baud Rate Register (Table 10-7) |
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| 168 | * Register: DUART_CLK_SEL_A |
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| 169 | * Register: DUART_CLK_SEL_B |
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| 170 | */ |
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| 171 | |
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| 172 | #define M_DUART_CLK_COUNTER _SB_MAKEMASK(12,0) |
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| 173 | #define V_DUART_BAUD_RATE(x) (100000000/((x)*20)-1) |
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| 174 | |
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| 175 | /* |
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| 176 | * DUART Data Registers (Table 10-8 and 10-9) |
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| 177 | * Register: DUART_RX_HOLD_A |
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| 178 | * Register: DUART_RX_HOLD_B |
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| 179 | * Register: DUART_TX_HOLD_A |
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| 180 | * Register: DUART_TX_HOLD_B |
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| 181 | */ |
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| 182 | |
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| 183 | #define M_DUART_RX_DATA _SB_MAKEMASK(8,0) |
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| 184 | #define M_DUART_TX_DATA _SB_MAKEMASK(8,0) |
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| 185 | |
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| 186 | /* |
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| 187 | * DUART Input Port Register (Table 10-10) |
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| 188 | * Register: DUART_IN_PORT |
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| 189 | */ |
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| 190 | |
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| 191 | #define M_DUART_IN_PIN0_VAL _SB_MAKEMASK1(0) |
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| 192 | #define M_DUART_IN_PIN1_VAL _SB_MAKEMASK1(1) |
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| 193 | #define M_DUART_IN_PIN2_VAL _SB_MAKEMASK1(2) |
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| 194 | #define M_DUART_IN_PIN3_VAL _SB_MAKEMASK1(3) |
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| 195 | #define M_DUART_IN_PIN4_VAL _SB_MAKEMASK1(4) |
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| 196 | #define M_DUART_IN_PIN5_VAL _SB_MAKEMASK1(5) |
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| 197 | #define M_DUART_RIN0_PIN _SB_MAKEMASK1(6) |
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| 198 | #define M_DUART_RIN1_PIN _SB_MAKEMASK1(7) |
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| 199 | |
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| 200 | /* |
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| 201 | * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13) |
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| 202 | * Register: DUART_INPORT_CHNG |
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| 203 | */ |
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| 204 | |
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| 205 | #define S_DUART_IN_PIN_VAL 0 |
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| 206 | #define M_DUART_IN_PIN_VAL _SB_MAKEMASK(4,S_DUART_IN_PIN_VAL) |
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| 207 | |
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| 208 | #define S_DUART_IN_PIN_CHNG 4 |
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| 209 | #define M_DUART_IN_PIN_CHNG _SB_MAKEMASK(4,S_DUART_IN_PIN_CHNG) |
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| 210 | |
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| 211 | |
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| 212 | /* |
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| 213 | * DUART Output port control register (Table 10-14) |
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| 214 | * Register: DUART_OPCR |
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| 215 | */ |
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| 216 | |
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| 217 | #define M_DUART_OPCR_RESERVED0 _SB_MAKEMASK1(0) /* must be zero */ |
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| 218 | #define M_DUART_OPC2_SEL _SB_MAKEMASK1(1) |
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| 219 | #define M_DUART_OPCR_RESERVED1 _SB_MAKEMASK1(2) /* must be zero */ |
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| 220 | #define M_DUART_OPC3_SEL _SB_MAKEMASK1(3) |
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| 221 | #define M_DUART_OPCR_RESERVED2 _SB_MAKEMASK(4,4) /* must be zero */ |
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| 222 | |
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| 223 | /* |
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| 224 | * DUART Aux Control Register (Table 10-15) |
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| 225 | * Register: DUART_AUX_CTRL |
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| 226 | */ |
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| 227 | |
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| 228 | #define M_DUART_IP0_CHNG_ENA _SB_MAKEMASK1(0) |
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| 229 | #define M_DUART_IP1_CHNG_ENA _SB_MAKEMASK1(1) |
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| 230 | #define M_DUART_IP2_CHNG_ENA _SB_MAKEMASK1(2) |
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| 231 | #define M_DUART_IP3_CHNG_ENA _SB_MAKEMASK1(3) |
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| 232 | #define M_DUART_ACR_RESERVED _SB_MAKEMASK(4,4) |
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| 233 | |
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| 234 | #define M_DUART_CTS_CHNG_ENA _SB_MAKEMASK1(0) |
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| 235 | #define M_DUART_CIN_CHNG_ENA _SB_MAKEMASK1(2) |
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| 236 | |
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| 237 | /* |
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| 238 | * DUART Interrupt Status Register (Table 10-16) |
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| 239 | * Register: DUART_ISR |
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| 240 | */ |
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| 241 | |
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| 242 | #define M_DUART_ISR_TX_A _SB_MAKEMASK1(0) |
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| 243 | #define M_DUART_ISR_RX_A _SB_MAKEMASK1(1) |
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| 244 | #define M_DUART_ISR_BRK_A _SB_MAKEMASK1(2) |
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| 245 | #define M_DUART_ISR_IN_A _SB_MAKEMASK1(3) |
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| 246 | #define M_DUART_ISR_TX_B _SB_MAKEMASK1(4) |
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| 247 | #define M_DUART_ISR_RX_B _SB_MAKEMASK1(5) |
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| 248 | #define M_DUART_ISR_BRK_B _SB_MAKEMASK1(6) |
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| 249 | #define M_DUART_ISR_IN_B _SB_MAKEMASK1(7) |
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| 250 | |
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| 251 | /* |
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| 252 | * DUART Channel A Interrupt Status Register (Table 10-17) |
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| 253 | * DUART Channel B Interrupt Status Register (Table 10-18) |
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| 254 | * Register: DUART_ISR_A |
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| 255 | * Register: DUART_ISR_B |
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| 256 | */ |
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| 257 | |
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| 258 | #define M_DUART_ISR_TX _SB_MAKEMASK1(0) |
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| 259 | #define M_DUART_ISR_RX _SB_MAKEMASK1(1) |
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| 260 | #define M_DUART_ISR_BRK _SB_MAKEMASK1(2) |
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| 261 | #define M_DUART_ISR_IN _SB_MAKEMASK1(3) |
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| 262 | #define M_DUART_ISR_RESERVED _SB_MAKEMASK(4,4) |
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| 263 | |
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| 264 | /* |
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| 265 | * DUART Interrupt Mask Register (Table 10-19) |
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| 266 | * Register: DUART_IMR |
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| 267 | */ |
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| 268 | |
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| 269 | #define M_DUART_IMR_TX_A _SB_MAKEMASK1(0) |
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| 270 | #define M_DUART_IMR_RX_A _SB_MAKEMASK1(1) |
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| 271 | #define M_DUART_IMR_BRK_A _SB_MAKEMASK1(2) |
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| 272 | #define M_DUART_IMR_IN_A _SB_MAKEMASK1(3) |
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| 273 | #define M_DUART_IMR_ALL_A _SB_MAKEMASK(4,0) |
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| 274 | |
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| 275 | #define M_DUART_IMR_TX_B _SB_MAKEMASK1(4) |
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| 276 | #define M_DUART_IMR_RX_B _SB_MAKEMASK1(5) |
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| 277 | #define M_DUART_IMR_BRK_B _SB_MAKEMASK1(6) |
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| 278 | #define M_DUART_IMR_IN_B _SB_MAKEMASK1(7) |
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| 279 | #define M_DUART_IMR_ALL_B _SB_MAKEMASK(4,4) |
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| 280 | |
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| 281 | /* |
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| 282 | * DUART Channel A Interrupt Mask Register (Table 10-20) |
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| 283 | * DUART Channel B Interrupt Mask Register (Table 10-21) |
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| 284 | * Register: DUART_IMR_A |
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| 285 | * Register: DUART_IMR_B |
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| 286 | */ |
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| 287 | |
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| 288 | #define M_DUART_IMR_TX _SB_MAKEMASK1(0) |
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| 289 | #define M_DUART_IMR_RX _SB_MAKEMASK1(1) |
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| 290 | #define M_DUART_IMR_BRK _SB_MAKEMASK1(2) |
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| 291 | #define M_DUART_IMR_IN _SB_MAKEMASK1(3) |
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| 292 | #define M_DUART_IMR_ALL _SB_MAKEMASK(4,0) |
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| 293 | #define M_DUART_IMR_RESERVED _SB_MAKEMASK(4,4) |
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| 294 | |
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| 295 | |
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| 296 | /* |
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| 297 | * DUART Output Port Set Register (Table 10-22) |
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| 298 | * Register: DUART_SET_OPR |
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| 299 | */ |
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| 300 | |
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| 301 | #define M_DUART_SET_OPR0 _SB_MAKEMASK1(0) |
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| 302 | #define M_DUART_SET_OPR1 _SB_MAKEMASK1(1) |
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| 303 | #define M_DUART_SET_OPR2 _SB_MAKEMASK1(2) |
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| 304 | #define M_DUART_SET_OPR3 _SB_MAKEMASK1(3) |
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| 305 | #define M_DUART_OPSR_RESERVED _SB_MAKEMASK(4,4) |
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| 306 | |
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| 307 | /* |
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| 308 | * DUART Output Port Clear Register (Table 10-23) |
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| 309 | * Register: DUART_CLEAR_OPR |
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| 310 | */ |
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| 311 | |
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| 312 | #define M_DUART_CLR_OPR0 _SB_MAKEMASK1(0) |
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| 313 | #define M_DUART_CLR_OPR1 _SB_MAKEMASK1(1) |
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| 314 | #define M_DUART_CLR_OPR2 _SB_MAKEMASK1(2) |
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| 315 | #define M_DUART_CLR_OPR3 _SB_MAKEMASK1(3) |
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| 316 | #define M_DUART_OPCR_RESERVED _SB_MAKEMASK(4,4) |
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| 317 | |
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| 318 | /* |
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| 319 | * DUART Output Port RTS Register (Table 10-24) |
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| 320 | * Register: DUART_OUT_PORT |
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| 321 | */ |
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| 322 | |
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| 323 | #define M_DUART_OUT_PIN_SET0 _SB_MAKEMASK1(0) |
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| 324 | #define M_DUART_OUT_PIN_SET1 _SB_MAKEMASK1(1) |
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| 325 | #define M_DUART_OUT_PIN_CLR0 _SB_MAKEMASK1(2) |
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| 326 | #define M_DUART_OUT_PIN_CLR1 _SB_MAKEMASK1(3) |
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| 327 | #define M_DUART_OPRR_RESERVED _SB_MAKEMASK(4,4) |
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| 328 | |
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| 329 | #define M_DUART_OUT_PIN_SET(chan) \ |
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| 330 | (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1) |
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| 331 | #define M_DUART_OUT_PIN_CLR(chan) \ |
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| 332 | (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1) |
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| 333 | |
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| 334 | #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) |
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| 335 | /* |
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| 336 | * Full Interrupt Control Register |
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| 337 | */ |
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| 338 | |
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| 339 | #define S_DUART_SIG_FULL _SB_MAKE64(0) |
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| 340 | #define M_DUART_SIG_FULL _SB_MAKEMASK(4,S_DUART_SIG_FULL) |
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| 341 | #define V_DUART_SIG_FULL(x) _SB_MAKEVALUE(x,S_DUART_SIG_FULL) |
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| 342 | #define G_DUART_SIG_FULL(x) _SB_GETVALUE(x,S_DUART_SIG_FULL,M_DUART_SIG_FULL) |
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| 343 | |
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| 344 | #define S_DUART_INT_TIME _SB_MAKE64(4) |
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| 345 | #define M_DUART_INT_TIME _SB_MAKEMASK(4,S_DUART_INT_TIME) |
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| 346 | #define V_DUART_INT_TIME(x) _SB_MAKEVALUE(x,S_DUART_INT_TIME) |
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| 347 | #define G_DUART_INT_TIME(x) _SB_GETVALUE(x,S_DUART_INT_TIME,M_DUART_INT_TIME) |
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| 348 | #endif /* 1250 PASS2 || 112x PASS1 */ |
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| 349 | |
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| 350 | |
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| 351 | /* ********************************************************************** */ |
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| 352 | |
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| 353 | |
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| 354 | #endif |
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