| 1 | /* |
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| 2 | * This file is subject to the terms and conditions of the GNU General Public |
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| 3 | * License. See the file "COPYING" in the main directory of this archive |
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| 4 | * for more details. |
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| 5 | * |
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| 6 | * Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126. |
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| 7 | * |
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| 8 | * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. |
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| 9 | * Copyright (C) 1999 by Ralf Baechle |
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| 10 | */ |
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| 11 | #ifndef _ASM_SN_SN0_ADDRS_H |
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| 12 | #define _ASM_SN_SN0_ADDRS_H |
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| 13 | |
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| 14 | |
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| 15 | /* |
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| 16 | * SN0 (on a T5) Address map |
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| 17 | * |
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| 18 | * This file contains a set of definitions and macros which are used |
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| 19 | * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC, |
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| 20 | * and UNCAC) used by the SN0 architecture. It also contains addresses |
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| 21 | * for "major" statically locatable PROM/Kernel data structures, such as |
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| 22 | * the partition table, the configuration data structure, etc. |
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| 23 | * We make an implicit assumption that the processor using this file |
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| 24 | * follows the R10K's provisions for specifying uncached attributes; |
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| 25 | * should this change, the base registers may very well become processor- |
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| 26 | * dependent. |
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| 27 | * |
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| 28 | * For more information on the address spaces, see the "Local Resources" |
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| 29 | * chapter of the Hub specification. |
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| 30 | * |
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| 31 | * NOTE: This header file is included both by C and by assembler source |
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| 32 | * files. Please bracket any language-dependent definitions |
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| 33 | * appropriately. |
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| 34 | */ |
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| 35 | |
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| 36 | /* |
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| 37 | * Some of the macros here need to be casted to appropriate types when used |
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| 38 | * from C. They definitely must not be casted from assembly language so we |
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| 39 | * use some new ANSI preprocessor stuff to paste these on where needed. |
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| 40 | */ |
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| 41 | |
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| 42 | /* |
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| 43 | * The following couple of definitions will eventually need to be variables, |
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| 44 | * since the amount of address space assigned to each node depends on |
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| 45 | * whether the system is running in N-mode (more nodes with less memory) |
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| 46 | * or M-mode (fewer nodes with more memory). We expect that it will |
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| 47 | * be a while before we need to make this decision dynamically, though, |
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| 48 | * so for now we just use defines bracketed by an ifdef. |
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| 49 | */ |
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| 50 | |
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| 51 | #ifdef CONFIG_SGI_SN0_N_MODE |
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| 52 | |
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| 53 | #define NODE_SIZE_BITS 31 |
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| 54 | #define BWIN_SIZE_BITS 28 |
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| 55 | |
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| 56 | #define NASID_BITS 9 |
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| 57 | #define NASID_BITMASK (0x1ffLL) |
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| 58 | #define NASID_SHFT 31 |
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| 59 | #define NASID_META_BITS 5 |
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| 60 | #define NASID_LOCAL_BITS 4 |
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| 61 | |
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| 62 | #define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10) |
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| 63 | #define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3) |
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| 64 | |
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| 65 | #else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */ |
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| 66 | |
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| 67 | #define NODE_SIZE_BITS 32 |
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| 68 | #define BWIN_SIZE_BITS 29 |
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| 69 | |
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| 70 | #define NASID_BITMASK (0xffLL) |
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| 71 | #define NASID_BITS 8 |
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| 72 | #define NASID_SHFT 32 |
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| 73 | #define NASID_META_BITS 4 |
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| 74 | #define NASID_LOCAL_BITS 4 |
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| 75 | |
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| 76 | #define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10) |
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| 77 | #define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3) |
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| 78 | |
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| 79 | #endif /* !defined(CONFIG_SGI_SN0_N_MODE) */ |
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| 80 | |
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| 81 | #define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS) |
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| 82 | |
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| 83 | #define NASID_MASK (UINT64_CAST NASID_BITMASK << NASID_SHFT) |
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| 84 | #define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \ |
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| 85 | NASID_SHFT) & NASID_BITMASK) |
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| 86 | |
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| 87 | #if !defined(__ASSEMBLY__) && !defined(_STANDALONE) |
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| 88 | |
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| 89 | #define NODE_SWIN_BASE(nasid, widget) \ |
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| 90 | ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \ |
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| 91 | : RAW_NODE_SWIN_BASE(nasid, widget)) |
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| 92 | #else /* __ASSEMBLY__ || _STANDALONE */ |
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| 93 | #define NODE_SWIN_BASE(nasid, widget) \ |
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| 94 | (NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS)) |
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| 95 | #endif /* __ASSEMBLY__ || _STANDALONE */ |
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| 96 | |
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| 97 | /* |
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| 98 | * The following definitions pertain to the IO special address |
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| 99 | * space. They define the location of the big and little windows |
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| 100 | * of any given node. |
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| 101 | */ |
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| 102 | |
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| 103 | #define BWIN_INDEX_BITS 3 |
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| 104 | #define BWIN_SIZE (UINT64_CAST 1 << BWIN_SIZE_BITS) |
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| 105 | #define BWIN_SIZEMASK (BWIN_SIZE - 1) |
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| 106 | #define BWIN_WIDGET_MASK 0x7 |
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| 107 | #define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE) |
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| 108 | #define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \ |
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| 109 | (UINT64_CAST (bigwin) << BWIN_SIZE_BITS)) |
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| 110 | |
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| 111 | #define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK) |
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| 112 | #define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK) |
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| 113 | /* |
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| 114 | * Verify if addr belongs to large window address of node with "nasid" |
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| 115 | * |
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| 116 | * |
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| 117 | * NOTE: "addr" is expected to be XKPHYS address, and NOT physical |
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| 118 | * address |
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| 119 | * |
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| 120 | * |
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| 121 | */ |
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| 122 | |
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| 123 | #define NODE_BWIN_ADDR(nasid, addr) \ |
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| 124 | (((addr) >= NODE_BWIN_BASE0(nasid)) && \ |
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| 125 | ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \ |
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| 126 | BWIN_SIZE))) |
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| 127 | |
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| 128 | /* |
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| 129 | * The following define the major position-independent aliases used |
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| 130 | * in SN0. |
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| 131 | * CALIAS -- Varies in size, points to the first n bytes of memory |
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| 132 | * on the reader's node. |
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| 133 | */ |
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| 134 | |
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| 135 | #define CALIAS_BASE CAC_BASE |
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| 136 | |
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| 137 | |
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| 138 | |
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| 139 | #define BRIDGE_REG_PTR(_base, _off) ((volatile bridgereg_t *) \ |
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| 140 | ((__psunsigned_t)(_base) + (__psunsigned_t)(_off))) |
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| 141 | |
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| 142 | #define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid))) |
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| 143 | |
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| 144 | /* Turn on sable logging for the processors whose bits are set. */ |
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| 145 | #ifdef SABLE |
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| 146 | #define SABLE_LOG_TRIGGER(_map) \ |
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| 147 | *((volatile hubreg_t *)(IO_BASE + 0x17ffff0)) = (_map) |
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| 148 | #else |
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| 149 | #define SABLE_LOG_TRIGGER(_map) |
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| 150 | #endif /* SABLE */ |
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| 151 | |
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| 152 | #ifndef __ASSEMBLY__ |
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| 153 | #define KERN_NMI_ADDR(nasid, slice) \ |
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| 154 | TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET + \ |
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| 155 | (IP27_NMI_KREGS_CPU_SIZE * (slice))) |
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| 156 | #endif /* !__ASSEMBLY__ */ |
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| 157 | |
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| 158 | #ifdef PROM |
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| 159 | |
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| 160 | #define MISC_PROM_BASE PHYS_TO_K0(0x01300000) |
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| 161 | #define MISC_PROM_SIZE 0x200000 |
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| 162 | |
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| 163 | #define DIAG_BASE PHYS_TO_K0(0x01500000) |
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| 164 | #define DIAG_SIZE 0x300000 |
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| 165 | |
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| 166 | #define ROUTE_BASE PHYS_TO_K0(0x01800000) |
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| 167 | #define ROUTE_SIZE 0x200000 |
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| 168 | |
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| 169 | #define IP27PROM_FLASH_HDR PHYS_TO_K0(0x01300000) |
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| 170 | #define IP27PROM_FLASH_DATA PHYS_TO_K0(0x01301000) |
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| 171 | #define IP27PROM_CORP_MAX 32 |
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| 172 | #define IP27PROM_CORP PHYS_TO_K0(0x01800000) |
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| 173 | #define IP27PROM_CORP_SIZE 0x10000 |
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| 174 | #define IP27PROM_CORP_STK PHYS_TO_K0(0x01810000) |
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| 175 | #define IP27PROM_CORP_STKSIZE 0x2000 |
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| 176 | #define IP27PROM_DECOMP_BUF PHYS_TO_K0(0x01900000) |
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| 177 | #define IP27PROM_DECOMP_SIZE 0xfff00 |
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| 178 | |
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| 179 | #define IP27PROM_BASE PHYS_TO_K0(0x01a00000) |
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| 180 | #define IP27PROM_BASE_MAPPED (UNCAC_BASE | 0x1fc00000) |
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| 181 | #define IP27PROM_SIZE_MAX 0x100000 |
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| 182 | |
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| 183 | #define IP27PROM_PCFG PHYS_TO_K0(0x01b00000) |
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| 184 | #define IP27PROM_PCFG_SIZE 0xd0000 |
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| 185 | #define IP27PROM_ERRDMP PHYS_TO_K1(0x01bd0000) |
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| 186 | #define IP27PROM_ERRDMP_SIZE 0xf000 |
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| 187 | |
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| 188 | #define IP27PROM_INIT_START PHYS_TO_K1(0x01bd0000) |
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| 189 | #define IP27PROM_CONSOLE PHYS_TO_K1(0x01bdf000) |
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| 190 | #define IP27PROM_CONSOLE_SIZE 0x200 |
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| 191 | #define IP27PROM_NETUART PHYS_TO_K1(0x01bdf200) |
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| 192 | #define IP27PROM_NETUART_SIZE 0x100 |
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| 193 | #define IP27PROM_UNUSED1 PHYS_TO_K1(0x01bdf300) |
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| 194 | #define IP27PROM_UNUSED1_SIZE 0x500 |
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| 195 | #define IP27PROM_ELSC_BASE_A PHYS_TO_K0(0x01bdf800) |
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| 196 | #define IP27PROM_ELSC_BASE_B PHYS_TO_K0(0x01bdfc00) |
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| 197 | #define IP27PROM_STACK_A PHYS_TO_K0(0x01be0000) |
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| 198 | #define IP27PROM_STACK_B PHYS_TO_K0(0x01bf0000) |
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| 199 | #define IP27PROM_STACK_SHFT 16 |
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| 200 | #define IP27PROM_STACK_SIZE (1 << IP27PROM_STACK_SHFT) |
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| 201 | #define IP27PROM_INIT_END PHYS_TO_K0(0x01c00000) |
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| 202 | |
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| 203 | #define SLAVESTACK_BASE PHYS_TO_K0(0x01580000) |
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| 204 | #define SLAVESTACK_SIZE 0x40000 |
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| 205 | |
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| 206 | #define ENETBUFS_BASE PHYS_TO_K0(0x01f80000) |
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| 207 | #define ENETBUFS_SIZE 0x20000 |
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| 208 | |
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| 209 | #define IO6PROM_BASE PHYS_TO_K0(0x01c00000) |
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| 210 | #define IO6PROM_SIZE 0x400000 |
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| 211 | #define IO6PROM_BASE_MAPPED (UNCAC_BASE | 0x11c00000) |
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| 212 | #define IO6DPROM_BASE PHYS_TO_K0(0x01c00000) |
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| 213 | #define IO6DPROM_SIZE 0x200000 |
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| 214 | |
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| 215 | #define NODEBUGUNIX_ADDR PHYS_TO_K0(0x00019000) |
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| 216 | #define DEBUGUNIX_ADDR PHYS_TO_K0(0x00100000) |
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| 217 | |
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| 218 | #define IP27PROM_INT_LAUNCH 10 /* and 11 */ |
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| 219 | #define IP27PROM_INT_NETUART 12 /* through 17 */ |
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| 220 | |
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| 221 | #endif /* PROM */ |
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| 222 | |
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| 223 | /* |
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| 224 | * needed by symmon so it needs to be outside #if PROM |
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| 225 | */ |
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| 226 | #define IP27PROM_ELSC_SHFT 10 |
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| 227 | #define IP27PROM_ELSC_SIZE (1 << IP27PROM_ELSC_SHFT) |
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| 228 | |
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| 229 | /* |
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| 230 | * This address is used by IO6PROM to build MemoryDescriptors of |
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| 231 | * free memory. This address is important since unix gets loaded |
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| 232 | * at this address, and this memory has to be FREE if unix is to |
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| 233 | * be loaded. |
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| 234 | */ |
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| 235 | |
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| 236 | #define FREEMEM_BASE PHYS_TO_K0(0x2000000) |
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| 237 | |
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| 238 | #define IO6PROM_STACK_SHFT 14 /* stack per cpu */ |
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| 239 | #define IO6PROM_STACK_SIZE (1 << IO6PROM_STACK_SHFT) |
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| 240 | |
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| 241 | /* |
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| 242 | * IP27 PROM vectors |
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| 243 | */ |
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| 244 | |
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| 245 | #define IP27PROM_ENTRY PHYS_TO_COMPATK1(0x1fc00000) |
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| 246 | #define IP27PROM_RESTART PHYS_TO_COMPATK1(0x1fc00008) |
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| 247 | #define IP27PROM_SLAVELOOP PHYS_TO_COMPATK1(0x1fc00010) |
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| 248 | #define IP27PROM_PODMODE PHYS_TO_COMPATK1(0x1fc00018) |
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| 249 | #define IP27PROM_IOC3UARTPOD PHYS_TO_COMPATK1(0x1fc00020) |
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| 250 | #define IP27PROM_FLASHLEDS PHYS_TO_COMPATK1(0x1fc00028) |
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| 251 | #define IP27PROM_REPOD PHYS_TO_COMPATK1(0x1fc00030) |
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| 252 | #define IP27PROM_LAUNCHSLAVE PHYS_TO_COMPATK1(0x1fc00038) |
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| 253 | #define IP27PROM_WAITSLAVE PHYS_TO_COMPATK1(0x1fc00040) |
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| 254 | #define IP27PROM_POLLSLAVE PHYS_TO_COMPATK1(0x1fc00048) |
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| 255 | |
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| 256 | #define KL_UART_BASE LOCAL_HUB_ADDR(MD_UREG0_0) /* base of UART regs */ |
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| 257 | #define KL_UART_CMD LOCAL_HUB_ADDR(MD_UREG0_0) /* UART command reg */ |
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| 258 | #define KL_UART_DATA LOCAL_HUB_ADDR(MD_UREG0_1) /* UART data reg */ |
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| 259 | #define KL_I2C_REG MD_UREG0_0 /* I2C reg */ |
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| 260 | |
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| 261 | #ifndef __ASSEMBLY__ |
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| 262 | |
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| 263 | /* Address 0x400 to 0x1000 ualias points to cache error eframe + misc |
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| 264 | * CACHE_ERR_SP_PTR could either contain an address to the stack, or |
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| 265 | * the stack could start at CACHE_ERR_SP_PTR |
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| 266 | */ |
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| 267 | #if defined (HUB_ERR_STS_WAR) |
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| 268 | #define CACHE_ERR_EFRAME 0x480 |
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| 269 | #else /* HUB_ERR_STS_WAR */ |
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| 270 | #define CACHE_ERR_EFRAME 0x400 |
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| 271 | #endif /* HUB_ERR_STS_WAR */ |
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| 272 | |
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| 273 | #define CACHE_ERR_ECCFRAME (CACHE_ERR_EFRAME + EF_SIZE) |
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| 274 | #define CACHE_ERR_SP_PTR (0x1000 - 32) /* why -32? TBD */ |
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| 275 | #define CACHE_ERR_IBASE_PTR (0x1000 - 40) |
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| 276 | #define CACHE_ERR_SP (CACHE_ERR_SP_PTR - 16) |
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| 277 | #define CACHE_ERR_AREA_SIZE (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME) |
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| 278 | |
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| 279 | #endif /* !__ASSEMBLY__ */ |
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| 280 | |
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| 281 | #define _ARCSPROM |
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| 282 | |
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| 283 | #ifdef _STANDALONE |
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| 284 | |
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| 285 | /* |
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| 286 | * The PROM needs to pass the device base address and the |
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| 287 | * device pci cfg space address to the device drivers during |
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| 288 | * install. The COMPONENT->Key field is used for this purpose. |
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| 289 | * Macros needed by SN0 device drivers to convert the |
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| 290 | * COMPONENT->Key field to the respective base address. |
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| 291 | * Key field looks as follows: |
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| 292 | * |
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| 293 | * +----------------------------------------------------+ |
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| 294 | * |devnasid | widget |pciid |hubwidid|hstnasid | adap | |
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| 295 | * | 2 | 1 | 1 | 1 | 2 | 1 | |
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| 296 | * +----------------------------------------------------+ |
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| 297 | * | | | | | | | |
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| 298 | * 64 48 40 32 24 8 0 |
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| 299 | * |
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| 300 | * These are used by standalone drivers till the io infrastructure |
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| 301 | * is in place. |
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| 302 | */ |
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| 303 | |
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| 304 | #ifndef __ASSEMBLY__ |
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| 305 | |
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| 306 | #define uchar unsigned char |
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| 307 | |
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| 308 | #define KEY_DEVNASID_SHFT 48 |
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| 309 | #define KEY_WIDID_SHFT 40 |
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| 310 | #define KEY_PCIID_SHFT 32 |
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| 311 | #define KEY_HUBWID_SHFT 24 |
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| 312 | #define KEY_HSTNASID_SHFT 8 |
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| 313 | |
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| 314 | #define MK_SN0_KEY(nasid, widid, pciid) \ |
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| 315 | ((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\ |
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| 316 | ((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\ |
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| 317 | ((__psunsigned_t)pciid) << KEY_PCIID_SHFT) |
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| 318 | |
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| 319 | #define ADD_HUBWID_KEY(key,hubwid)\ |
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| 320 | (key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT)) |
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| 321 | |
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| 322 | #define ADD_HSTNASID_KEY(key,hstnasid)\ |
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| 323 | (key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT)) |
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| 324 | |
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| 325 | #define GET_DEVNASID_FROM_KEY(key) ((short)(key >> KEY_DEVNASID_SHFT)) |
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| 326 | #define GET_WIDID_FROM_KEY(key) ((uchar)(key >> KEY_WIDID_SHFT)) |
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| 327 | #define GET_PCIID_FROM_KEY(key) ((uchar)(key >> KEY_PCIID_SHFT)) |
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| 328 | #define GET_HUBWID_FROM_KEY(key) ((uchar)(key >> KEY_HUBWID_SHFT)) |
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| 329 | #define GET_HSTNASID_FROM_KEY(key) ((short)(key >> KEY_HSTNASID_SHFT)) |
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| 330 | |
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| 331 | #define PCI_64_TARGID_SHFT 60 |
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| 332 | |
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| 333 | #define GET_PCIBASE_FROM_KEY(key) (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ |
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| 334 | GET_WIDID_FROM_KEY(key))\ |
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| 335 | | BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key))) |
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| 336 | |
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| 337 | #define GET_PCICFGBASE_FROM_KEY(key) \ |
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| 338 | (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ |
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| 339 | GET_WIDID_FROM_KEY(key))\ |
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| 340 | | BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key))) |
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| 341 | |
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| 342 | #define GET_WIDBASE_FROM_KEY(key) \ |
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| 343 | (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\ |
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| 344 | GET_WIDID_FROM_KEY(key))) |
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| 345 | |
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| 346 | #define PUT_INSTALL_STATUS(c,s) c->Revision = s |
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| 347 | #define GET_INSTALL_STATUS(c) c->Revision |
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| 348 | |
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| 349 | #endif /* !__ASSEMBLY__ */ |
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| 350 | |
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| 351 | #endif /* _STANDALONE */ |
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| 352 | |
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| 353 | #if defined (HUB_ERR_STS_WAR) |
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| 354 | |
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| 355 | #define ERR_STS_WAR_REGISTER IIO_IIBUSERR |
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| 356 | #define ERR_STS_WAR_ADDR LOCAL_HUB_ADDR(IIO_IIBUSERR) |
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| 357 | #define ERR_STS_WAR_PHYSADDR TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR) |
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| 358 | /* Used to match addr in error reg. */ |
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| 359 | #define OLD_ERR_STS_WAR_OFFSET ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100) |
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| 360 | |
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| 361 | #endif /* HUB_ERR_STS_WAR */ |
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| 362 | |
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| 363 | #endif /* _ASM_SN_SN0_ADDRS_H */ |
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