| 1 | /* |
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| 2 | * This file is subject to the terms and conditions of the GNU General Public |
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| 3 | * License. See the file "COPYING" in the main directory of this archive |
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| 4 | * for more details. |
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| 5 | * |
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| 6 | * Derived from IRIX <sys/SN/SN0/hubpi.h>, revision 1.28. |
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| 7 | * |
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| 8 | * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc. |
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| 9 | * Copyright (C) 1999 by Ralf Baechle |
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| 10 | */ |
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| 11 | #ifndef _ASM_SN_SN0_HUBPI_H |
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| 12 | #define _ASM_SN_SN0_HUBPI_H |
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| 13 | |
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| 14 | #include <linux/types.h> |
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| 15 | |
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| 16 | /* |
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| 17 | * Hub I/O interface registers |
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| 18 | * |
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| 19 | * All registers in this file are subject to change until Hub chip tapeout. |
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| 20 | * All register "addresses" are actually offsets. Use the LOCAL_HUB |
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| 21 | * or REMOTE_HUB macros to synthesize an actual address |
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| 22 | */ |
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| 23 | |
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| 24 | #define PI_BASE 0x000000 |
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| 25 | |
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| 26 | /* General protection and control registers */ |
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| 27 | |
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| 28 | #define PI_CPU_PROTECT 0x000000 /* CPU Protection */ |
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| 29 | #define PI_PROT_OVERRD 0x000008 /* Clear CPU Protection bit */ |
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| 30 | #define PI_IO_PROTECT 0x000010 /* Interrupt Pending Protection */ |
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| 31 | #define PI_REGION_PRESENT 0x000018 /* Indicates whether region exists */ |
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| 32 | #define PI_CPU_NUM 0x000020 /* CPU Number ID */ |
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| 33 | #define PI_CALIAS_SIZE 0x000028 /* Cached Alias Size */ |
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| 34 | #define PI_MAX_CRB_TIMEOUT 0x000030 /* Maximum Timeout for CRB */ |
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| 35 | #define PI_CRB_SFACTOR 0x000038 /* Scale factor for CRB timeout */ |
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| 36 | |
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| 37 | /* CALIAS values */ |
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| 38 | #define PI_CALIAS_SIZE_0 0 |
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| 39 | #define PI_CALIAS_SIZE_4K 1 |
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| 40 | #define PI_CALIAS_SIZE_8K 2 |
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| 41 | #define PI_CALIAS_SIZE_16K 3 |
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| 42 | #define PI_CALIAS_SIZE_32K 4 |
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| 43 | #define PI_CALIAS_SIZE_64K 5 |
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| 44 | #define PI_CALIAS_SIZE_128K 6 |
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| 45 | #define PI_CALIAS_SIZE_256K 7 |
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| 46 | #define PI_CALIAS_SIZE_512K 8 |
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| 47 | #define PI_CALIAS_SIZE_1M 9 |
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| 48 | #define PI_CALIAS_SIZE_2M 10 |
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| 49 | #define PI_CALIAS_SIZE_4M 11 |
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| 50 | #define PI_CALIAS_SIZE_8M 12 |
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| 51 | #define PI_CALIAS_SIZE_16M 13 |
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| 52 | #define PI_CALIAS_SIZE_32M 14 |
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| 53 | #define PI_CALIAS_SIZE_64M 15 |
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| 54 | |
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| 55 | /* Processor control and status checking */ |
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| 56 | |
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| 57 | #define PI_CPU_PRESENT_A 0x000040 /* CPU Present A */ |
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| 58 | #define PI_CPU_PRESENT_B 0x000048 /* CPU Present B */ |
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| 59 | #define PI_CPU_ENABLE_A 0x000050 /* CPU Enable A */ |
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| 60 | #define PI_CPU_ENABLE_B 0x000058 /* CPU Enable B */ |
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| 61 | #define PI_REPLY_LEVEL 0x000060 /* Reply Level */ |
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| 62 | #define PI_HARDRESET_BIT 0x020068 /* Bit cleared by s/w on SR */ |
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| 63 | #define PI_NMI_A 0x000070 /* NMI to CPU A */ |
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| 64 | #define PI_NMI_B 0x000078 /* NMI to CPU B */ |
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| 65 | #define PI_NMI_OFFSET (PI_NMI_B - PI_NMI_A) |
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| 66 | #define PI_SOFTRESET 0x000080 /* Softreset (to both CPUs) */ |
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| 67 | |
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| 68 | /* Regular Interrupt register checking. */ |
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| 69 | |
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| 70 | #define PI_INT_PEND_MOD 0x000090 /* Write to set pending ints */ |
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| 71 | #define PI_INT_PEND0 0x000098 /* Read to get pending ints */ |
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| 72 | #define PI_INT_PEND1 0x0000a0 /* Read to get pending ints */ |
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| 73 | #define PI_INT_MASK0_A 0x0000a8 /* Interrupt Mask 0 for CPU A */ |
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| 74 | #define PI_INT_MASK1_A 0x0000b0 /* Interrupt Mask 1 for CPU A */ |
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| 75 | #define PI_INT_MASK0_B 0x0000b8 /* Interrupt Mask 0 for CPU B */ |
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| 76 | #define PI_INT_MASK1_B 0x0000c0 /* Interrupt Mask 1 for CPU B */ |
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| 77 | |
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| 78 | #define PI_INT_MASK_OFFSET 0x10 /* Offset from A to B */ |
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| 79 | |
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| 80 | /* Crosscall interrupts */ |
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| 81 | |
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| 82 | #define PI_CC_PEND_SET_A 0x0000c8 /* CC Interrupt Pending Set, CPU A */ |
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| 83 | #define PI_CC_PEND_SET_B 0x0000d0 /* CC Interrupt Pending Set, CPU B */ |
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| 84 | #define PI_CC_PEND_CLR_A 0x0000d8 /* CC Interrupt Pending Clr, CPU A */ |
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| 85 | #define PI_CC_PEND_CLR_B 0x0000e0 /* CC Interrupt Pending Clr, CPU B */ |
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| 86 | #define PI_CC_MASK 0x0000e8 /* CC Interrupt mask */ |
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| 87 | |
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| 88 | #define PI_INT_SET_OFFSET 0x08 /* Offset from A to B */ |
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| 89 | |
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| 90 | /* Realtime Counter and Profiler control registers */ |
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| 91 | |
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| 92 | #define PI_RT_COUNT 0x030100 /* Real Time Counter */ |
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| 93 | #define PI_RT_COMPARE_A 0x000108 /* Real Time Compare A */ |
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| 94 | #define PI_RT_COMPARE_B 0x000110 /* Real Time Compare B */ |
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| 95 | #define PI_PROFILE_COMPARE 0x000118 /* L5 int to both cpus when == RTC */ |
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| 96 | #define PI_RT_PEND_A 0x000120 /* Set if RT int for A pending */ |
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| 97 | #define PI_RT_PEND_B 0x000128 /* Set if RT int for B pending */ |
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| 98 | #define PI_PROF_PEND_A 0x000130 /* Set if Prof int for A pending */ |
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| 99 | #define PI_PROF_PEND_B 0x000138 /* Set if Prof int for B pending */ |
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| 100 | #define PI_RT_EN_A 0x000140 /* RT int for CPU A enable */ |
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| 101 | #define PI_RT_EN_B 0x000148 /* RT int for CPU B enable */ |
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| 102 | #define PI_PROF_EN_A 0x000150 /* PROF int for CPU A enable */ |
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| 103 | #define PI_PROF_EN_B 0x000158 /* PROF int for CPU B enable */ |
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| 104 | #define PI_RT_LOCAL_CTRL 0x000160 /* RT control register */ |
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| 105 | #define PI_RT_FILTER_CTRL 0x000168 /* GCLK Filter control register */ |
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| 106 | |
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| 107 | #define PI_COUNT_OFFSET 0x08 /* A to B offset for all counts */ |
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| 108 | |
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| 109 | /* Built-In Self Test support */ |
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| 110 | |
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| 111 | #define PI_BIST_WRITE_DATA 0x000200 /* BIST write data */ |
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| 112 | #define PI_BIST_READ_DATA 0x000208 /* BIST read data */ |
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| 113 | #define PI_BIST_COUNT_TARG 0x000210 /* BIST Count and Target */ |
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| 114 | #define PI_BIST_READY 0x000218 /* BIST Ready indicator */ |
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| 115 | #define PI_BIST_SHIFT_LOAD 0x000220 /* BIST control */ |
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| 116 | #define PI_BIST_SHIFT_UNLOAD 0x000228 /* BIST control */ |
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| 117 | #define PI_BIST_ENTER_RUN 0x000230 /* BIST control */ |
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| 118 | |
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| 119 | /* Graphics control registers */ |
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| 120 | |
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| 121 | #define PI_GFX_PAGE_A 0x000300 /* Graphics page A */ |
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| 122 | #define PI_GFX_CREDIT_CNTR_A 0x000308 /* Graphics credit counter A */ |
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| 123 | #define PI_GFX_BIAS_A 0x000310 /* Graphics bias A */ |
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| 124 | #define PI_GFX_INT_CNTR_A 0x000318 /* Graphics interrupt counter A */ |
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| 125 | #define PI_GFX_INT_CMP_A 0x000320 /* Graphics interrupt comparator A */ |
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| 126 | #define PI_GFX_PAGE_B 0x000328 /* Graphics page B */ |
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| 127 | #define PI_GFX_CREDIT_CNTR_B 0x000330 /* Graphics credit counter B */ |
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| 128 | #define PI_GFX_BIAS_B 0x000338 /* Graphics bias B */ |
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| 129 | #define PI_GFX_INT_CNTR_B 0x000340 /* Graphics interrupt counter B */ |
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| 130 | #define PI_GFX_INT_CMP_B 0x000348 /* Graphics interrupt comparator B */ |
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| 131 | |
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| 132 | #define PI_GFX_OFFSET (PI_GFX_PAGE_B - PI_GFX_PAGE_A) |
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| 133 | #define PI_GFX_PAGE_ENABLE 0x0000010000000000LL |
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| 134 | |
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| 135 | /* Error and timeout registers */ |
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| 136 | #define PI_ERR_INT_PEND 0x000400 /* Error Interrupt Pending */ |
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| 137 | #define PI_ERR_INT_MASK_A 0x000408 /* Error Interrupt mask for CPU A */ |
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| 138 | #define PI_ERR_INT_MASK_B 0x000410 /* Error Interrupt mask for CPU B */ |
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| 139 | #define PI_ERR_STACK_ADDR_A 0x000418 /* Error stack address for CPU A */ |
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| 140 | #define PI_ERR_STACK_ADDR_B 0x000420 /* Error stack address for CPU B */ |
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| 141 | #define PI_ERR_STACK_SIZE 0x000428 /* Error Stack Size */ |
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| 142 | #define PI_ERR_STATUS0_A 0x000430 /* Error Status 0A */ |
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| 143 | #define PI_ERR_STATUS0_A_RCLR 0x000438 /* Error Status 0A clear on read */ |
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| 144 | #define PI_ERR_STATUS1_A 0x000440 /* Error Status 1A */ |
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| 145 | #define PI_ERR_STATUS1_A_RCLR 0x000448 /* Error Status 1A clear on read */ |
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| 146 | #define PI_ERR_STATUS0_B 0x000450 /* Error Status 0B */ |
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| 147 | #define PI_ERR_STATUS0_B_RCLR 0x000458 /* Error Status 0B clear on read */ |
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| 148 | #define PI_ERR_STATUS1_B 0x000460 /* Error Status 1B */ |
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| 149 | #define PI_ERR_STATUS1_B_RCLR 0x000468 /* Error Status 1B clear on read */ |
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| 150 | #define PI_SPOOL_CMP_A 0x000470 /* Spool compare for CPU A */ |
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| 151 | #define PI_SPOOL_CMP_B 0x000478 /* Spool compare for CPU B */ |
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| 152 | #define PI_CRB_TIMEOUT_A 0x000480 /* Timed out CRB entries for A */ |
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| 153 | #define PI_CRB_TIMEOUT_B 0x000488 /* Timed out CRB entries for B */ |
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| 154 | #define PI_SYSAD_ERRCHK_EN 0x000490 /* Enables SYSAD error checking */ |
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| 155 | #define PI_BAD_CHECK_BIT_A 0x000498 /* Force SYSAD check bit error */ |
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| 156 | #define PI_BAD_CHECK_BIT_B 0x0004a0 /* Force SYSAD check bit error */ |
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| 157 | #define PI_NACK_CNT_A 0x0004a8 /* Consecutive NACK counter */ |
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| 158 | #define PI_NACK_CNT_B 0x0004b0 /* " " for CPU B */ |
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| 159 | #define PI_NACK_CMP 0x0004b8 /* NACK count compare */ |
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| 160 | #define PI_STACKADDR_OFFSET (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A) |
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| 161 | #define PI_ERRSTAT_OFFSET (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A) |
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| 162 | #define PI_RDCLR_OFFSET (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A) |
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| 163 | |
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| 164 | /* Bits in PI_ERR_INT_PEND */ |
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| 165 | #define PI_ERR_SPOOL_CMP_B 0x00000001 /* Spool end hit high water */ |
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| 166 | #define PI_ERR_SPOOL_CMP_A 0x00000002 |
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| 167 | #define PI_ERR_SPUR_MSG_B 0x00000004 /* Spurious message intr. */ |
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| 168 | #define PI_ERR_SPUR_MSG_A 0x00000008 |
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| 169 | #define PI_ERR_WRB_TERR_B 0x00000010 /* WRB TERR */ |
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| 170 | #define PI_ERR_WRB_TERR_A 0x00000020 |
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| 171 | #define PI_ERR_WRB_WERR_B 0x00000040 /* WRB WERR */ |
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| 172 | #define PI_ERR_WRB_WERR_A 0x00000080 |
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| 173 | #define PI_ERR_SYSSTATE_B 0x00000100 /* SysState parity error */ |
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| 174 | #define PI_ERR_SYSSTATE_A 0x00000200 |
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| 175 | #define PI_ERR_SYSAD_DATA_B 0x00000400 /* SysAD data parity error */ |
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| 176 | #define PI_ERR_SYSAD_DATA_A 0x00000800 |
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| 177 | #define PI_ERR_SYSAD_ADDR_B 0x00001000 /* SysAD addr parity error */ |
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| 178 | #define PI_ERR_SYSAD_ADDR_A 0x00002000 |
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| 179 | #define PI_ERR_SYSCMD_DATA_B 0x00004000 /* SysCmd data parity error */ |
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| 180 | #define PI_ERR_SYSCMD_DATA_A 0x00008000 |
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| 181 | #define PI_ERR_SYSCMD_ADDR_B 0x00010000 /* SysCmd addr parity error */ |
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| 182 | #define PI_ERR_SYSCMD_ADDR_A 0x00020000 |
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| 183 | #define PI_ERR_BAD_SPOOL_B 0x00040000 /* Error spooling to memory */ |
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| 184 | #define PI_ERR_BAD_SPOOL_A 0x00080000 |
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| 185 | #define PI_ERR_UNCAC_UNCORR_B 0x00100000 /* Uncached uncorrectable */ |
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| 186 | #define PI_ERR_UNCAC_UNCORR_A 0x00200000 |
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| 187 | #define PI_ERR_SYSSTATE_TAG_B 0x00400000 /* SysState tag parity error */ |
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| 188 | #define PI_ERR_SYSSTATE_TAG_A 0x00800000 |
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| 189 | #define PI_ERR_MD_UNCORR 0x01000000 /* Must be cleared in MD */ |
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| 190 | |
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| 191 | #define PI_ERR_CLEAR_ALL_A 0x00aaaaaa |
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| 192 | #define PI_ERR_CLEAR_ALL_B 0x00555555 |
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| 193 | |
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| 194 | |
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| 195 | /* |
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| 196 | * The following three macros define all possible error int pends. |
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| 197 | */ |
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| 198 | |
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| 199 | #define PI_FATAL_ERR_CPU_A (PI_ERR_SYSSTATE_TAG_A | \ |
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| 200 | PI_ERR_BAD_SPOOL_A | \ |
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| 201 | PI_ERR_SYSCMD_ADDR_A | \ |
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| 202 | PI_ERR_SYSCMD_DATA_A | \ |
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| 203 | PI_ERR_SYSAD_ADDR_A | \ |
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| 204 | PI_ERR_SYSAD_DATA_A | \ |
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| 205 | PI_ERR_SYSSTATE_A) |
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| 206 | |
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| 207 | #define PI_MISC_ERR_CPU_A (PI_ERR_UNCAC_UNCORR_A | \ |
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| 208 | PI_ERR_WRB_WERR_A | \ |
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| 209 | PI_ERR_WRB_TERR_A | \ |
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| 210 | PI_ERR_SPUR_MSG_A | \ |
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| 211 | PI_ERR_SPOOL_CMP_A) |
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| 212 | |
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| 213 | #define PI_FATAL_ERR_CPU_B (PI_ERR_SYSSTATE_TAG_B | \ |
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| 214 | PI_ERR_BAD_SPOOL_B | \ |
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| 215 | PI_ERR_SYSCMD_ADDR_B | \ |
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| 216 | PI_ERR_SYSCMD_DATA_B | \ |
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| 217 | PI_ERR_SYSAD_ADDR_B | \ |
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| 218 | PI_ERR_SYSAD_DATA_B | \ |
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| 219 | PI_ERR_SYSSTATE_B) |
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| 220 | |
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| 221 | #define PI_MISC_ERR_CPU_B (PI_ERR_UNCAC_UNCORR_B | \ |
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| 222 | PI_ERR_WRB_WERR_B | \ |
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| 223 | PI_ERR_WRB_TERR_B | \ |
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| 224 | PI_ERR_SPUR_MSG_B | \ |
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| 225 | PI_ERR_SPOOL_CMP_B) |
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| 226 | |
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| 227 | #define PI_ERR_GENERIC (PI_ERR_MD_UNCORR) |
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| 228 | |
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| 229 | /* |
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| 230 | * Error types for PI_ERR_STATUS0_[AB] and error stack: |
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| 231 | * Use the write types if WRBRRB is 1 else use the read types |
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| 232 | */ |
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| 233 | |
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| 234 | /* Fields in PI_ERR_STATUS0_[AB] */ |
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| 235 | #define PI_ERR_ST0_TYPE_MASK 0x0000000000000007 |
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| 236 | #define PI_ERR_ST0_TYPE_SHFT 0 |
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| 237 | #define PI_ERR_ST0_REQNUM_MASK 0x0000000000000038 |
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| 238 | #define PI_ERR_ST0_REQNUM_SHFT 3 |
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| 239 | #define PI_ERR_ST0_SUPPL_MASK 0x000000000001ffc0 |
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| 240 | #define PI_ERR_ST0_SUPPL_SHFT 6 |
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| 241 | #define PI_ERR_ST0_CMD_MASK 0x0000000001fe0000 |
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| 242 | #define PI_ERR_ST0_CMD_SHFT 17 |
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| 243 | #define PI_ERR_ST0_ADDR_MASK 0x3ffffffffe000000 |
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| 244 | #define PI_ERR_ST0_ADDR_SHFT 25 |
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| 245 | #define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000 |
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| 246 | #define PI_ERR_ST0_OVERRUN_SHFT 62 |
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| 247 | #define PI_ERR_ST0_VALID_MASK 0x8000000000000000 |
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| 248 | #define PI_ERR_ST0_VALID_SHFT 63 |
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| 249 | |
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| 250 | /* Fields in PI_ERR_STATUS1_[AB] */ |
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| 251 | #define PI_ERR_ST1_SPOOL_MASK 0x00000000001fffff |
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| 252 | #define PI_ERR_ST1_SPOOL_SHFT 0 |
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| 253 | #define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000 |
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| 254 | #define PI_ERR_ST1_TOUTCNT_SHFT 21 |
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| 255 | #define PI_ERR_ST1_INVCNT_MASK 0x0000007fe0000000 |
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| 256 | #define PI_ERR_ST1_INVCNT_SHFT 29 |
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| 257 | #define PI_ERR_ST1_CRBNUM_MASK 0x0000038000000000 |
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| 258 | #define PI_ERR_ST1_CRBNUM_SHFT 39 |
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| 259 | #define PI_ERR_ST1_WRBRRB_MASK 0x0000040000000000 |
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| 260 | #define PI_ERR_ST1_WRBRRB_SHFT 42 |
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| 261 | #define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000 |
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| 262 | #define PI_ERR_ST1_CRBSTAT_SHFT 43 |
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| 263 | #define PI_ERR_ST1_MSGSRC_MASK 0xffe0000000000000 |
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| 264 | #define PI_ERR_ST1_MSGSRC_SHFT 53 |
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| 265 | |
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| 266 | /* Fields in the error stack */ |
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| 267 | #define PI_ERR_STK_TYPE_MASK 0x0000000000000003 |
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| 268 | #define PI_ERR_STK_TYPE_SHFT 0 |
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| 269 | #define PI_ERR_STK_SUPPL_MASK 0x0000000000000038 |
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| 270 | #define PI_ERR_STK_SUPPL_SHFT 3 |
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| 271 | #define PI_ERR_STK_REQNUM_MASK 0x00000000000001c0 |
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| 272 | #define PI_ERR_STK_REQNUM_SHFT 6 |
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| 273 | #define PI_ERR_STK_CRBNUM_MASK 0x0000000000000e00 |
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| 274 | #define PI_ERR_STK_CRBNUM_SHFT 9 |
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| 275 | #define PI_ERR_STK_WRBRRB_MASK 0x0000000000001000 |
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| 276 | #define PI_ERR_STK_WRBRRB_SHFT 12 |
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| 277 | #define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000 |
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| 278 | #define PI_ERR_STK_CRBSTAT_SHFT 13 |
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| 279 | #define PI_ERR_STK_CMD_MASK 0x000000007f800000 |
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| 280 | #define PI_ERR_STK_CMD_SHFT 23 |
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| 281 | #define PI_ERR_STK_ADDR_MASK 0xffffffff80000000 |
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| 282 | #define PI_ERR_STK_ADDR_SHFT 31 |
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| 283 | |
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| 284 | /* Error type in the error status or stack on Read CRBs */ |
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| 285 | #define PI_ERR_RD_PRERR 1 |
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| 286 | #define PI_ERR_RD_DERR 2 |
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| 287 | #define PI_ERR_RD_TERR 3 |
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| 288 | |
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| 289 | /* Error type in the error status or stack on Write CRBs */ |
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| 290 | #define PI_ERR_WR_WERR 0 |
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| 291 | #define PI_ERR_WR_PWERR 1 |
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| 292 | #define PI_ERR_WR_TERR 3 |
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| 293 | |
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| 294 | /* Read or Write CRB in error status or stack */ |
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| 295 | #define PI_ERR_RRB 0 |
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| 296 | #define PI_ERR_WRB 1 |
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| 297 | #define PI_ERR_ANY_CRB 2 |
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| 298 | |
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| 299 | /* Address masks in the error status and error stack are not the same */ |
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| 300 | #define ERR_STK_ADDR_SHFT 7 |
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| 301 | #define ERR_STAT0_ADDR_SHFT 3 |
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| 302 | |
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| 303 | #define PI_MIN_STACK_SIZE 4096 /* For figuring out the size to set */ |
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| 304 | #define PI_STACK_SIZE_SHFT 12 /* 4k */ |
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| 305 | |
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| 306 | #define ERR_STACK_SIZE_BYTES(_sz) \ |
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| 307 | ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0) |
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| 308 | |
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| 309 | #ifndef __ASSEMBLY__ |
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| 310 | /* |
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| 311 | * format of error stack and error status registers. |
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| 312 | */ |
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| 313 | |
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| 314 | struct err_stack_format { |
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| 315 | __u64 sk_addr : 33, /* address */ |
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| 316 | sk_cmd : 8, /* message command */ |
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| 317 | sk_crb_sts : 10, /* status from RRB or WRB */ |
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| 318 | sk_rw_rb : 1, /* RRB == 0, WRB == 1 */ |
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| 319 | sk_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ |
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| 320 | sk_t5_req : 3, /* RRB T5 request number */ |
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| 321 | sk_suppl : 3, /* lowest 3 bit of supplemental */ |
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| 322 | sk_err_type: 3; /* error type */ |
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| 323 | }; |
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| 324 | |
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| 325 | typedef union pi_err_stack { |
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| 326 | __u64 pi_stk_word; |
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| 327 | struct err_stack_format pi_stk_fmt; |
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| 328 | } pi_err_stack_t; |
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| 329 | |
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| 330 | struct err_status0_format { |
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| 331 | __u64 s0_valid : 1, /* Valid */ |
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| 332 | s0_ovr_run : 1, /* Overrun, spooled to memory */ |
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| 333 | s0_addr : 37, /* address */ |
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| 334 | s0_cmd : 8, /* message command */ |
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| 335 | s0_supl : 11, /* message supplemental field */ |
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| 336 | s0_t5_req : 3, /* RRB T5 request number */ |
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| 337 | s0_err_type: 3; /* error type */ |
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| 338 | }; |
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| 339 | |
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| 340 | typedef union pi_err_stat0 { |
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| 341 | __u64 pi_stat0_word; |
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| 342 | struct err_status0_format pi_stat0_fmt; |
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| 343 | } pi_err_stat0_t; |
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| 344 | |
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| 345 | struct err_status1_format { |
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| 346 | __u64 s1_src : 11, /* message source */ |
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| 347 | s1_crb_sts : 10, /* status from RRB or WRB */ |
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| 348 | s1_rw_rb : 1, /* RRB == 0, WRB == 1 */ |
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| 349 | s1_crb_num : 3, /* WRB (0 to 7) or RRB (0 to 4) */ |
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| 350 | s1_inval_cnt:10, /* signed invalidate counter RRB */ |
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| 351 | s1_to_cnt : 8, /* crb timeout counter */ |
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| 352 | s1_spl_cnt : 21; /* number spooled to memory */ |
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| 353 | }; |
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| 354 | |
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| 355 | typedef union pi_err_stat1 { |
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| 356 | __u64 pi_stat1_word; |
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| 357 | struct err_status1_format pi_stat1_fmt; |
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| 358 | } pi_err_stat1_t; |
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| 359 | |
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| 360 | typedef __u64 rtc_time_t; |
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| 361 | |
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| 362 | #endif /* !__ASSEMBLY__ */ |
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| 363 | |
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| 364 | |
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| 365 | /* Bits in PI_SYSAD_ERRCHK_EN */ |
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| 366 | #define PI_SYSAD_ERRCHK_ECCGEN 0x01 /* Enable ECC generation */ |
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| 367 | #define PI_SYSAD_ERRCHK_QUALGEN 0x02 /* Enable data quality signal gen. */ |
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| 368 | #define PI_SYSAD_ERRCHK_SADP 0x04 /* Enable SysAD parity checking */ |
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| 369 | #define PI_SYSAD_ERRCHK_CMDP 0x08 /* Enable SysCmd parity checking */ |
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| 370 | #define PI_SYSAD_ERRCHK_STATE 0x10 /* Enable SysState parity checking */ |
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| 371 | #define PI_SYSAD_ERRCHK_QUAL 0x20 /* Enable data quality checking */ |
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| 372 | #define PI_SYSAD_CHECK_ALL 0x3f /* Generate and check all signals. */ |
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| 373 | |
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| 374 | /* Interrupt pending bits on R10000 */ |
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| 375 | |
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| 376 | #define HUB_IP_PEND0 0x0400 |
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| 377 | #define HUB_IP_PEND1_CC 0x0800 |
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| 378 | #define HUB_IP_RT 0x1000 |
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| 379 | #define HUB_IP_PROF 0x2000 |
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| 380 | #define HUB_IP_ERROR 0x4000 |
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| 381 | #define HUB_IP_MASK 0x7c00 |
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| 382 | |
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| 383 | /* PI_RT_LOCAL_CTRL mask and shift definitions */ |
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| 384 | |
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| 385 | #define PRLC_USE_INT_SHFT 16 |
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| 386 | #define PRLC_USE_INT_MASK (UINT64_CAST 1 << 16) |
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| 387 | #define PRLC_USE_INT (UINT64_CAST 1 << 16) |
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| 388 | #define PRLC_GCLK_SHFT 15 |
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| 389 | #define PRLC_GCLK_MASK (UINT64_CAST 1 << 15) |
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| 390 | #define PRLC_GCLK (UINT64_CAST 1 << 15) |
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| 391 | #define PRLC_GCLK_COUNT_SHFT 8 |
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| 392 | #define PRLC_GCLK_COUNT_MASK (UINT64_CAST 0x7f << 8) |
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| 393 | #define PRLC_MAX_COUNT_SHFT 1 |
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| 394 | #define PRLC_MAX_COUNT_MASK (UINT64_CAST 0x7f << 1) |
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| 395 | #define PRLC_GCLK_EN_SHFT 0 |
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| 396 | #define PRLC_GCLK_EN_MASK (UINT64_CAST 1) |
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| 397 | #define PRLC_GCLK_EN (UINT64_CAST 1) |
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| 398 | |
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| 399 | /* PI_RT_FILTER_CTRL mask and shift definitions */ |
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| 400 | |
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| 401 | #if 0 |
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| 402 | /* |
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| 403 | * XXX - This register's definition has changed, but it's only implemented |
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| 404 | * in Hub 2. |
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| 405 | */ |
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| 406 | #define PRFC_DROP_COUNT_SHFT 27 |
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| 407 | #define PRFC_DROP_COUNT_MASK (UINT64_CAST 0x3ff << 27) |
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| 408 | #define PRFC_DROP_CTR_SHFT 18 |
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| 409 | #define PRFC_DROP_CTR_MASK (UINT64_CAST 0x1ff << 18) |
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| 410 | #define PRFC_MASK_ENABLE_SHFT 10 |
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| 411 | #define PRFC_MASK_ENABLE_MASK (UINT64_CAST 0x7f << 10) |
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| 412 | #define PRFC_MASK_CTR_SHFT 2 |
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| 413 | #define PRFC_MASK_CTR_MASK (UINT64_CAST 0xff << 2) |
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| 414 | #define PRFC_OFFSET_SHFT 0 |
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| 415 | #define PRFC_OFFSET_MASK (UINT64_CAST 3) |
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| 416 | #endif /* 0 */ |
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| 417 | |
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| 418 | |
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| 419 | /* |
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| 420 | * Bits for NACK_CNT_A/B and NACK_CMP |
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| 421 | */ |
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| 422 | #define PI_NACK_CNT_EN_SHFT 20 |
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| 423 | #define PI_NACK_CNT_EN_MASK 0x100000 |
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| 424 | #define PI_NACK_CNT_MASK 0x0fffff |
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| 425 | #define PI_NACK_CNT_MAX 0x0fffff |
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| 426 | |
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| 427 | #endif /* _ASM_SN_SN0_HUBPI_H */ |
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