| [2] | 1 | /* |
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| 2 | * Copyright (C) 2000, 2004, 2005 MIPS Technologies, Inc. |
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| 3 | * All rights reserved. |
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| 4 | * Authors: Carsten Langgaard <carstenl@mips.com> |
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| 5 | * Maciej W. Rozycki <macro@mips.com> |
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| 6 | * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) |
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| 7 | * |
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| 8 | * This program is free software; you can distribute it and/or modify it |
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| 9 | * under the terms of the GNU General Public License (Version 2) as |
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| 10 | * published by the Free Software Foundation. |
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| 11 | * |
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| 12 | * This program is distributed in the hope it will be useful, but WITHOUT |
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| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
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| 15 | * for more details. |
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| 16 | * |
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| 17 | * You should have received a copy of the GNU General Public License along |
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| 18 | * with this program; if not, write to the Free Software Foundation, Inc., |
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| 19 | * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. |
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| 20 | */ |
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| 21 | #ifndef _ASM_GT64120_H |
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| 22 | #define _ASM_GT64120_H |
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| 23 | |
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| 24 | #include <asm/addrspace.h> |
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| 25 | #include <asm/byteorder.h> |
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| 26 | |
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| 27 | #define MSK(n) ((1 << (n)) - 1) |
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| 28 | |
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| 29 | /* |
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| 30 | * Register offset addresses |
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| 31 | */ |
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| 32 | /* CPU Configuration. */ |
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| 33 | #define GT_CPU_OFS 0x000 |
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| 34 | |
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| 35 | #define GT_MULTI_OFS 0x120 |
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| 36 | |
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| 37 | /* CPU Address Decode. */ |
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| 38 | #define GT_SCS10LD_OFS 0x008 |
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| 39 | #define GT_SCS10HD_OFS 0x010 |
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| 40 | #define GT_SCS32LD_OFS 0x018 |
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| 41 | #define GT_SCS32HD_OFS 0x020 |
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| 42 | #define GT_CS20LD_OFS 0x028 |
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| 43 | #define GT_CS20HD_OFS 0x030 |
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| 44 | #define GT_CS3BOOTLD_OFS 0x038 |
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| 45 | #define GT_CS3BOOTHD_OFS 0x040 |
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| 46 | #define GT_PCI0IOLD_OFS 0x048 |
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| 47 | #define GT_PCI0IOHD_OFS 0x050 |
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| 48 | #define GT_PCI0M0LD_OFS 0x058 |
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| 49 | #define GT_PCI0M0HD_OFS 0x060 |
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| 50 | #define GT_ISD_OFS 0x068 |
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| 51 | |
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| 52 | #define GT_PCI0M1LD_OFS 0x080 |
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| 53 | #define GT_PCI0M1HD_OFS 0x088 |
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| 54 | #define GT_PCI1IOLD_OFS 0x090 |
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| 55 | #define GT_PCI1IOHD_OFS 0x098 |
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| 56 | #define GT_PCI1M0LD_OFS 0x0a0 |
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| 57 | #define GT_PCI1M0HD_OFS 0x0a8 |
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| 58 | #define GT_PCI1M1LD_OFS 0x0b0 |
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| 59 | #define GT_PCI1M1HD_OFS 0x0b8 |
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| 60 | #define GT_PCI1M1LD_OFS 0x0b0 |
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| 61 | #define GT_PCI1M1HD_OFS 0x0b8 |
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| 62 | |
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| 63 | #define GT_SCS10AR_OFS 0x0d0 |
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| 64 | #define GT_SCS32AR_OFS 0x0d8 |
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| 65 | #define GT_CS20R_OFS 0x0e0 |
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| 66 | #define GT_CS3BOOTR_OFS 0x0e8 |
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| 67 | |
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| 68 | #define GT_PCI0IOREMAP_OFS 0x0f0 |
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| 69 | #define GT_PCI0M0REMAP_OFS 0x0f8 |
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| 70 | #define GT_PCI0M1REMAP_OFS 0x100 |
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| 71 | #define GT_PCI1IOREMAP_OFS 0x108 |
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| 72 | #define GT_PCI1M0REMAP_OFS 0x110 |
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| 73 | #define GT_PCI1M1REMAP_OFS 0x118 |
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| 74 | |
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| 75 | /* CPU Error Report. */ |
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| 76 | #define GT_CPUERR_ADDRLO_OFS 0x070 |
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| 77 | #define GT_CPUERR_ADDRHI_OFS 0x078 |
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| 78 | |
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| 79 | #define GT_CPUERR_DATALO_OFS 0x128 /* GT-64120A only */ |
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| 80 | #define GT_CPUERR_DATAHI_OFS 0x130 /* GT-64120A only */ |
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| 81 | #define GT_CPUERR_PARITY_OFS 0x138 /* GT-64120A only */ |
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| 82 | |
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| 83 | /* CPU Sync Barrier. */ |
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| 84 | #define GT_PCI0SYNC_OFS 0x0c0 |
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| 85 | #define GT_PCI1SYNC_OFS 0x0c8 |
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| 86 | |
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| 87 | /* SDRAM and Device Address Decode. */ |
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| 88 | #define GT_SCS0LD_OFS 0x400 |
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| 89 | #define GT_SCS0HD_OFS 0x404 |
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| 90 | #define GT_SCS1LD_OFS 0x408 |
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| 91 | #define GT_SCS1HD_OFS 0x40c |
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| 92 | #define GT_SCS2LD_OFS 0x410 |
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| 93 | #define GT_SCS2HD_OFS 0x414 |
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| 94 | #define GT_SCS3LD_OFS 0x418 |
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| 95 | #define GT_SCS3HD_OFS 0x41c |
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| 96 | #define GT_CS0LD_OFS 0x420 |
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| 97 | #define GT_CS0HD_OFS 0x424 |
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| 98 | #define GT_CS1LD_OFS 0x428 |
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| 99 | #define GT_CS1HD_OFS 0x42c |
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| 100 | #define GT_CS2LD_OFS 0x430 |
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| 101 | #define GT_CS2HD_OFS 0x434 |
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| 102 | #define GT_CS3LD_OFS 0x438 |
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| 103 | #define GT_CS3HD_OFS 0x43c |
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| 104 | #define GT_BOOTLD_OFS 0x440 |
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| 105 | #define GT_BOOTHD_OFS 0x444 |
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| 106 | |
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| 107 | #define GT_ADERR_OFS 0x470 |
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| 108 | |
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| 109 | /* SDRAM Configuration. */ |
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| 110 | #define GT_SDRAM_CFG_OFS 0x448 |
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| 111 | |
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| 112 | #define GT_SDRAM_OPMODE_OFS 0x474 |
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| 113 | #define GT_SDRAM_BM_OFS 0x478 |
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| 114 | #define GT_SDRAM_ADDRDECODE_OFS 0x47c |
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| 115 | |
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| 116 | /* SDRAM Parameters. */ |
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| 117 | #define GT_SDRAM_B0_OFS 0x44c |
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| 118 | #define GT_SDRAM_B1_OFS 0x450 |
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| 119 | #define GT_SDRAM_B2_OFS 0x454 |
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| 120 | #define GT_SDRAM_B3_OFS 0x458 |
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| 121 | |
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| 122 | /* Device Parameters. */ |
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| 123 | #define GT_DEV_B0_OFS 0x45c |
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| 124 | #define GT_DEV_B1_OFS 0x460 |
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| 125 | #define GT_DEV_B2_OFS 0x464 |
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| 126 | #define GT_DEV_B3_OFS 0x468 |
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| 127 | #define GT_DEV_BOOT_OFS 0x46c |
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| 128 | |
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| 129 | /* ECC. */ |
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| 130 | #define GT_ECC_ERRDATALO 0x480 /* GT-64120A only */ |
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| 131 | #define GT_ECC_ERRDATAHI 0x484 /* GT-64120A only */ |
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| 132 | #define GT_ECC_MEM 0x488 /* GT-64120A only */ |
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| 133 | #define GT_ECC_CALC 0x48c /* GT-64120A only */ |
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| 134 | #define GT_ECC_ERRADDR 0x490 /* GT-64120A only */ |
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| 135 | |
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| 136 | /* DMA Record. */ |
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| 137 | #define GT_DMA0_CNT_OFS 0x800 |
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| 138 | #define GT_DMA1_CNT_OFS 0x804 |
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| 139 | #define GT_DMA2_CNT_OFS 0x808 |
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| 140 | #define GT_DMA3_CNT_OFS 0x80c |
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| 141 | #define GT_DMA0_SA_OFS 0x810 |
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| 142 | #define GT_DMA1_SA_OFS 0x814 |
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| 143 | #define GT_DMA2_SA_OFS 0x818 |
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| 144 | #define GT_DMA3_SA_OFS 0x81c |
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| 145 | #define GT_DMA0_DA_OFS 0x820 |
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| 146 | #define GT_DMA1_DA_OFS 0x824 |
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| 147 | #define GT_DMA2_DA_OFS 0x828 |
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| 148 | #define GT_DMA3_DA_OFS 0x82c |
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| 149 | #define GT_DMA0_NEXT_OFS 0x830 |
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| 150 | #define GT_DMA1_NEXT_OFS 0x834 |
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| 151 | #define GT_DMA2_NEXT_OFS 0x838 |
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| 152 | #define GT_DMA3_NEXT_OFS 0x83c |
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| 153 | |
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| 154 | #define GT_DMA0_CUR_OFS 0x870 |
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| 155 | #define GT_DMA1_CUR_OFS 0x874 |
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| 156 | #define GT_DMA2_CUR_OFS 0x878 |
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| 157 | #define GT_DMA3_CUR_OFS 0x87c |
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| 158 | |
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| 159 | /* DMA Channel Control. */ |
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| 160 | #define GT_DMA0_CTRL_OFS 0x840 |
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| 161 | #define GT_DMA1_CTRL_OFS 0x844 |
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| 162 | #define GT_DMA2_CTRL_OFS 0x848 |
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| 163 | #define GT_DMA3_CTRL_OFS 0x84c |
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| 164 | |
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| 165 | /* DMA Arbiter. */ |
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| 166 | #define GT_DMA_ARB_OFS 0x860 |
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| 167 | |
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| 168 | /* Timer/Counter. */ |
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| 169 | #define GT_TC0_OFS 0x850 |
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| 170 | #define GT_TC1_OFS 0x854 |
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| 171 | #define GT_TC2_OFS 0x858 |
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| 172 | #define GT_TC3_OFS 0x85c |
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| 173 | |
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| 174 | #define GT_TC_CONTROL_OFS 0x864 |
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| 175 | |
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| 176 | /* PCI Internal. */ |
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| 177 | #define GT_PCI0_CMD_OFS 0xc00 |
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| 178 | #define GT_PCI0_TOR_OFS 0xc04 |
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| 179 | #define GT_PCI0_BS_SCS10_OFS 0xc08 |
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| 180 | #define GT_PCI0_BS_SCS32_OFS 0xc0c |
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| 181 | #define GT_PCI0_BS_CS20_OFS 0xc10 |
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| 182 | #define GT_PCI0_BS_CS3BT_OFS 0xc14 |
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| 183 | |
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| 184 | #define GT_PCI1_IACK_OFS 0xc30 |
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| 185 | #define GT_PCI0_IACK_OFS 0xc34 |
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| 186 | |
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| 187 | #define GT_PCI0_BARE_OFS 0xc3c |
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| 188 | #define GT_PCI0_PREFMBR_OFS 0xc40 |
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| 189 | |
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| 190 | #define GT_PCI0_SCS10_BAR_OFS 0xc48 |
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| 191 | #define GT_PCI0_SCS32_BAR_OFS 0xc4c |
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| 192 | #define GT_PCI0_CS20_BAR_OFS 0xc50 |
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| 193 | #define GT_PCI0_CS3BT_BAR_OFS 0xc54 |
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| 194 | #define GT_PCI0_SSCS10_BAR_OFS 0xc58 |
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| 195 | #define GT_PCI0_SSCS32_BAR_OFS 0xc5c |
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| 196 | |
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| 197 | #define GT_PCI0_SCS3BT_BAR_OFS 0xc64 |
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| 198 | |
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| 199 | #define GT_PCI1_CMD_OFS 0xc80 |
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| 200 | #define GT_PCI1_TOR_OFS 0xc84 |
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| 201 | #define GT_PCI1_BS_SCS10_OFS 0xc88 |
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| 202 | #define GT_PCI1_BS_SCS32_OFS 0xc8c |
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| 203 | #define GT_PCI1_BS_CS20_OFS 0xc90 |
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| 204 | #define GT_PCI1_BS_CS3BT_OFS 0xc94 |
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| 205 | |
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| 206 | #define GT_PCI1_BARE_OFS 0xcbc |
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| 207 | #define GT_PCI1_PREFMBR_OFS 0xcc0 |
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| 208 | |
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| 209 | #define GT_PCI1_SCS10_BAR_OFS 0xcc8 |
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| 210 | #define GT_PCI1_SCS32_BAR_OFS 0xccc |
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| 211 | #define GT_PCI1_CS20_BAR_OFS 0xcd0 |
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| 212 | #define GT_PCI1_CS3BT_BAR_OFS 0xcd4 |
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| 213 | #define GT_PCI1_SSCS10_BAR_OFS 0xcd8 |
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| 214 | #define GT_PCI1_SSCS32_BAR_OFS 0xcdc |
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| 215 | |
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| 216 | #define GT_PCI1_SCS3BT_BAR_OFS 0xce4 |
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| 217 | |
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| 218 | #define GT_PCI1_CFGADDR_OFS 0xcf0 |
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| 219 | #define GT_PCI1_CFGDATA_OFS 0xcf4 |
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| 220 | #define GT_PCI0_CFGADDR_OFS 0xcf8 |
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| 221 | #define GT_PCI0_CFGDATA_OFS 0xcfc |
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| 222 | |
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| 223 | /* Interrupts. */ |
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| 224 | #define GT_INTRCAUSE_OFS 0xc18 |
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| 225 | #define GT_INTRMASK_OFS 0xc1c |
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| 226 | |
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| 227 | #define GT_PCI0_ICMASK_OFS 0xc24 |
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| 228 | #define GT_PCI0_SERR0MASK_OFS 0xc28 |
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| 229 | |
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| 230 | #define GT_CPU_INTSEL_OFS 0xc70 |
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| 231 | #define GT_PCI0_INTSEL_OFS 0xc74 |
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| 232 | |
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| 233 | #define GT_HINTRCAUSE_OFS 0xc98 |
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| 234 | #define GT_HINTRMASK_OFS 0xc9c |
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| 235 | |
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| 236 | #define GT_PCI0_HICMASK_OFS 0xca4 |
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| 237 | #define GT_PCI1_SERR1MASK_OFS 0xca8 |
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| 238 | |
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| 239 | |
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| 240 | /* |
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| 241 | * I2O Support Registers |
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| 242 | */ |
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| 243 | #define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010 |
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| 244 | #define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014 |
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| 245 | #define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018 |
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| 246 | #define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c |
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| 247 | #define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020 |
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| 248 | #define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024 |
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| 249 | #define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028 |
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| 250 | #define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c |
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| 251 | #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030 |
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| 252 | #define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034 |
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| 253 | #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040 |
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| 254 | #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044 |
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| 255 | #define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050 |
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| 256 | #define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054 |
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| 257 | #define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060 |
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| 258 | #define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064 |
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| 259 | #define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068 |
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| 260 | #define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c |
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| 261 | #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070 |
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| 262 | #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074 |
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| 263 | #define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078 |
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| 264 | #define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c |
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| 265 | |
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| 266 | #define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10 |
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| 267 | #define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14 |
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| 268 | #define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18 |
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| 269 | #define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c |
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| 270 | #define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20 |
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| 271 | #define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24 |
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| 272 | #define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28 |
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| 273 | #define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c |
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| 274 | #define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30 |
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| 275 | #define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34 |
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| 276 | #define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40 |
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| 277 | #define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44 |
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| 278 | #define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50 |
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| 279 | #define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54 |
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| 280 | #define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60 |
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| 281 | #define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64 |
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| 282 | #define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68 |
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| 283 | #define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c |
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| 284 | #define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70 |
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| 285 | #define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74 |
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| 286 | #define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78 |
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| 287 | #define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c |
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| 288 | |
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| 289 | /* |
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| 290 | * Register encodings |
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| 291 | */ |
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| 292 | #define GT_CPU_ENDIAN_SHF 12 |
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| 293 | #define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF) |
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| 294 | #define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK |
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| 295 | #define GT_CPU_WR_SHF 16 |
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| 296 | #define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF) |
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| 297 | #define GT_CPU_WR_BIT GT_CPU_WR_MSK |
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| 298 | #define GT_CPU_WR_DXDXDXDX 0 |
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| 299 | #define GT_CPU_WR_DDDD 1 |
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| 300 | |
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| 301 | |
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| 302 | #define GT_PCI_DCRM_SHF 21 |
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| 303 | #define GT_PCI_LD_SHF 0 |
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| 304 | #define GT_PCI_LD_MSK (MSK(15) << GT_PCI_LD_SHF) |
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| 305 | #define GT_PCI_HD_SHF 0 |
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| 306 | #define GT_PCI_HD_MSK (MSK(7) << GT_PCI_HD_SHF) |
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| 307 | #define GT_PCI_REMAP_SHF 0 |
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| 308 | #define GT_PCI_REMAP_MSK (MSK(11) << GT_PCI_REMAP_SHF) |
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| 309 | |
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| 310 | |
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| 311 | #define GT_CFGADDR_CFGEN_SHF 31 |
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| 312 | #define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF) |
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| 313 | #define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK |
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| 314 | |
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| 315 | #define GT_CFGADDR_BUSNUM_SHF 16 |
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| 316 | #define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF) |
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| 317 | |
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| 318 | #define GT_CFGADDR_DEVNUM_SHF 11 |
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| 319 | #define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF) |
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| 320 | |
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| 321 | #define GT_CFGADDR_FUNCNUM_SHF 8 |
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| 322 | #define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF) |
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| 323 | |
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| 324 | #define GT_CFGADDR_REGNUM_SHF 2 |
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| 325 | #define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF) |
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| 326 | |
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| 327 | |
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| 328 | #define GT_SDRAM_BM_ORDER_SHF 2 |
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| 329 | #define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF) |
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| 330 | #define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK |
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| 331 | #define GT_SDRAM_BM_ORDER_SUB 1 |
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| 332 | #define GT_SDRAM_BM_ORDER_LIN 0 |
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| 333 | |
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| 334 | #define GT_SDRAM_BM_RSVD_ALL1 0xffb |
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| 335 | |
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| 336 | |
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| 337 | #define GT_SDRAM_ADDRDECODE_ADDR_SHF 0 |
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| 338 | #define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF) |
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| 339 | #define GT_SDRAM_ADDRDECODE_ADDR_0 0 |
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| 340 | #define GT_SDRAM_ADDRDECODE_ADDR_1 1 |
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| 341 | #define GT_SDRAM_ADDRDECODE_ADDR_2 2 |
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| 342 | #define GT_SDRAM_ADDRDECODE_ADDR_3 3 |
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| 343 | #define GT_SDRAM_ADDRDECODE_ADDR_4 4 |
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| 344 | #define GT_SDRAM_ADDRDECODE_ADDR_5 5 |
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| 345 | #define GT_SDRAM_ADDRDECODE_ADDR_6 6 |
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| 346 | #define GT_SDRAM_ADDRDECODE_ADDR_7 7 |
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| 347 | |
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| 348 | |
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| 349 | #define GT_SDRAM_B0_CASLAT_SHF 0 |
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| 350 | #define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF) |
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| 351 | #define GT_SDRAM_B0_CASLAT_2 1 |
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| 352 | #define GT_SDRAM_B0_CASLAT_3 2 |
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| 353 | |
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| 354 | #define GT_SDRAM_B0_FTDIS_SHF 2 |
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| 355 | #define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF) |
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| 356 | #define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK |
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| 357 | |
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| 358 | #define GT_SDRAM_B0_SRASPRCHG_SHF 3 |
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| 359 | #define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF) |
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| 360 | #define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK |
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| 361 | #define GT_SDRAM_B0_SRASPRCHG_2 0 |
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| 362 | #define GT_SDRAM_B0_SRASPRCHG_3 1 |
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| 363 | |
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| 364 | #define GT_SDRAM_B0_B0COMPAB_SHF 4 |
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| 365 | #define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF) |
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| 366 | #define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK |
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| 367 | |
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| 368 | #define GT_SDRAM_B0_64BITINT_SHF 5 |
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| 369 | #define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF) |
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| 370 | #define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK |
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| 371 | #define GT_SDRAM_B0_64BITINT_2 0 |
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| 372 | #define GT_SDRAM_B0_64BITINT_4 1 |
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| 373 | |
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| 374 | #define GT_SDRAM_B0_BW_SHF 6 |
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| 375 | #define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF) |
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| 376 | #define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK |
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| 377 | #define GT_SDRAM_B0_BW_32 0 |
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| 378 | #define GT_SDRAM_B0_BW_64 1 |
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| 379 | |
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| 380 | #define GT_SDRAM_B0_BLODD_SHF 7 |
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| 381 | #define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF) |
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| 382 | #define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK |
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| 383 | |
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| 384 | #define GT_SDRAM_B0_PAR_SHF 8 |
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| 385 | #define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF) |
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| 386 | #define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK |
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| 387 | |
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| 388 | #define GT_SDRAM_B0_BYPASS_SHF 9 |
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| 389 | #define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF) |
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| 390 | #define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK |
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| 391 | |
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| 392 | #define GT_SDRAM_B0_SRAS2SCAS_SHF 10 |
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| 393 | #define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF) |
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| 394 | #define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK |
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| 395 | #define GT_SDRAM_B0_SRAS2SCAS_2 0 |
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| 396 | #define GT_SDRAM_B0_SRAS2SCAS_3 1 |
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| 397 | |
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| 398 | #define GT_SDRAM_B0_SIZE_SHF 11 |
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| 399 | #define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF) |
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| 400 | #define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK |
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| 401 | #define GT_SDRAM_B0_SIZE_16M 0 |
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| 402 | #define GT_SDRAM_B0_SIZE_64M 1 |
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| 403 | |
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| 404 | #define GT_SDRAM_B0_EXTPAR_SHF 12 |
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| 405 | #define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF) |
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| 406 | #define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK |
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| 407 | |
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| 408 | #define GT_SDRAM_B0_BLEN_SHF 13 |
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| 409 | #define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF) |
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| 410 | #define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK |
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| 411 | #define GT_SDRAM_B0_BLEN_8 0 |
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| 412 | #define GT_SDRAM_B0_BLEN_4 1 |
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| 413 | |
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| 414 | |
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| 415 | #define GT_SDRAM_CFG_REFINT_SHF 0 |
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| 416 | #define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF) |
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| 417 | |
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| 418 | #define GT_SDRAM_CFG_NINTERLEAVE_SHF 14 |
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| 419 | #define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF) |
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| 420 | #define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK |
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| 421 | |
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| 422 | #define GT_SDRAM_CFG_RMW_SHF 15 |
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| 423 | #define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF) |
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| 424 | #define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK |
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| 425 | |
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| 426 | #define GT_SDRAM_CFG_NONSTAGREF_SHF 16 |
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| 427 | #define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF) |
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| 428 | #define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK |
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| 429 | |
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| 430 | #define GT_SDRAM_CFG_DUPCNTL_SHF 19 |
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| 431 | #define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF) |
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| 432 | #define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK |
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| 433 | |
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| 434 | #define GT_SDRAM_CFG_DUPBA_SHF 20 |
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| 435 | #define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF) |
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| 436 | #define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK |
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| 437 | |
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| 438 | #define GT_SDRAM_CFG_DUPEOT0_SHF 21 |
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| 439 | #define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF) |
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| 440 | #define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK |
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| 441 | |
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| 442 | #define GT_SDRAM_CFG_DUPEOT1_SHF 22 |
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| 443 | #define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF) |
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| 444 | #define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK |
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| 445 | |
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| 446 | #define GT_SDRAM_OPMODE_OP_SHF 0 |
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| 447 | #define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF) |
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| 448 | #define GT_SDRAM_OPMODE_OP_NORMAL 0 |
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| 449 | #define GT_SDRAM_OPMODE_OP_NOP 1 |
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| 450 | #define GT_SDRAM_OPMODE_OP_PRCHG 2 |
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| 451 | #define GT_SDRAM_OPMODE_OP_MODE 3 |
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| 452 | #define GT_SDRAM_OPMODE_OP_CBR 4 |
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| 453 | |
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| 454 | |
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| 455 | #define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0 |
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| 456 | #define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF) |
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| 457 | #define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK |
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| 458 | |
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| 459 | #define GT_PCI0_BARE_SWSCS32DIS_SHF 1 |
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| 460 | #define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF) |
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| 461 | #define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK |
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| 462 | |
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| 463 | #define GT_PCI0_BARE_SWSCS10DIS_SHF 2 |
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| 464 | #define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF) |
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| 465 | #define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK |
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| 466 | |
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| 467 | #define GT_PCI0_BARE_INTIODIS_SHF 3 |
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| 468 | #define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF) |
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| 469 | #define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK |
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| 470 | |
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| 471 | #define GT_PCI0_BARE_INTMEMDIS_SHF 4 |
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| 472 | #define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF) |
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| 473 | #define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK |
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| 474 | |
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| 475 | #define GT_PCI0_BARE_CS3BOOTDIS_SHF 5 |
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| 476 | #define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF) |
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| 477 | #define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK |
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| 478 | |
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| 479 | #define GT_PCI0_BARE_CS20DIS_SHF 6 |
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| 480 | #define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF) |
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| 481 | #define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK |
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| 482 | |
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| 483 | #define GT_PCI0_BARE_SCS32DIS_SHF 7 |
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| 484 | #define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF) |
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| 485 | #define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK |
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| 486 | |
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| 487 | #define GT_PCI0_BARE_SCS10DIS_SHF 8 |
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| 488 | #define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF) |
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| 489 | #define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK |
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| 490 | |
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| 491 | |
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| 492 | #define GT_INTRCAUSE_MASABORT0_SHF 18 |
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| 493 | #define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF) |
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| 494 | #define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK |
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| 495 | |
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| 496 | #define GT_INTRCAUSE_TARABORT0_SHF 19 |
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| 497 | #define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF) |
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| 498 | #define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK |
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| 499 | |
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| 500 | |
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| 501 | #define GT_PCI0_CFGADDR_REGNUM_SHF 2 |
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| 502 | #define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF) |
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| 503 | #define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8 |
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| 504 | #define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
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| 505 | #define GT_PCI0_CFGADDR_DEVNUM_SHF 11 |
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| 506 | #define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF) |
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| 507 | #define GT_PCI0_CFGADDR_BUSNUM_SHF 16 |
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| 508 | #define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF) |
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| 509 | #define GT_PCI0_CFGADDR_CONFIGEN_SHF 31 |
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| 510 | #define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF) |
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| 511 | #define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK |
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| 512 | |
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| 513 | #define GT_PCI0_CMD_MBYTESWAP_SHF 0 |
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| 514 | #define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF) |
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| 515 | #define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK |
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| 516 | #define GT_PCI0_CMD_MWORDSWAP_SHF 10 |
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| 517 | #define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF) |
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| 518 | #define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK |
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| 519 | #define GT_PCI0_CMD_SBYTESWAP_SHF 16 |
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| 520 | #define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF) |
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| 521 | #define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK |
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| 522 | #define GT_PCI0_CMD_SWORDSWAP_SHF 11 |
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| 523 | #define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF) |
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| 524 | #define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK |
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| 525 | |
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| 526 | /* |
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| 527 | * Misc |
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| 528 | */ |
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| 529 | #define GT_DEF_PCI0_IO_BASE 0x10000000UL |
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| 530 | #define GT_DEF_PCI0_IO_SIZE 0x02000000UL |
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| 531 | #define GT_DEF_PCI0_MEM0_BASE 0x12000000UL |
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| 532 | #define GT_DEF_PCI0_MEM0_SIZE 0x02000000UL |
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| 533 | #define GT_DEF_BASE 0x14000000UL |
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| 534 | |
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| 535 | #define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */ |
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| 536 | #define GT_LATTIM_MIN 6 /* Minimum lat */ |
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| 537 | |
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| 538 | /* |
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| 539 | * The gt64120_dep.h file must define the following macros |
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| 540 | * |
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| 541 | * GT_READ(ofs, data_pointer) |
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| 542 | * GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit |
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| 543 | * |
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| 544 | * TIMER - gt64120 timer irq, temporary solution until |
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| 545 | * full gt64120 cascade interrupt support is in place |
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| 546 | */ |
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| 547 | |
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| 548 | #include <mach-gt64120.h> |
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| 549 | |
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| 550 | /* |
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| 551 | * Because of an error/peculiarity in the Galileo chip, we need to swap the |
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| 552 | * bytes when running bigendian. We also provide non-swapping versions. |
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| 553 | */ |
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| 554 | #define __GT_READ(ofs) \ |
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| 555 | (*(volatile __u32 *)(GT64120_BASE+(ofs))) |
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| 556 | #define __GT_WRITE(ofs, data) \ |
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| 557 | do { *(volatile __u32 *)(GT64120_BASE+(ofs)) = (data); } while (0) |
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| 558 | #define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs)) |
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| 559 | #define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data)) |
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| 560 | |
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| 561 | #endif /* _ASM_GT64120_H */ |
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