| 1 | /* $Revision: 1.5 $$Date: 2005-03-25 19:09:14 +0100 (Fri, 25 Mar 2005) $ |
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| 2 | * linux/include/linux/cyclades.h |
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| 3 | * |
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| 4 | * This file was initially written by |
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| 5 | * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by |
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| 6 | * Ivan Passos <ivan@cyclades.com>. |
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| 7 | * |
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| 8 | * This file contains the general definitions for the cyclades.c driver |
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| 9 | *$Log: cyclades.h,v $ |
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| 10 | *Revision 1.5 2004/10/24 16:29:31 mmazur |
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| 11 | *- remove __force and __iomem |
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| 12 | * |
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| 13 | *Revision 1.4 2004/10/22 15:56:17 mmazur |
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| 14 | *- 2.6.9 update |
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| 15 | * |
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| 16 | *Revision 1.3 2004/03/27 16:03:40 mmazur |
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| 17 | *- up to 2.6.4 |
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| 18 | * |
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| 19 | *Revision 1.2 2004/01/01 18:23:40 mmazur |
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| 20 | *- Total Infor^H^H^H^H^HKernel Block Removal part 1 |
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| 21 | *- after finishing this I will make a script to test each and every header |
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| 22 | * for getting parsed correctly by a C compiler |
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| 23 | * |
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| 24 | *Revision 1.1.1.1 2003/12/15 18:46:58 mmazur |
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| 25 | *Initial from debian |
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| 26 | * |
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| 27 | *Revision 3.1 2000/04/19 18:52:52 ivan |
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| 28 | *converted address fields to unsigned long and added fields for physical |
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| 29 | *addresses on cyclades_card structure; |
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| 30 | * |
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| 31 | *Revision 3.0 1998/11/02 14:20:59 ivan |
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| 32 | *added nports field on cyclades_card structure; |
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| 33 | * |
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| 34 | *Revision 2.5 1998/08/03 16:57:01 ivan |
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| 35 | *added cyclades_idle_stats structure; |
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| 36 | * |
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| 37 | *Revision 2.4 1998/06/01 12:09:53 ivan |
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| 38 | *removed closing_wait2 from cyclades_port structure; |
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| 39 | * |
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| 40 | *Revision 2.3 1998/03/16 18:01:12 ivan |
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| 41 | *changes in the cyclades_port structure to get it closer to the |
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| 42 | *standard serial port structure; |
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| 43 | *added constants for new ioctls; |
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| 44 | * |
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| 45 | *Revision 2.2 1998/02/17 16:50:00 ivan |
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| 46 | *changes in the cyclades_port structure (addition of shutdown_wait and |
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| 47 | *chip_rev variables); |
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| 48 | *added constants for new ioctls and for CD1400 rev. numbers. |
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| 49 | * |
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| 50 | *Revision 2.1 1997/10/24 16:03:00 ivan |
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| 51 | *added rflow (which allows enabling the CD1400 special flow control |
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| 52 | *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to |
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| 53 | *cyclades_port structure; |
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| 54 | *added Alpha support |
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| 55 | * |
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| 56 | *Revision 2.0 1997/06/30 10:30:00 ivan |
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| 57 | *added some new doorbell command constants related to IOCTLW and |
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| 58 | *UART error signaling |
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| 59 | * |
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| 60 | *Revision 1.8 1997/06/03 15:30:00 ivan |
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| 61 | *added constant ZFIRM_HLT |
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| 62 | *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin) |
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| 63 | * |
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| 64 | *Revision 1.7 1997/03/26 10:30:00 daniel |
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| 65 | *new entries at the end of cyclades_port struct to reallocate |
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| 66 | *variables illegally allocated within card memory. |
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| 67 | * |
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| 68 | *Revision 1.6 1996/09/09 18:35:30 bentson |
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| 69 | *fold in changes for Cyclom-Z -- including structures for |
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| 70 | *communicating with board as well modest changes to original |
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| 71 | *structures to support new features. |
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| 72 | * |
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| 73 | *Revision 1.5 1995/11/13 21:13:31 bentson |
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| 74 | *changes suggested by Michael Chastain <mec@duracef.shout.net> |
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| 75 | *to support use of this file in non-kernel applications |
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| 76 | * |
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| 77 | * |
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| 78 | */ |
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| 79 | |
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| 80 | #ifndef _LINUX_CYCLADES_H |
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| 81 | #define _LINUX_CYCLADES_H |
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| 82 | |
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| 83 | struct cyclades_monitor { |
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| 84 | unsigned long int_count; |
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| 85 | unsigned long char_count; |
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| 86 | unsigned long char_max; |
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| 87 | unsigned long char_last; |
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| 88 | }; |
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| 89 | |
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| 90 | /* |
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| 91 | * These stats all reflect activity since the device was last initialized. |
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| 92 | * (i.e., since the port was opened with no other processes already having it |
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| 93 | * open) |
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| 94 | */ |
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| 95 | struct cyclades_idle_stats { |
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| 96 | time_t in_use; /* Time device has been in use (secs) */ |
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| 97 | time_t recv_idle; /* Time since last char received (secs) */ |
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| 98 | time_t xmit_idle; /* Time since last char transmitted (secs) */ |
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| 99 | unsigned long recv_bytes; /* Bytes received */ |
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| 100 | unsigned long xmit_bytes; /* Bytes transmitted */ |
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| 101 | unsigned long overruns; /* Input overruns */ |
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| 102 | unsigned long frame_errs; /* Input framing errors */ |
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| 103 | unsigned long parity_errs; /* Input parity errors */ |
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| 104 | }; |
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| 105 | |
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| 106 | #define CYCLADES_MAGIC 0x4359 |
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| 107 | |
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| 108 | #define CYGETMON 0x435901 |
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| 109 | #define CYGETTHRESH 0x435902 |
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| 110 | #define CYSETTHRESH 0x435903 |
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| 111 | #define CYGETDEFTHRESH 0x435904 |
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| 112 | #define CYSETDEFTHRESH 0x435905 |
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| 113 | #define CYGETTIMEOUT 0x435906 |
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| 114 | #define CYSETTIMEOUT 0x435907 |
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| 115 | #define CYGETDEFTIMEOUT 0x435908 |
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| 116 | #define CYSETDEFTIMEOUT 0x435909 |
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| 117 | #define CYSETRFLOW 0x43590a |
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| 118 | #define CYGETRFLOW 0x43590b |
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| 119 | #define CYSETRTSDTR_INV 0x43590c |
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| 120 | #define CYGETRTSDTR_INV 0x43590d |
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| 121 | #define CYZSETPOLLCYCLE 0x43590e |
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| 122 | #define CYZGETPOLLCYCLE 0x43590f |
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| 123 | #define CYGETCD1400VER 0x435910 |
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| 124 | #define CYGETCARDINFO 0x435911 |
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| 125 | #define CYSETWAIT 0x435912 |
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| 126 | #define CYGETWAIT 0x435913 |
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| 127 | |
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| 128 | /*************** CYCLOM-Z ADDITIONS ***************/ |
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| 129 | |
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| 130 | #define CZIOC ('M' << 8) |
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| 131 | #define CZ_NBOARDS (CZIOC|0xfa) |
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| 132 | #define CZ_BOOT_START (CZIOC|0xfb) |
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| 133 | #define CZ_BOOT_DATA (CZIOC|0xfc) |
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| 134 | #define CZ_BOOT_END (CZIOC|0xfd) |
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| 135 | #define CZ_TEST (CZIOC|0xfe) |
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| 136 | |
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| 137 | #define CZ_DEF_POLL (HZ/25) |
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| 138 | |
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| 139 | #define MAX_BOARD 4 /* Max number of boards */ |
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| 140 | #define MAX_DEV 256 /* Max number of ports total */ |
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| 141 | #define CYZ_MAX_SPEED 921600 |
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| 142 | |
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| 143 | #define CYZ_FIFO_SIZE 16 |
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| 144 | |
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| 145 | #define CYZ_BOOT_NWORDS 0x100 |
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| 146 | struct CYZ_BOOT_CTRL { |
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| 147 | unsigned short nboard; |
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| 148 | int status[MAX_BOARD]; |
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| 149 | int nchannel[MAX_BOARD]; |
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| 150 | int fw_rev[MAX_BOARD]; |
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| 151 | unsigned long offset; |
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| 152 | unsigned long data[CYZ_BOOT_NWORDS]; |
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| 153 | }; |
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| 154 | |
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| 155 | |
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| 156 | #ifndef DP_WINDOW_SIZE |
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| 157 | /* #include "cyclomz.h" */ |
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| 158 | /****************** ****************** *******************/ |
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| 159 | /* |
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| 160 | * The data types defined below are used in all ZFIRM interface |
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| 161 | * data structures. They accomodate differences between HW |
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| 162 | * architectures and compilers. |
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| 163 | */ |
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| 164 | |
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| 165 | #if defined(__alpha__) |
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| 166 | typedef unsigned long ucdouble; /* 64 bits, unsigned */ |
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| 167 | typedef unsigned int uclong; /* 32 bits, unsigned */ |
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| 168 | #else |
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| 169 | typedef unsigned long uclong; /* 32 bits, unsigned */ |
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| 170 | #endif |
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| 171 | typedef unsigned short ucshort; /* 16 bits, unsigned */ |
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| 172 | typedef unsigned char ucchar; /* 8 bits, unsigned */ |
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| 173 | |
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| 174 | /* |
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| 175 | * Memory Window Sizes |
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| 176 | */ |
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| 177 | |
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| 178 | #define DP_WINDOW_SIZE (0x00080000) /* window size 512 Kb */ |
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| 179 | #define ZE_DP_WINDOW_SIZE (0x00100000) /* window size 1 Mb (Ze and |
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| 180 | 8Zo V.2 */ |
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| 181 | #define CTRL_WINDOW_SIZE (0x00000080) /* runtime regs 128 bytes */ |
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| 182 | |
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| 183 | /* |
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| 184 | * CUSTOM_REG - Cyclom-Z/PCI Custom Registers Set. The driver |
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| 185 | * normally will access only interested on the fpga_id, fpga_version, |
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| 186 | * start_cpu and stop_cpu. |
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| 187 | */ |
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| 188 | |
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| 189 | struct CUSTOM_REG { |
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| 190 | uclong fpga_id; /* FPGA Identification Register */ |
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| 191 | uclong fpga_version; /* FPGA Version Number Register */ |
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| 192 | uclong cpu_start; /* CPU start Register (write) */ |
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| 193 | uclong cpu_stop; /* CPU stop Register (write) */ |
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| 194 | uclong misc_reg; /* Miscelaneous Register */ |
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| 195 | uclong idt_mode; /* IDT mode Register */ |
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| 196 | uclong uart_irq_status; /* UART IRQ status Register */ |
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| 197 | uclong clear_timer0_irq; /* Clear timer interrupt Register */ |
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| 198 | uclong clear_timer1_irq; /* Clear timer interrupt Register */ |
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| 199 | uclong clear_timer2_irq; /* Clear timer interrupt Register */ |
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| 200 | uclong test_register; /* Test Register */ |
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| 201 | uclong test_count; /* Test Count Register */ |
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| 202 | uclong timer_select; /* Timer select register */ |
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| 203 | uclong pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */ |
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| 204 | uclong ram_wait_state; /* RAM wait-state Register */ |
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| 205 | uclong uart_wait_state; /* UART wait-state Register */ |
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| 206 | uclong timer_wait_state; /* timer wait-state Register */ |
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| 207 | uclong ack_wait_state; /* ACK wait State Register */ |
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| 208 | }; |
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| 209 | |
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| 210 | /* |
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| 211 | * RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime |
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| 212 | * registers. This structure can be used to access the 9060 registers |
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| 213 | * (memory mapped). |
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| 214 | */ |
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| 215 | |
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| 216 | struct RUNTIME_9060 { |
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| 217 | uclong loc_addr_range; /* 00h - Local Address Range */ |
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| 218 | uclong loc_addr_base; /* 04h - Local Address Base */ |
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| 219 | uclong loc_arbitr; /* 08h - Local Arbitration */ |
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| 220 | uclong endian_descr; /* 0Ch - Big/Little Endian Descriptor */ |
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| 221 | uclong loc_rom_range; /* 10h - Local ROM Range */ |
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| 222 | uclong loc_rom_base; /* 14h - Local ROM Base */ |
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| 223 | uclong loc_bus_descr; /* 18h - Local Bus descriptor */ |
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| 224 | uclong loc_range_mst; /* 1Ch - Local Range for Master to PCI */ |
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| 225 | uclong loc_base_mst; /* 20h - Local Base for Master PCI */ |
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| 226 | uclong loc_range_io; /* 24h - Local Range for Master IO */ |
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| 227 | uclong pci_base_mst; /* 28h - PCI Base for Master PCI */ |
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| 228 | uclong pci_conf_io; /* 2Ch - PCI configuration for Master IO */ |
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| 229 | uclong filler1; /* 30h */ |
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| 230 | uclong filler2; /* 34h */ |
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| 231 | uclong filler3; /* 38h */ |
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| 232 | uclong filler4; /* 3Ch */ |
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| 233 | uclong mail_box_0; /* 40h - Mail Box 0 */ |
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| 234 | uclong mail_box_1; /* 44h - Mail Box 1 */ |
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| 235 | uclong mail_box_2; /* 48h - Mail Box 2 */ |
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| 236 | uclong mail_box_3; /* 4Ch - Mail Box 3 */ |
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| 237 | uclong filler5; /* 50h */ |
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| 238 | uclong filler6; /* 54h */ |
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| 239 | uclong filler7; /* 58h */ |
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| 240 | uclong filler8; /* 5Ch */ |
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| 241 | uclong pci_doorbell; /* 60h - PCI to Local Doorbell */ |
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| 242 | uclong loc_doorbell; /* 64h - Local to PCI Doorbell */ |
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| 243 | uclong intr_ctrl_stat; /* 68h - Interrupt Control/Status */ |
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| 244 | uclong init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */ |
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| 245 | }; |
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| 246 | |
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| 247 | /* Values for the Local Base Address re-map register */ |
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| 248 | |
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| 249 | #define WIN_RAM 0x00000001L /* set the sliding window to RAM */ |
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| 250 | #define WIN_CREG 0x14000001L /* set the window to custom Registers */ |
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| 251 | |
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| 252 | /* Values timer select registers */ |
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| 253 | |
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| 254 | #define TIMER_BY_1M 0x00 /* clock divided by 1M */ |
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| 255 | #define TIMER_BY_256K 0x01 /* clock divided by 256k */ |
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| 256 | #define TIMER_BY_128K 0x02 /* clock divided by 128k */ |
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| 257 | #define TIMER_BY_32K 0x03 /* clock divided by 32k */ |
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| 258 | |
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| 259 | /****************** ****************** *******************/ |
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| 260 | #endif |
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| 261 | |
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| 262 | #ifndef ZFIRM_ID |
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| 263 | /* #include "zfwint.h" */ |
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| 264 | /****************** ****************** *******************/ |
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| 265 | /* |
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| 266 | * This file contains the definitions for interfacing with the |
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| 267 | * Cyclom-Z ZFIRM Firmware. |
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| 268 | */ |
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| 269 | |
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| 270 | /* General Constant definitions */ |
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| 271 | |
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| 272 | #define MAX_CHAN 64 /* max number of channels per board */ |
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| 273 | |
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| 274 | /* firmware id structure (set after boot) */ |
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| 275 | |
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| 276 | #define ID_ADDRESS 0x00000180L /* signature/pointer address */ |
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| 277 | #define ZFIRM_ID 0x5557465AL /* ZFIRM/U signature */ |
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| 278 | #define ZFIRM_HLT 0x59505B5CL /* ZFIRM needs external power supply */ |
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| 279 | #define ZFIRM_RST 0x56040674L /* RST signal (due to FW reset) */ |
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| 280 | |
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| 281 | #define ZF_TINACT_DEF 1000 /* default inactivity timeout |
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| 282 | (1000 ms) */ |
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| 283 | #define ZF_TINACT ZF_TINACT_DEF |
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| 284 | |
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| 285 | struct FIRM_ID { |
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| 286 | uclong signature; /* ZFIRM/U signature */ |
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| 287 | uclong zfwctrl_addr; /* pointer to ZFW_CTRL structure */ |
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| 288 | }; |
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| 289 | |
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| 290 | /* Op. System id */ |
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| 291 | |
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| 292 | #define C_OS_LINUX 0x00000030 /* generic Linux system */ |
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| 293 | |
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| 294 | /* channel op_mode */ |
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| 295 | |
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| 296 | #define C_CH_DISABLE 0x00000000 /* channel is disabled */ |
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| 297 | #define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */ |
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| 298 | #define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */ |
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| 299 | #define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */ |
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| 300 | #define C_CH_LOOPBACK 0x00000004 /* Loopback mode */ |
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| 301 | |
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| 302 | /* comm_parity - parity */ |
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| 303 | |
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| 304 | #define C_PR_NONE 0x00000000 /* None */ |
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| 305 | #define C_PR_ODD 0x00000001 /* Odd */ |
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| 306 | #define C_PR_EVEN 0x00000002 /* Even */ |
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| 307 | #define C_PR_MARK 0x00000004 /* Mark */ |
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| 308 | #define C_PR_SPACE 0x00000008 /* Space */ |
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| 309 | #define C_PR_PARITY 0x000000ff |
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| 310 | |
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| 311 | #define C_PR_DISCARD 0x00000100 /* discard char with frame/par error */ |
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| 312 | #define C_PR_IGNORE 0x00000200 /* ignore frame/par error */ |
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| 313 | |
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| 314 | /* comm_data_l - data length and stop bits */ |
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| 315 | |
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| 316 | #define C_DL_CS5 0x00000001 |
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| 317 | #define C_DL_CS6 0x00000002 |
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| 318 | #define C_DL_CS7 0x00000004 |
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| 319 | #define C_DL_CS8 0x00000008 |
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| 320 | #define C_DL_CS 0x0000000f |
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| 321 | #define C_DL_1STOP 0x00000010 |
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| 322 | #define C_DL_15STOP 0x00000020 |
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| 323 | #define C_DL_2STOP 0x00000040 |
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| 324 | #define C_DL_STOP 0x000000f0 |
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| 325 | |
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| 326 | /* interrupt enabling/status */ |
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| 327 | |
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| 328 | #define C_IN_DISABLE 0x00000000 /* zero, disable interrupts */ |
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| 329 | #define C_IN_TXBEMPTY 0x00000001 /* tx buffer empty */ |
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| 330 | #define C_IN_TXLOWWM 0x00000002 /* tx buffer below LWM */ |
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| 331 | #define C_IN_RXHIWM 0x00000010 /* rx buffer above HWM */ |
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| 332 | #define C_IN_RXNNDT 0x00000020 /* rx no new data timeout */ |
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| 333 | #define C_IN_MDCD 0x00000100 /* modem DCD change */ |
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| 334 | #define C_IN_MDSR 0x00000200 /* modem DSR change */ |
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| 335 | #define C_IN_MRI 0x00000400 /* modem RI change */ |
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| 336 | #define C_IN_MCTS 0x00000800 /* modem CTS change */ |
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| 337 | #define C_IN_RXBRK 0x00001000 /* Break received */ |
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| 338 | #define C_IN_PR_ERROR 0x00002000 /* parity error */ |
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| 339 | #define C_IN_FR_ERROR 0x00004000 /* frame error */ |
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| 340 | #define C_IN_OVR_ERROR 0x00008000 /* overrun error */ |
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| 341 | #define C_IN_RXOFL 0x00010000 /* RX buffer overflow */ |
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| 342 | #define C_IN_IOCTLW 0x00020000 /* I/O control w/ wait */ |
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| 343 | #define C_IN_MRTS 0x00040000 /* modem RTS drop */ |
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| 344 | #define C_IN_ICHAR 0x00080000 |
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| 345 | |
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| 346 | /* flow control */ |
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| 347 | |
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| 348 | #define C_FL_OXX 0x00000001 /* output Xon/Xoff flow control */ |
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| 349 | #define C_FL_IXX 0x00000002 /* output Xon/Xoff flow control */ |
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| 350 | #define C_FL_OIXANY 0x00000004 /* output Xon/Xoff (any xon) */ |
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| 351 | #define C_FL_SWFLOW 0x0000000f |
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| 352 | |
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| 353 | /* flow status */ |
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| 354 | |
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| 355 | #define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer or UART */ |
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| 356 | #define C_FS_SENDING 0x00000001 /* UART is sending data */ |
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| 357 | #define C_FS_SWFLOW 0x00000002 /* Tx is stopped by received Xoff */ |
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| 358 | |
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| 359 | /* rs_control/rs_status RS-232 signals */ |
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| 360 | |
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| 361 | #define C_RS_PARAM 0x80000000 /* Indicates presence of parameter in |
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| 362 | IOCTLM command */ |
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| 363 | #define C_RS_RTS 0x00000001 /* RTS */ |
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| 364 | #define C_RS_DTR 0x00000004 /* DTR */ |
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| 365 | #define C_RS_DCD 0x00000100 /* CD */ |
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| 366 | #define C_RS_DSR 0x00000200 /* DSR */ |
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| 367 | #define C_RS_RI 0x00000400 /* RI */ |
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| 368 | #define C_RS_CTS 0x00000800 /* CTS */ |
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| 369 | |
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| 370 | /* commands Host <-> Board */ |
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| 371 | |
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| 372 | #define C_CM_RESET 0x01 /* reset/flush buffers */ |
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| 373 | #define C_CM_IOCTL 0x02 /* re-read CH_CTRL */ |
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| 374 | #define C_CM_IOCTLW 0x03 /* re-read CH_CTRL, intr when done */ |
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| 375 | #define C_CM_IOCTLM 0x04 /* RS-232 outputs change */ |
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| 376 | #define C_CM_SENDXOFF 0x10 /* send Xoff */ |
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| 377 | #define C_CM_SENDXON 0x11 /* send Xon */ |
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| 378 | #define C_CM_CLFLOW 0x12 /* Clear flow control (resume) */ |
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| 379 | #define C_CM_SENDBRK 0x41 /* send break */ |
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| 380 | #define C_CM_INTBACK 0x42 /* Interrupt back */ |
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| 381 | #define C_CM_SET_BREAK 0x43 /* Tx break on */ |
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| 382 | #define C_CM_CLR_BREAK 0x44 /* Tx break off */ |
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| 383 | #define C_CM_CMD_DONE 0x45 /* Previous command done */ |
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| 384 | #define C_CM_INTBACK2 0x46 /* Alternate Interrupt back */ |
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| 385 | #define C_CM_TINACT 0x51 /* set inactivity detection */ |
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| 386 | #define C_CM_IRQ_ENBL 0x52 /* enable generation of interrupts */ |
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| 387 | #define C_CM_IRQ_DSBL 0x53 /* disable generation of interrupts */ |
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| 388 | #define C_CM_ACK_ENBL 0x54 /* enable acknowledged interrupt mode */ |
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| 389 | #define C_CM_ACK_DSBL 0x55 /* disable acknowledged intr mode */ |
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| 390 | #define C_CM_FLUSH_RX 0x56 /* flushes Rx buffer */ |
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| 391 | #define C_CM_FLUSH_TX 0x57 /* flushes Tx buffer */ |
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| 392 | #define C_CM_Q_ENABLE 0x58 /* enables queue access from the |
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| 393 | driver */ |
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| 394 | #define C_CM_Q_DISABLE 0x59 /* disables queue access from the |
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| 395 | driver */ |
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| 396 | |
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| 397 | #define C_CM_TXBEMPTY 0x60 /* Tx buffer is empty */ |
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| 398 | #define C_CM_TXLOWWM 0x61 /* Tx buffer low water mark */ |
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| 399 | #define C_CM_RXHIWM 0x62 /* Rx buffer high water mark */ |
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| 400 | #define C_CM_RXNNDT 0x63 /* rx no new data timeout */ |
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| 401 | #define C_CM_TXFEMPTY 0x64 |
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| 402 | #define C_CM_ICHAR 0x65 |
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| 403 | #define C_CM_MDCD 0x70 /* modem DCD change */ |
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| 404 | #define C_CM_MDSR 0x71 /* modem DSR change */ |
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| 405 | #define C_CM_MRI 0x72 /* modem RI change */ |
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| 406 | #define C_CM_MCTS 0x73 /* modem CTS change */ |
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| 407 | #define C_CM_MRTS 0x74 /* modem RTS drop */ |
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| 408 | #define C_CM_RXBRK 0x84 /* Break received */ |
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| 409 | #define C_CM_PR_ERROR 0x85 /* Parity error */ |
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| 410 | #define C_CM_FR_ERROR 0x86 /* Frame error */ |
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| 411 | #define C_CM_OVR_ERROR 0x87 /* Overrun error */ |
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| 412 | #define C_CM_RXOFL 0x88 /* RX buffer overflow */ |
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| 413 | #define C_CM_CMDERROR 0x90 /* command error */ |
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| 414 | #define C_CM_FATAL 0x91 /* fatal error */ |
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| 415 | #define C_CM_HW_RESET 0x92 /* reset board */ |
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| 416 | |
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| 417 | /* |
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| 418 | * CH_CTRL - This per port structure contains all parameters |
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| 419 | * that control an specific port. It can be seen as the |
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| 420 | * configuration registers of a "super-serial-controller". |
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| 421 | */ |
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| 422 | |
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| 423 | struct CH_CTRL { |
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| 424 | uclong op_mode; /* operation mode */ |
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| 425 | uclong intr_enable; /* interrupt masking */ |
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| 426 | uclong sw_flow; /* SW flow control */ |
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| 427 | uclong flow_status; /* output flow status */ |
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| 428 | uclong comm_baud; /* baud rate - numerically specified */ |
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| 429 | uclong comm_parity; /* parity */ |
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| 430 | uclong comm_data_l; /* data length/stop */ |
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| 431 | uclong comm_flags; /* other flags */ |
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| 432 | uclong hw_flow; /* HW flow control */ |
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| 433 | uclong rs_control; /* RS-232 outputs */ |
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| 434 | uclong rs_status; /* RS-232 inputs */ |
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| 435 | uclong flow_xon; /* xon char */ |
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| 436 | uclong flow_xoff; /* xoff char */ |
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| 437 | uclong hw_overflow; /* hw overflow counter */ |
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| 438 | uclong sw_overflow; /* sw overflow counter */ |
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| 439 | uclong comm_error; /* frame/parity error counter */ |
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| 440 | uclong ichar; |
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| 441 | uclong filler[7]; |
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| 442 | }; |
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| 443 | |
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| 444 | |
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| 445 | /* |
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| 446 | * BUF_CTRL - This per channel structure contains |
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| 447 | * all Tx and Rx buffer control for a given channel. |
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| 448 | */ |
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| 449 | |
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| 450 | struct BUF_CTRL { |
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| 451 | uclong flag_dma; /* buffers are in Host memory */ |
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| 452 | uclong tx_bufaddr; /* address of the tx buffer */ |
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| 453 | uclong tx_bufsize; /* tx buffer size */ |
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| 454 | uclong tx_threshold; /* tx low water mark */ |
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| 455 | uclong tx_get; /* tail index tx buf */ |
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| 456 | uclong tx_put; /* head index tx buf */ |
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| 457 | uclong rx_bufaddr; /* address of the rx buffer */ |
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| 458 | uclong rx_bufsize; /* rx buffer size */ |
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| 459 | uclong rx_threshold; /* rx high water mark */ |
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| 460 | uclong rx_get; /* tail index rx buf */ |
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| 461 | uclong rx_put; /* head index rx buf */ |
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| 462 | uclong filler[5]; /* filler to align structures */ |
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| 463 | }; |
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| 464 | |
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| 465 | /* |
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| 466 | * BOARD_CTRL - This per board structure contains all global |
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| 467 | * control fields related to the board. |
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| 468 | */ |
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| 469 | |
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| 470 | struct BOARD_CTRL { |
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| 471 | |
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| 472 | /* static info provided by the on-board CPU */ |
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| 473 | uclong n_channel; /* number of channels */ |
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| 474 | uclong fw_version; /* firmware version */ |
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| 475 | |
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| 476 | /* static info provided by the driver */ |
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| 477 | uclong op_system; /* op_system id */ |
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| 478 | uclong dr_version; /* driver version */ |
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| 479 | |
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| 480 | /* board control area */ |
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| 481 | uclong inactivity; /* inactivity control */ |
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| 482 | |
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| 483 | /* host to FW commands */ |
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| 484 | uclong hcmd_channel; /* channel number */ |
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| 485 | uclong hcmd_param; /* pointer to parameters */ |
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| 486 | |
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| 487 | /* FW to Host commands */ |
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| 488 | uclong fwcmd_channel; /* channel number */ |
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| 489 | uclong fwcmd_param; /* pointer to parameters */ |
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| 490 | uclong zf_int_queue_addr; /* offset for INT_QUEUE structure */ |
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| 491 | |
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| 492 | /* filler so the structures are aligned */ |
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| 493 | uclong filler[6]; |
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| 494 | }; |
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| 495 | |
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| 496 | /* Host Interrupt Queue */ |
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| 497 | |
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| 498 | #define QUEUE_SIZE (10*MAX_CHAN) |
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| 499 | |
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| 500 | struct INT_QUEUE { |
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| 501 | unsigned char intr_code[QUEUE_SIZE]; |
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| 502 | unsigned long channel[QUEUE_SIZE]; |
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| 503 | unsigned long param[QUEUE_SIZE]; |
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| 504 | unsigned long put; |
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| 505 | unsigned long get; |
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| 506 | }; |
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| 507 | |
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| 508 | /* |
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| 509 | * ZFW_CTRL - This is the data structure that includes all other |
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| 510 | * data structures used by the Firmware. |
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| 511 | */ |
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| 512 | |
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| 513 | struct ZFW_CTRL { |
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| 514 | struct BOARD_CTRL board_ctrl; |
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| 515 | struct CH_CTRL ch_ctrl[MAX_CHAN]; |
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| 516 | struct BUF_CTRL buf_ctrl[MAX_CHAN]; |
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| 517 | }; |
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| 518 | |
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| 519 | /****************** ****************** *******************/ |
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| 520 | #endif |
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| 521 | |
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| 522 | /* Per card data structure */ |
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| 523 | struct resource; |
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| 524 | struct cyclades_card { |
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| 525 | unsigned long base_phys; |
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| 526 | unsigned long ctl_phys; |
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| 527 | void *base_addr; |
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| 528 | void *ctl_addr; |
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| 529 | int irq; |
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| 530 | int num_chips; /* 0 if card absent, -1 if Z/PCI, else Y */ |
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| 531 | int first_line; /* minor number of first channel on card */ |
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| 532 | int nports; /* Number of ports in the card */ |
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| 533 | int bus_index; /* address shift - 0 for ISA, 1 for PCI */ |
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| 534 | int intr_enabled; /* FW Interrupt flag - 0 disabled, 1 enabled */ |
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| 535 | struct pci_dev *pdev; |
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| 536 | unsigned long filler; |
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| 537 | }; |
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| 538 | |
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| 539 | struct cyclades_chip { |
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| 540 | int filler; |
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| 541 | }; |
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| 542 | |
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| 543 | #endif /* _LINUX_CYCLADES_H */ |
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