// ANALOGIX Company // HDMI_TX Demo Firmware on SST #ifndef _HDMI_TX_Sys_H #define _HDMI_TX_Sys_H #define HDMI_TX_FW_VER 1.01 typedef unsigned char BYTE; typedef unsigned char BIT; typedef unsigned short WORD; extern BYTE timer_slot,misc_reset_needed; extern BYTE bist_switch_value_pc,switch_value; extern BYTE switch_value_sw_backup,switch_value_pc_backup; extern BYTE HDMI_TX_system_state; extern BIT hdmi_tx_srm_checked; extern BIT hdmi_tx_HDCP_enable; extern BYTE FREQ_MCLK; struct Video_Timing { //BYTE number; WORD h_total_length; WORD h_active_length; WORD v_total_length; WORD v_active_length; WORD h_front_porch; WORD h_sync_width; WORD h_back_porch; BYTE v_front_porch; BYTE v_sync_width; BYTE v_back_porch; BYTE h_sync_polarity; BYTE v_sync_polarity; BYTE is_interlaced; BYTE video_mode; }; typedef struct { BYTE is_HDMI; BYTE ycbcr444_supported; BYTE ycbcr422_supported; BYTE supported_1080p_60Hz; BYTE supported_1080p_50Hz; BYTE supported_1080i_60Hz; BYTE supported_1080i_50Hz; BYTE supported_720p_60Hz; BYTE supported_720p_50Hz; BYTE supported_576p_50Hz; BYTE supported_576i_50Hz; BYTE supported_640x480p_60Hz; BYTE supported_720x480p_60Hz; BYTE supported_720x480i_60Hz; BYTE AudioFormat[10];//MAX audio STD block is 10(0x1f / 3) BYTE AudioChannel[10]; BYTE AudioFs[10]; BYTE AudioLength[10]; BYTE SpeakerFormat; BYTE edid_errcode; BYTE RGB30bit; BYTE RGB36bit; BYTE RGB48bit; BYTE DC_Y444; }hdmi_tx_edid_result_4_system; extern hdmi_tx_edid_result_4_system hdmi_tx_edid_result; // 8 type of packets are legal, It is possible to sent 6 types in the same time; // So select 6 types below at most; // avi_infoframe and audio_infoframe have fixxed address; // config other selected types of packet to the rest 4 address with no limits. typedef enum { HDMI_TX_avi_infoframe, HDMI_TX_audio_infoframe, HDMI_TX_spd_infoframe, HDMI_TX_mpeg_infoframe, HDMI_TX_acp_packet, HDMI_TX_isrc1_packet, HDMI_TX_isrc2_packet, HDMI_TX_vendor_infoframe }packet_type; typedef struct { unsigned char type; unsigned char version; unsigned char length; unsigned char pb_byte[28]; }infoframe_struct; typedef struct { BYTE packets_need_config; //which infoframe packet is need updated infoframe_struct avi_info; infoframe_struct audio_info; infoframe_struct spd_info; infoframe_struct mpeg_info; infoframe_struct acp_pkt; infoframe_struct isrc1_pkt; infoframe_struct isrc2_pkt; infoframe_struct vendor_info; } config_packets; /* BYTE i2s_format; Bit(s) Name Type Default Description 7 EXT_VUCP R/W 0x0 Enable indicator of VUCP BITs extraction from input I2S audio stream. 0 = disable; 1 = enable. 6:5 MCLK_PHS_CTRL R/W 0x0 MCLK phase control for audio SPDIF input, which value is depended on the value of MCLK frequency set and not great than it. 4 Reserved 3 SHIFT_CTRL R/W 0x0 WS to SD shift first BIT. 0 = fist BIT shift (Philips Spec); 1 = no shift. 2 DIR_CTRL R/W 0x0 SD data Indian (MSB or LSB first) control. 0 = MSB first; 1 = LSB first. 1 WS_POL R/W 0x0 Word select left/right polarity select. 0 = left polarity when works select is low; 1 = left polarity when word select is high. 0 JUST_CTRL R/W 0x0 SD Justification control. 1 = data is right justified; 0 = data is left justified. */ /* BYTE audio_channel Bit(s) Name Type Default Description 5 AUD_SD3_IN R/W 0x0 Set I2S input channel #3 enable. 0 = disable; 1 = enable. 4 AUD_SD2_IN R/W 0x0 Set I2S input channel #2 enable. 0 = disable; 1 = enable. 3 AUD_SD1_IN R/W 0x0 Set I2S input channel #1 enable. 0 = disable; 1 = enable. 2 AUD_SD0_IN R/W 0x0 Set I2S input channel #0 enable. 0 = disable; 1 = enable. */ /* BYTE i2s_map0 Bit(s) Name Type Default Description 7:6 FIFO3_SEL R/W 0x3 I2S Channel data stream select for audio FIFO 3. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3; 5:4 FIFO2_SEL R/W 0x2 I2S Channel data stream select for audio FIFO 2. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3; 3:2 FIFO1_SEL R/W 0x1 I2S Channel data stream select for audio FIFO 1. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3; 1:0 FIFO0_SEL R/W 0x0 I2S Channel data stream select for audio FIFO 0. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3; BYTE i2s_map1 Bit(s) Name Type Default Description 7 SW3 R/W 0x0 Swap left/right channel on I2S channel 3. 1 = swap; 0 = no swap. 6 SW2 R/W 0x0 Swap left/right channel on I2S channel 2. 1 = swap; 0 = no swap. 5 SW1 R/W 0x0 Swap left/right channel on I2S channel 1. 1 = swap; 0 = no swap. 4 SW0 R/W 0x0 Swap left/right channel on I2S channel 0. 1 = swap; 0 = no swap. 3:1 IN_WORD_LEN R/W 0x5 Input I2S audio word length (corresponding to channel status BITs [35:33]). When IN_WORD_MAX = 0, 001 = 16 BITs; 010 = 18 BITs; 100 = 19 BITs; 101 = 20 BITs; 110 = 17 BITs; when IN_WORD_MAX = 1, 001 = 20 BITs; 010 = 22 BITs; 100 = 23 BITs; 101 = 24 BITs; 110 = 21 BITs. 0 IN_WORD_MAX R/W 0x1 Input I2S audio word length Max (corresponding to channel status BITs 32). 0 = maximal word length is 20 BITs; 1 = maximal word length is 24 BITs. */ /* BYTE Channel_status1 Bit(s) Name Type Default Description 7:6 MODE R/W 0x0 00 = PCM Audio 5:3 PCM_MODE R/W 0x0 000 = 2 audio channels without pre-emphasis; 001 = 2 audio channels with 50/15 usec pre-emphasis 2 SW_CPRGT R/W 0x0 0 = software for which copyright is asserted; 1 = software for which no copyright is asserted 1 NON_PCM R/W 0x0 0 = audio sample word represents linear PCM samples; 1 = audio sample word used for other purposes. 0 PROF_APP R/W 0x0 0 = consumer applications; 1 = professional applications. BYTE Channel_status2 Bit(s) Name Type Default Description 7:0 CAT_CODE R/W 0x0 Category code (corresponding to channel status BITs [15:8]) BYTE Channel_status3 Bit(s) Name Type Default Description 7:4 CH_NUM R/W 0x0 Channel number (corresponding to channel status BITs [23:20]) 3:0 SOURCE_NUM R/W 0x0 Source number (corresponding to channel status BITs [19:16]) BYTE Channel_status4 Bit(s) Name Type Default Description 7:6 CHNL_BIT1 R/W 0x0 corresponding to channels status BITs [31:30] 5:4 CLK_ACCUR R/W 0x0 Clock accuracy (corresponding to channels status BITs [29:28]). These two BITs define the sampling frequency tolerance. The BITs are set in the transmitter. 3:0 FS_FREQ R/W 0x0 Sampling clock frequency (corresponding to channel status BITs [27:24]). 0000 = 44.1 KHz; 0010 = 48 KHz; 0011 = 32 KHz; 1000 = 88.2 KHz; 1010 = 96 KHz; 176.4 KHz; 1110 = 192 KHz; others = reserved. BYTE Channel_status5 Bit(s) Name Type Default Description 7:4 CHNL_BIT2 R/W 0x0 corresponding to channels status BITs [39:36] 3:1 WORD_LENGTH R/W 0x5 Audio word length (corresponding to channel status BITs [35:33]). When WORD_MAX = 0, 001 = 16 BITs; 010 = 18 BITs; 100 = 19 BITs; 101 = 20 BITs; 110 = 17 BITs; when WORD_MAX = 1, 001 = 20 BITs; 010 = 22 BITs; 100 = 23 BITs; 101 = 24 BITs; 110 = 21 BITs. 0 WORD_MAX R/W 0x1 Audio word length Max (corresponding to channel status BITs 32). 0 = maximal word length is 20 BITs; 1 = maximal word length is 24 BITs. */ typedef struct { BYTE audio_channel; BYTE i2s_format; BYTE i2s_swap; BYTE Channel_status1; BYTE Channel_status2; BYTE Channel_status3; BYTE Channel_status4; BYTE Channel_status5; } i2s_config_struct; /* BYTE FS_FREQ; 7:4 FS_FREQ R 0x0 Sampling clock frequency (corresponding to channel status BITs [27:24]). 0000 = 44.1 KHz; 0010 = 48 KHz; 0011 = 32 KHz; 1000 = 88.2 KHz; 1010 = 96 KHz; 176.4 KHz; 1110 = 192 KHz; others = reserved. */ typedef struct { BYTE one_BIT_ctrl; } super_audio_config_struct; typedef struct { BYTE audio_type; // audio type // #define HDMI_TX_i2s_input 0x01 // #define HDMI_TX_spdif_input 0x02 // #define HDMI_TX_super_audio_input 0x04 BYTE down_sample; // 0x72:0x50 // 0x00: 00 no down sample // 0x20: 01 2 to 1 down sample // 0x60: 11 4 to 1 down sample // 0x40: 10 reserved i2s_config_struct i2s_config; super_audio_config_struct super_audio_config; } audio_config_struct; /*added by gerard.zhu*/ /*DDC type*/ typedef enum { DDC_Hdcp, DDC_Edid }Anx8560_DDC_Type; /*Read DDC status type*/ typedef enum { report, Judge }Anx8560_DDC_Status_Check_Type; /*Define DDC address struction*/ typedef struct { BYTE dev_addr; BYTE sgmt_addr; BYTE offset_addr; }Anx8560_DDC_Addr; /*DDC status bit*/ #define DDC_Error_bit 0x07 #define DDC_Occup_bit 0x06 #define DDC_Fifo_Full_bit 0x05 #define DDC_Fifo_Empt_bit 0x04 #define DDC_No_Ack_bit 0x03 #define DDC_Fifo_Rd_bit 0x02 #define DDC_Fifo_Wr_bit 0x01 #define DDC_Progress_bit 0x00 #define YCbCr422 0x20 #define null 0 #define source_ratio 0x08 /*DDC Command*/ #define Abort_Current_Operation 0x00 #define Sequential_Byte_Read 0x01 #define Sequential_Byte_Write 0x02 #define Implicit_Offset_Address_Read 0x3 #define Enhanced_DDC_Sequenital_Read 0x04 #define Clear_DDC_Fifo 0x05 #define I2c_reset 0x06 /*DDC result*/ #define DDC_NO_Err 0x00 #define DDC_Status_Err 0x01 #define DDC_Data_Addr_Err 0x02 #define DDC_Length_Err 0x03 /*checksum result*/ #define Edid_Checksum_No_Err 0x00 #define Edid_Checksum_Err 0x01 /*HDCP device base address*/ #define HDCP_Dev_Addr 0x74 /*HDCP Bksv offset*/ #define HDCP_Bksv_Offset 0x00 /*HDCP Bcaps offset*/ #define HDCP_Bcaps_Offset 0x40 /*HDCP Bstatus offset*/ #define HDCP_Bstatus_offset 0x41 /*HDCP KSV Fifo offset */ #define HDCP_Ksv_Fifo_Offset 0x43 /*HDCP bksv data nums*/ #define Bksv_Data_Nums 5 /*HDCP ksvs data number by defult*/ #define ksvs_data_nums 50 /*DDC Max bytes*/ #define DDC_Max_Length 1024 /*DDC fifo depth*/ #define DDC_Fifo_Depth 16 /*DDC read delay ms*/ #define DDC_Read_Delay 3 /*DDC Write delay ms*/ #define DDC_Write_Delay 3 /*end*/ extern BIT hdmi_tx_parse_edid_done; extern BIT hdmi_tx_system_config_video_done,hdmi_tx_system_config_audio_done,hdmi_tx_system_config_gamut_data_done; extern BYTE hdmi_tx_video_format_config,hdmi_tx_video_timing_id; extern BIT hdmi_tx_new_csc,hdmi_tx_new_vid_id,hdmi_tx_new_HW_interface; extern BIT hdmi_tx_ddr_edge; extern BYTE hdmi_tx_in_pix_rpt_bkp,hdmi_tx_tx_pix_rpt_bkp; extern BYTE hdmi_tx_in_pix_rpt,hdmi_tx_tx_pix_rpt; extern BIT hdmi_tx_pix_rpt_set_by_sys; extern BYTE hdmi_tx_RGBorYCbCr; extern audio_config_struct s_hdmi_tx_audio_config; extern config_packets s_hdmi_tx_packet_config; extern BIT hdmi_tx_app_hold_video_config,hdmi_tx_app_hold_audio_config; extern BIT hdmi_tx_shutdown; //********************** BIST Enable*********************************** #define BIST_MODE_USED 1 #define HDMI_RX_USED 0 #define HDMI_TX_CLK_SOURCE 1 #define BIST_EN g_BIST_OnOff #define BIST_MODE3 ((g_BIST_Resolution >> 3) & 0x01) #define BIST_MODE2 ((g_BIST_Resolution >> 2) & 0x01) #define BIST_MODE1 ((g_BIST_Resolution >> 1) & 0x01) #define BIST_MODE0 ((g_BIST_Resolution >> 0) & 0x01) #define HDMI_TX_USE_NATIVE_CODE 1 #define rpt_auto_setting 0 #define rpt_manual_setting 1 #define ddr_falling_edge 1 #define ddr_rising_edge 0 #define input_pixel_clk_1x_repeatition 0x00 #define input_pixel_clk_2x_repeatition 0x01 #define input_pixel_clk_4x_repeatition 0x03 //***********************Video Config*********************************** #define hdmi_tx_RGB_YCrCb444_SepSync 0 #define hdmi_tx_YCrCb422_SepSync 1 #define hdmi_tx_YCrCb422_EmbSync 2 #define hdmi_tx_YCMux422_SepSync_Mode1 3 #define hdmi_tx_YCMux422_SepSync_Mode2 4 #define hdmi_tx_YCMux422_EmbSync_Mode1 5 #define hdmi_tx_YCMux422_EmbSync_Mode2 6 #define hdmi_tx_YCMux422_EmbSync_Mode3 12 #define hdmi_tx_YCMux422_SepSync_Mode3 11 #define hdmi_tx_RGB_YCrCb444_DDR_SepSync 7 #define hdmi_tx_RGB_YCrCb444_DDR_EmbSync 8 #define hdmi_tx_RGB_YCrCb444_SepSync_No_DE 9 #define hdmi_tx_YCrCb422_SepSync_No_DE 10 #define hdmi_tx_Progressive 0 #define hdmi_tx_Interlace 0x08 #define hdmi_tx_Neg_Hsync_pol 0x20 #define hdmi_tx_Pos_Hsync_pol 0 #define hdmi_tx_Neg_Vsync_pol 0x40 #define hdmi_tx_Pos_Vsync_pol 0 //Use for digital video output fomat #define RGB444 0x00 #define RGB444_CLK48B 0x80 #define YCbCr444 0x01 #define YCbCr444_CLK48B 0x81 #define YCbCR422 0x03 #define YCbCr422_656 0x0b #define YCbCr422_YCMUX 0x07 #define YCbCr422_656_YCMUX 0x0f #define HDMI_TX_RGB 0x00 #define HDMI_TX_YCbCr422 0x01 #define HDMI_TX_YCbCr444 0x02 #define HDMI_TX_CSC_BT709 1 #define HDMI_TX_CSC_BT601 0 #define HDMI_TX_EMBEDED_BLUE_SCREEN_ENABLE 1 #define HDMI_TX_HDCP_FAIL_THRESHOLD 3 #define HDMI_TX_avi_sel 0x01 #define HDMI_TX_audio_sel 0x02 #define HDMI_TX_spd_sel 0x04 #define HDMI_TX_mpeg_sel 0x08 #define HDMI_TX_acp_sel 0x10 #define HDMI_TX_isrc1_sel 0x20 #define HDMI_TX_isrc2_sel 0x40 #define HDMI_TX_vendor_sel 0x80 #define sim // audio type #define HDMI_TX_i2s_input 0x01 #define HDMI_TX_spdif_input 0x02 #define HDMI_TX_super_audio_input 0x04 // freq_mclk #define HDMI_TX_mclk_128_Fs 0x00 #define HDMI_TX_mclk_256_Fs 0x01 #define HDMI_TX_mclk_384_Fs 0x02 #define HDMI_TX_mclk_512_Fs 0x03 // thresholds #define HDMI_TX_spdif_stable_th 0x03 // fs -> N(ACR) #define HDMI_TX_N_32k 0x1000 #define HDMI_TX_N_44k 0x1880 #define HDMI_TX_N_88k 0x3100 #define HDMI_TX_N_176k 0x6200 #define HDMI_TX_N_48k 0x1800 #define HDMI_TX_N_96k 0x3000 #define HDMI_TX_N_192k 0x6000 #define HDMI_TX_INITIAL 0x01 #define HDMI_TX_WAIT_HOTPLUG 0x02 #define HDMI_TX_READ_PARSE_EDID 0x03 //#define HDMI_TX_WAIT_RX_SENSE 0x04 #define HDMI_TX_CONFIG_VIDEO 0x05 #define HDMI_TX_CONFIG_AUDIO 0x07 #define HDMI_TX_CONFIG_PACKETS 0x08 #define HDMI_TX_HDCP_AUTHENTICATION 0x06 #define HDMI_TX_PLAY_BACK 0x09 #define HDMI_TX_RESET_LINK 0x0a #define spdif_error_th 0x0a #define Hresolution_1920 1920 #define Vresolution_540 540 #define Vresolution_1080 1080 #define Hresolution_1280 1280 #define Vresolution_720 720 #define Hresolution_640 640 #define Vresolution_480 480 #define Hresolution_720 720 #define Vresolution_240 240 #define Vresolution_576 576 #define Vresolution_288 288 #define Hz_50 50 #define Hz_60 60 #define Interlace_EDID 0 #define Progressive_EDID 1 #define ratio_16_9 1.777778 #define ratio_4_3 1.333333 #define HDMI_TX_EDID_BadHeader 0x01; #define HDMI_TX_EDID_861B_not_supported 0x02; #define HDMI_TX_EDID_CheckSum_ERR 0x03; #define HDMI_TX_EDID_No_ExtBlock 0x04; #define HDMI_TX_EDID_ExtBlock_NotFor_861B 0x05; //Reg difine // DEV_ADDR = 0x72 or 0x76 #define HDMI_TX_VND_IDL_REG 0x00 #define HDMI_TX_VND_IDH_REG 0x01 #define HDMI_TX_DEV_IDL_REG 0x02 #define HDMI_TX_DEV_IDH_REG 0x03 #define HDMI_TX_DEV_REV_REG 0x04 #define HDMI_TX_SRST_REG 0x05 #define HDMI_TX_SRST_MISC_TXPLL_RST 0x80 #define HDMI_TX_TMDS_CHNL_ALIGN 0x40 #define HDMI_TX_SRST_VIDCAP_RST 0x20 // bit position #define HDMI_TX_SRST_AFIFO_RST 0x10 // bit position #define HDMI_TX_SRST_HDCP_RST 0x08 // bit position #define HDMI_TX_SRST_VID_FIFO_RST 0x04 // bit position #define HDMI_TX_SRST_AUD_RST 0x02 // bit position #define HDMI_TX_SRST_SW_RST 0x01 // bit position #define HDMI_TX_SYS_STATE_REG 0x06 #define HDMI_TX_SYS_STATE_PLLF_MISC_LOCK 0x80 #define HDMI_TX_SYS_STATE_TXPLL_MISC_LOCK 0x40 #define HDMI_TX_SYS_STATE_AUD_CLK_DET 0x20 // bit position #define HDMI_TX_SYS_STATE_AVMUTE 0x10 // bit position #define HDMI_TX_SYS_STATE_HP 0x08 // bit position #define HDMI_TX_SYS_STATE_VSYNC 0x04 // bit position #define HDMI_TX_SYS_STATE_CLK_DET 0x02 // bit position #define HDMI_TX_SYS_STATE_RSV_DET 0x01 // bit position #define HDMI_TX_SYS_CTRL1_REG 0x07 #define HDMI_TX_SYS_CTRL1_LINKMUTE_EN 0x80 // bit position #define HDMI_TX_SYS_CTRL1_HDCPHPD_RST 0x40 // bit position #define HDMI_TX_SYS_CTRL1_PDINT_SEL 0x20 // bit position #define HDMI_TX_SYS_CTRL1_DDC_FAST 0x10 // bit position #define HDMI_TX_SYS_CTRL1_DDC_SWCTRL 0x08 // bit position #define HDMI_TX_SYS_CTRL1_HDCPMODE 0x04 // bit position #define HDMI_TX_SYS_CTRL1_HDMI 0x02 // bit position #define HDMI_TX_SYS_CTRL1_PWDN_CTRL 0x01 // bit position #define HDMI_TX_SYS_CTRL2_REG 0x08 #define HDMI_TX_SYS_CTRL2_DDC_RST 0x08 // bit position #define HDMI_TX_SYS_CTRL2_TMDSBIST_RST 0x04 // bit position #define HDMI_TX_SYS_CTRL2_MISC_RST 0x02 // bit position #define HDMI_TX_SYS_CTRL2_HW_RST 0x01 // bit position #define HDMI_TX_SYS_CTRL3_REG 0x09 #define HDMI_TX_SYS_CTRL3_PD_MACRO_ALL 0x04 // bit position #define HDMI_TX_SYS_CTRL3_I2C_PWON 0x02 // bit position #define HDMI_TX_SYS_CTRL3_PWON_ALL 0x01 // bit position #define HDMI_TX_SYS_CTRL4_REG 0x0A #define HDMI_TX_SYS_CTRL4_VID_BIT_CTRL_SHR 0x80 // bit position #define HDMI_TX_SYS_CTRL4_VH_SYNC_ALIGN_EN 0x04 // bit position #define HDMI_TX_SYS_CTRL4_AUD_MUTE 0x02 // bit position #define HDMI_TX_SYS_CTRL4_VID_MUTE 0x01 // bit position #define HDMI_TX_VID_STATUS_REG 0x10 #define HDMI_TX_VID_STATUS_VID_STABLE 0x20 // bit position #define HDMI_TX_VID_STATUS_EMSYNC_ERR 0x10 // bit position #define HDMI_TX_VID_STATUS_FLD_POL 0x08 // bit position #define HDMI_TX_VID_STATUS_TYPE 0x04 // bit position #define HDMI_TX_VID_STATUS_VSYNC_POL 0x02 // bit position #define HDMI_TX_VID_STATUS_HSYNC_POL 0x01 // bit position #define HDMI_TX_VID_MODE_REG 0x11 #define HDMI_TX_VID_MODE_CHKSHARED_EN 0x80 // bit position #define HDMI_TX_VID_MODE_LINKVID_EN 0x40 // bit position #define HDMI_TX_VID_MODE_RANGE_Y2R 0x20 // bit position #define HDMI_TX_VID_MODE_CSPACE_Y2R 0x10 // bit position #define HDMI_TX_VID_MODE_CSC_MODE_SEL 0x08 // bit position #define HDMI_TX_VID_MODE_UPSAMPLE 0x04 // bit position #define HDMI_TX_VID_CTRL_REG 0x12 #define HDMI_TX_VID_CTRL_IN_EN 0x10 // bit position #define HDMI_TX_VID_CTRL_DEF_PHS_AUTORST_EN 0x08 // bit position #define HDMI_TX_VID_CTRL_BITCTRL_EN 0x04 // bit position #define HDMI_TX_VID_CAPCTRL0_REG 0x13 #define HDMI_TX_VID_CAPCTRL0_DEGEN_EN 0x80 // bit position #define HDMI_TX_VID_CAPCTRL0_EMSYNC_EN 0x40 // bit position #define HDMI_TX_VID_CAPCTRL0_DEMUX_EN 0x20 // bit position #define HDMI_TX_VID_CAPCTRL0_INV_IDCK 0x10 // bit position #define HDMI_TX_VID_CAPCTRL0_DV_BUSMODE 0x08 // bit position #define HDMI_TX_VID_CAPCTRL0_DDR_EDGE 0x04 // bit position #define HDMI_TX_VID_CAPCTRL0_VIDBIT_SWAP 0x02 // bit position #define HDMI_TX_VID_CAPCTRL0_VIDBIST_EN 0x01 // bit position #define HDMI_TX_VID_CAPCTRL1_REG 0x14 #define HDMI_TX_VID_CAPCTRL1_FORMAT_SEL 0x80 // bit position #define HDMI_TX_VID_CAPCTRL1_VSYNC_POL 0x40 // bit position #define HDMI_TX_VID_CAPCTRL1_HSYNC_POL 0x20 // bit position #define HDMI_TX_VID_CAPCTRL1_INV_ESYNC_FLDPOL 0x10 // bit position #define HDMI_TX_VID_CAPCTRL1_VID_TYPE 0x08 // bit position #define HDMI_TX_H_RESL_REG 0x15 #define HDMI_TX_H_RESH_REG 0x16 #define HDMI_TX_VID_PIXL_REG 0x17 #define HDMI_TX_VID_PIXH_REG 0x18 #define HDMI_TX_H_FRONTPORCHL_REG 0x19 #define HDMI_TX_H_FRONTPORCHH_REG 0x1A #define HDMI_TX_HSYNC_ACT_WIDTHL_REG 0x1B #define HDMI_TX_HSYNC_ACT_WIDTHH_REG 0x1C #define HDMI_TX_H_BACKPORCHL_REG 0x1D #define HDMI_TX_H_BACKPORCHH_REG 0x1E #define HDMI_TX_V_RESL_REG 0x1F #define HDMI_TX_V_RESH_REG 0x20 #define HDMI_TX_ACT_LINEL_REG 0x21 #define HDMI_TX_ACT_LINEH_REG 0x22 #define HDMI_TX_ACT_LINE2VSYNC_REG 0x23 #define HDMI_TX_VSYNC_WID_REG 0x24 #define HDMI_TX_VSYNC_TAIL2VIDLINE_REG 0x25 #define HDMI_TX_VIDF_HRESL_REG 0x26 #define HDMI_TX_VIDF_HRESH_REG 0x27 #define HDMI_TX_VIDF_PIXL_REG 0x28 #define HDMI_TX_VIDF_PIXH_REG 0x29 #define HDMI_TX_VIDF_HFORNTPORCHL_REG 0x2A #define HDMI_TX_VIDF_HFORNTPORCHH_REG 0x2B #define HDMI_TX_VIDF_HSYNCWIDL_REG 0x2C #define HDMI_TX_VIDF_HSYNCWIDH_REG 0x2D #define HDMI_TX_VIDF_HBACKPORCHL_REG 0x2E #define HDMI_TX_VIDF_HBACKPORCHH_REG 0x2F #define HDMI_TX_VIDF_VRESL_REG 0x30 #define HDMI_TX_VIDF_VRESH_REG 0x31 #define HDMI_TX_VIDF_ACTVIDLINEL_REG 0x32 #define HDMI_TX_VIDF_ACTVIDLINEH_REG 0x33 #define HDMI_TX_VIDF_ACTLINE2VSYNC_REG 0x34 #define HDMI_TX_VIDF_VSYNCWIDLINE_REG 0x35 #define HDMI_TX_VIDF_VSYNCTAIL2VIDLINE_REG 0x36 #define HDMI_TX_VIDEO_MODE_REG 0x37 #define HDMI_TX_VIDEO_MODE_DC_LINK_HRES_SEL 0x80 // bit position #define HDMI_TX_VIDEO_MODE_DC_DEFAULT_PHASE 0x40 // bit position #define HDMI_TX_VIDEO_MODE_XVYCC_RNG_LMT 0x20 // bit position #define HDMI_TX_VIDEO_MODE_RGB_RNG_LMT 0x10 // bit position #define HDMI_TX_VIDEO_MODE_YC_RNG_LMT 0x08 // bit position #define HDMI_TX_VIDEO_MODE_DOWN_SAMPLE 0x04 // bit position #define HDMI_TX_VIDEO_MODE_RANGE_R2Y 0x02 // bit position #define HDMI_TX_VIDEO_MODE_CSPACE_R2Y 0x01 // bit position #define HDMI_TX_VID_CLK_FREQ_COUNTER 0x38 /* //Video input data bit control registers //#define VID_BIT_CTRL0 0x37 //added #define VID_BIT_CTRL1 0x38 #define VID_BIT_CTRL2 0x39 #define VID_BIT_CTRL3 0x3A #define VID_BIT_CTRL4 0x3B #define VID_BIT_CTRL5 0x3C #define VID_BIT_CTRL6 0x3D #define VID_BIT_CTRL7 0x3E #define VID_BIT_CTRL8 0x3F #define VID_BIT_CTRL9 0x48 #define VID_BIT_CTRL10 0x49 #define VID_BIT_CTRL11 0x4A #define VID_BIT_CTRL12 0x4B #define VID_BIT_CTRL13 0x4C #define VID_BIT_CTRL14 0x4D #define VID_BIT_CTRL15 0x4E #define VID_BIT_CTRL16 0x4F #define VID_BIT_CTRL17 0x89 #define VID_BIT_CTRL18 0x8A #define VID_BIT_CTRL19 0x8B #define VID_BIT_CTRL20 0x8C */ #define HDMI_TX_VID_CAP_CTRL2_REG 0x39 #define HDMI_TX_VID_CAP_CTRL2_FRM_CHK_INV_FLD 0x80 // bit position #define HDMI_TX_VID_CAP_CTRL2_ADJ_V_INV_FLD 0x40 // bit position #define HDMI_TX_VID_CAP_CTRL2_ADJ_VSYNC_EN 0x02 // bit position #define HDMI_TX_VID_CAP_CTRL2_ADJ_VSYNC_VALUE 0x01 // bit position #define HDMI_TX_VID_CAP_CTRL3_REG 0x3A #define HDMI_TX_VID_CAP_CTRL3_VSYNC_FPOS_SIGN 0x80 // bit position #define HDMI_TX_LINK_FORMAT_LINES_OFFSET0_REG 0x3B #define HDMI_TX_LINK_FORMAT_LINES_OFFSET0_VSYNC_BPOS_SIGN0 0x80 // bit position #define HDMI_TX_LINK_FORMAT_LINES_OFFSET0_VSYNC_BPOS_SIGN1 0x08 // bit position #define HDMI_TX_LINK_FORMAT_LINES_OFFSET1_REG 0x3C #define HDMI_TX_LINK_FORMAT_LINES_OFFSET1_ACT_LINEOS_SIGN0 0x80 // bit position #define HDMI_TX_LINK_FORMAT_LINES_OFFSET1_ACT_LINEOS_SIGN1 0X08 // bit position #define HDMI_TX_VID_MODE2_REG 0x3D #define HDMI_TX_VID_MODE2_OUTPUT_LIMIT_EN 0x80 // bit position #define HDMI_TX_VID_MODE2_OUTPUT_LIMIT_RANGE 0x40 // bit position #define HDMI_TX_VID_MODE2_O_YC422 0x20 // bit position #define HDMI_TX_VID_MODE2_O_YCBCR 0x10 // bit position #define HDMI_TX_VID_MODE2_VID_US_MODE 0x02 // bit position #define HDMI_TX_VID_MODE2_VID_DS_MODE 0x01 // bit position #define HDMI_TX_VID_MODE3_REG 0x3E #define HDMI_TX_VID_MODE3_YC422_BUS_ADJ_EN 0x80 #define HDMI_TX_VID_MODE3_BRU_EN 0x10 #define HDMI_TX_VID_MODE3_BRU_RND_DIR 0x02 #define HDMI_TX_VID_MODE3_DE_DEALY 0x01 #define HDMI_TX_INTR_STATE_REG 0x40 #define HDMI_TX_INTR_CTRL_REG 0x41 #define HDMI_TX_INTR_CTRL_SOFT_INTR 0x04 // bit position #define HDMI_TX_INTR_CTRL_TYPE 0x02 // bit position #define HDMI_TX_INTR_CTRL_POL 0x01 // bit position #define HDMI_TX_INTR1_STATUS_REG 0x42 #define HDMI_TX_INTR1_STATUS_CTS_CHG 0x80 // bit position #define HDMI_TX_INTR1_STATUS_AFIFO_UNDER 0x40 // bit position #define HDMI_TX_INTR1_STATUS_AFIFO_OVER 0x20 // bit position #define HDMI_TX_INTR1_STATUS_SPDIF_ERR 0x10 // bit position #define HDMI_TX_INTR1_STATUS_SW_INT 0x08 // bit position #define HDMI_TX_INTR1_STATUS_HP_CHG 0x04 // bit position #define HDMI_TX_INTR1_STATUS_CTS_OVRWR 0x02 // bit position #define HDMI_TX_INTR1_STATUS_CLK_CHG 0x01 // bit position #define HDMI_TX_INTR2_STATUS_REG 0x43 #define HDMI_TX_INTR2_STATUS_ENCEN_CHG 0x80 // bit position #define HDMI_TX_INTR2_STATUS_HDCPLINK_CHK 0x40 // bit position #define HDMI_TX_INTR2_STATUS_HDCPENHC_CHK 0x20 // bit position #define HDMI_TX_INTR2_STATUS_BKSV_RDY 0x10 // bit position #define HDMI_TX_INTR2_STATUS_PLLLOCK_CHG 0x08 // bit position #define HDMI_TX_INTR2_STATUS_SHA_DONE 0x04 // bit position #define HDMI_TX_INTR2_STATUS_AUTH_CHG 0x02 // bit position #define HDMI_TX_INTR2_STATUS_AUTH_DONE 0x01 // bit position #define HDMI_TX_INTR3_STATUS_REG 0x44 #define HDMI_TX_INTR3_STATUS_SPDIFBI_ERR 0x80 // bit position #define HDMI_TX_INTR3_STATUS_VIDF_CHG 0x40 // bit position #define HDMI_TX_INTR3_STATUS_AUDCLK_CHG 0x20 // bit position #define HDMI_TX_INTR3_STATUS_DDCACC_ERR 0x10 // bit position #define HDMI_TX_INTR3_STATUS_DDC_NOACK 0x08 // bit position #define HDMI_TX_INTR3_STATUS_VSYNC_DET 0x04 // bit position #define HDMI_TX_INTR3_STATUS_RXSEN_CHG 0x02 // bit position #define HDMI_TX_INTR3_STATUS_SPDIF_UNSTBL 0x01 // bit position #define HDMI_TX_INTR1_MASK_REG 0x45 #define HDMI_TX_INTR2_MASK_REG 0x46 #define HDMI_TX_INTR3_MASK_REG 0x47 #define HDMI_TX_INTR4_STATUS_REG 0x48 #define HDMI_TX_INTR4_STATUS_DDC_FIFO_FULL 0x80 // bit position #define HDMI_TX_INTR4_STATUS_DDC_FIFO_EMPTY 0x40 // bit position #define HDMI_TX_INTR4_STATUS_DDC_FIFO_HALF 0x20 // bit position #define HDMI_TX_INTR4_STATUS_DDC_ACC_DONE 0x10 // bit position #define HDMI_TX_INTR4_STATUS_CEC_MSG_READY 0x08 // bit position #define HDMI_TX_INTR4_STATUS_CEC_TX_DONE 0x04 // bit position #define HDMI_TX_INTR4_STATUS_SAUD_STATIC_DET 0x02 // bit position #define HDMI_TX_INTR4_STATUS_SAUD_INVAL_DET 0x01 // bit position #define HDMI_TX_INTR5_STATUS_REG 0x49 #define HDMI_TX_INTR5_STATUS_DEFAULT_PHASE_ERR 0x80 // bit position #define HDMI_TX_INTR5_STATUS_R0_CHK_FLAG 0x40 // bit position #define HDMI_TX_INTR5_STATUS_LINK_CHK_TIMEOUT 0x20 // bit position #define HDMI_TX_INTR5_STATUS_RI_NO_UPDATE 0x10 // bit position #define HDMI_TX_INTR5_STATUS_SYNC_PRE_CHK_FAIL 0x08 // bit position #define HDMI_TX_INTR5_STATUS_SYNC_POST_CHK_FAIL 0x04 // bit position #define HDMI_TX_INTR5_STATUS_HDCP_LNK_CHK_FAIL 0x02 // bit position #define HDMI_TX_INTR5_STATUS_HDCP_ENHC_CHK_FAIL 0x01 // bit position #define HDMI_TX_INTR4_MASK_REG 0x4A #define HDMI_TX_INTR5_MASK_REG 0x4B #define HDMI_TX_HDMI_AUDCTRL0_REG 0x50 #define HDMI_TX_HDMI_AUDCTRL0_LAYOUT 0x80 // bit position #define HDMI_TX_HDMI_AUDCTRL0_DOWN_SMPL 0x60 // bit position #define HDMI_TX_HDMI_AUDCTRL0_CTSGEN_SC0 0x10 // bit position #define HDMI_TX_HDMI_AUDCTRL0_INV_AUDCLK 0x08 // bit position #define HDMI_TX_HDMI_AUDCTRL1_REG 0x51 #define HDMI_TX_HDMI_AUDCTRL1_IN_EN 0x80 // bit position #define HDMI_TX_HDMI_AUDCTRL1_SPDIFIN_EN 0x40 // bit position #define HDMI_TX_HDMI_AUDCTRL1_SD3IN_EN 0x20 // bit position #define HDMI_TX_HDMI_AUDCTRL1_SD2IN_EN 0x10 // bit position #define HDMI_TX_HDMI_AUDCTRL1_SD1IN_EN 0x08 // bit position #define HDMI_TX_HDMI_AUDCTRL1_SD0IN_EN 0x04 // bit position #define HDMI_TX_HDMI_AUDCTRL1_SPDIFFS_OVRWR 0x02 // bit position #define HDMI_TX_HDMI_AUDCTRL1_CLK_SEL0 0x01 // bit position #define HDMI_TX_I2S_CTRL_REG 0x52 #define HDMI_TX_I2S_CTRL_VUCP 0x80 // bit position #define HDMI_TX_I2S_CTRL_SHIFT_CTRL 0x08 // bit position #define HDMI_TX_I2S_CTRL_DIR_CTRL 0x04 // bit position #define HDMI_TX_I2S_CTRL_WS_POL 0x02 // bit position #define HDMI_TX_I2S_CTRL_JUST_CTRL 0x01 // bit position #define HDMI_TX_I2SCH_CTRL_REG 0x53 #define HDMI_TX_I2SCH_FIFO3_SEL 0xC0 // bit position #define HDMI_TX_I2SCH_FIFO2_SEL 0x30 // bit position #define HDMI_TX_I2SCH_FIFO1_SEL 0x0C // bit position #define HDMI_TX_I2SCH_FIFO0_SEL 0x03 // bit position #define HDMI_TX_I2SCH_SWCTRL_REG 0x54 #define HDMI_TX_I2SCH_SWCTRL_SW3 0x80 // bit position #define HDMI_TX_I2SCH_SWCTRL_SW2 0x40 // bit position #define HDMI_TX_I2SCH_SWCTRL_SW1 0x20 // bit position #define HDMI_TX_I2SCH_SWCTRL_SW0 0x10 // bit position #define HDMI_TX_I2SCH_SWCTRL_INWD_LEN 0xE0 // bit position #define HDMI_TX_I2SCH_SWCTRL_INWD_MAX 0x01 // bit position #define HDMI_TX_SPDIFCH_STATUS_REG 0x55 #define HDMI_TX_SPDIFCH_STATUS_FS_FREG 0xF0 // bit position #define HDMI_TX_SPDIFCH_STATUS_WD_LEN 0x0E // bit position #define HDMI_TX_SPDIFCH_STATUS_WD_MX 0x01 // bit position #define HDMI_TX_I2SCH_STATUS1_REG 0x56 #define HDMI_TX_I2SCH_STATUS1_MODE 0xC0 // bit position #define HDMI_TX_I2SCH_STATUS1_PCM_MODE 0x38 // bit position #define HDMI_TX_I2SCH_STATUS1_SW_CPRGT 0x04 // bit position #define HDMI_TX_I2SCH_STATUS1_NON_PCM 0x02 // bit position #define HDMI_TX_I2SCH_STATUS1_PROF_APP 0x01 // bit position #define HDMI_TX_I2SCH_STATUS2_REG 0x57 #define HDMI_TX_I2SCH_STATUS3_REG 0x58 #define HDMI_TX_I2SCH_STATUS3_CH_NUM 0xF0 // bit position #define HDMI_TX_I2SCH_STATUS3_SRC_NUM 0x0F // bit position #define HDMI_TX_I2SCH_STATUS4_REG 0x59 #define HDMI_TX_I2SCH_STATUS5_REG 0x5A #define HDMI_TX_I2SCH_STATUS5_WORD_MAX 0x01 // bit position #define HDMI_TX_HDMI_AUDSTATUS_REG 0x5B #define HDMI_TX_HDMI_AUDSTATUS_SPDIF_DET 0x01 // bit position #define HDMI_TX_HDMI_AUDBIST_CTRL_REG 0x5C #define HDMI_TX_HDMI_AUDBIST_EN3 0x08 // bit position #define HDMI_TX_HDMI_AUDBIST_EN2 0x04 // bit position #define HDMI_TX_HDMI_AUDBIST_EN1 0x02 // bit position #define HDMI_TX_HDMI_AUDBIST_EN0 0x01 // bit position #define HDMI_TX_AUD_INCLK_CNT_REG 0x5D #define HDMI_TX_AUD_DEBUG_STATUS_REG 0x5E #define HDMI_TX_AUD_CTRL2_REG 0x5F #define HDMI_TX_AUD_CTRL2_AUD_LAYOUT_CTRL 0x80 // bit position #define HDMI_TX_AUD_CTRL2_AUD_HBR_EN 0x40 // bit position #define HDMI_TX_AUD_CTRL2_CTS_GEN_SC1 0x08 // bit position #define HDMI_TX_AUD_CTRL2_AUD_CLK_SEL1 0x04 // bit position #define HDMI_TX_AUD_CTRL2_AUD_CS_CTRL 0x02 // bit position #define HDMI_TX_AUD_CTRL2_AUD_VBIT 0x01 // bit position #define HDMI_TX_ONEBIT_AUD_CTRL_REG 0x60 #define HDMI_TX_ONEBIT_AUD_CTRL_SEN7 0x80 // bit position #define HDMI_TX_ONEBIT_AUD_CTRL_SEN6 0x40 // bit position #define HDMI_TX_ONEBIT_AUD_CTRL_SEN5 0x20 // bit position #define HDMI_TX_ONEBIT_AUD_CTRL_SEN4 0x10 // bit position #define HDMI_TX_ONEBIT_AUD_CTRL_SEN3 0x08 // bit position #define HDMI_TX_ONEBIT_AUD_CTRL_SEN2 0x04 // bit position #define HDMI_TX_ONEBIT_AUD_CTRL_SEN1 0x02 // bit position #define HDMI_TX_ONEBIT_AUD_CTRL_SEN0 0x01 // bit position #define HDMI_TX_ONEBIT_AUD0_CTRL_REG 0x61 #define HDMI_TX_ONEBIT_AUD1_CTRL_REG 0x62 #define HDMI_TX_ONEBIT_AUD2_CTRL_REG 0x63 #define HDMI_TX_ONEBIT_AUD3_CTRL_REG 0x64 #define HDMI_TX_ONEBIT_AUDCLK_CTRL_REG 0x65 #define HDMI_TX_ONEBIT_AUDCLK_DET 0x08 // bit position #define HDMI_TX_SPDIF_ERR_THRSHLD_REG 0x66 #define HDMI_TX_SPDIF_ERR_CNT_REG 0x67 #define HDMI_TX_HBIT_AUD_CTRL_REG 0x68 #define HDMI_TX_HDMI_LINK_CTRL_REG 0x70 #define HDMI_TX_HDMI_LINK_DATA_MUTEEN1 0x80 // bit position #define HDMI_TX_HDMI_LINK_DATA_MUTEEN0 0x40 // bit position #define HDMI_TX_HDMI_LINK_CLK_MUTEEN2 0x20 // bit position #define HDMI_TX_HDMI_LINK_CLK_MUTEEN1 0x10 // bit position #define HDMI_TX_HDMI_LINK_CLK_MUTEEN0 0x08 // bit position #define HDMI_TX_HDMI_LINK_DEC_DE 0x04 // bit position #define HDMI_TX_HDMI_LINK_PRMB_INC 0x02 // bit position #define HDMI_TX_HDMI_LINK_AUTO_PROG 0x01 // bit position #define HDMI_TX_VID_CAPCTRL2_REG 0x71 #define HDMI_TX_VID_CAPCTRL2_CHK_UPDATEEN 0x10 // bit position #define HDMI_TX_LINK_MUTEEE_REG 0x72 #define HDMI_TX_LINK_MUTEEE_AVMUTE_EN2 0x20 // bit position #define HDMI_TX_LINK_MUTEEE_AVMUTE_EN1 0x10 // bit position #define HDMI_TX_LINK_MUTEEE_AVMUTE_EN0 0x08 // bit position #define HDMI_TX_LINK_MUTEEE_AUDMUTE_EN2 0x04 // bit position #define HDMI_TX_LINK_MUTEEE_AUDMUTE_EN1 0x02 // bit position #define HDMI_TX_LINK_MUTEEE_AUDMUTE_EN0 0x01 // bit position #define HDMI_TX_SERDES_TEST0_REG 0x73 #define HDMI_TX_SERDES_TEST1_REG 0x74 #define HDMI_TX_SERDES_TEST2_REG 0x75 #define HDMI_TX_I2C_US_COUNTER0_REG 0x76 #define HDMI_TX_I2C_US_COUNTER1_REG 0x77 #define HDMI_TX_PLL_MISC_CTRL0_REG 0x78 #define HDMI_TX_PLL_MISC_CTRL0_TIMER_SEL 0x20 // bit position #define HDMI_TX_PLL_MISC_CTRL0_RNGCHK_EN 0x10 // bit position #define HDMI_TX_PLL_MISC_CTRL0_FORCE_PLLF_LOCK 0x02 // bit position #define HDMI_TX_PLL_MISC_CTRL0_PLLF_MAN_RNG 0x01 // bit position #define HDMI_TX_PLL_MISC_CTRL1_REG 0x79 #define HDMI_TX_PLL_MISC_CTRL1_MISC_MODE_SEL 0x80 // bit position #define HDMI_TX_PLL_MISC_CTRL1_FORCE_TXPLL_LOCK 0x02 // bit position #define HDMI_TX_PLL_MISC_CTRL1_TXPLL_MAN_RNG 0x01 // bit position #define HDMI_TX_ANALOG_BLK_CTRL_REG 0x7A #define HDMI_TX_DDC_SLV_ADDR_REG 0x80 #define HDMI_TX_DDC_SLV_SEGADDR_REG 0x81 #define HDMI_TX_DDC_SLV_OFFADDR_REG 0x82 #define HDMI_TX_DDC_ACC_CMD_REG 0x83 #define HDMI_TX_DDC_ACCNUM0_REG 0x84 #define HDMI_TX_DDC_ACCNUM1_REG 0x85 #define HDMI_TX_DDC_CHSTATUS_REG 0x86 #define HDMI_TX_DDC_CHSTATUS_DDCERR 0x80 // bit position #define HDMI_TX_DDC_CHSTATUS_DDC_OCCUPY 0x40 // bit position #define HDMI_TX_DDC_CHSTATUS_FIFO_FULL 0x20 // bit position #define HDMI_TX_DDC_CHSTATUS_FIFO_EMPT 0x10 // bit position #define HDMI_TX_DDC_CHSTATUS_NOACK 0x08 // bit position #define HDMI_TX_DDC_CHSTATUS_FIFO_RD 0x04 // bit position #define HDMI_TX_DDC_CHSTATUS_FIFO_WR 0x02 // bit position #define HDMI_TX_DDC_CHSTATUS_INPRO 0x01 // bit position #define HDMI_TX_DDC_FIFO_ACC_REG 0x87 #define HDMI_TX_DDC_FIFOCNT_REG 0x88 #define HDMI_TX_ANA_BLK_CTRL0_REG 0x8A #define HDMI_TX_ANA_BLK_CTRL0_OSC_CLK_TEST_EN 0x80 // bit position #define HDMI_TX_ANA_BLK_CTRL0_PLL_CLK_TEST_EN 0x40 // bit position #define HDMI_TX_ANA_BLK_CTRL0_ST_EN 0x10 // bit position #define HDMI_TX_PLLF_CTRL0_REG 0x8B #define HDMI_TX_PLLF_CTRL0_PLLF_BYPASS 0x80 #define HDMI_TX_PLLF_CTRL0_PLLF_SELREG 0x40 #define HDMI_TX_LINK_PLL_CTRL0_REG 0x8C #define HDMI_TX_LINK_PLL_CTRL0_SEL_DIV2 0x80 #define HDMI_TX_PLLF_PLL_CTRL_REG 0x8D #define HDMI_TX_PLLF_PLL_CTRL_TXPLL_RCNER 0x80 #define HDMI_TX_PLLF_PLL_CTRL_TXPLL_SELREG 0x10 #define HDMI_TX_ANA_BLK_CTRL1_REG 0x8E #define HDMI_TX_ANA_BLK_CTRL2_REG 0x8F #define HDMI_TX_SYS_PD_REG 0x90 #define HDMI_TX_SYS_PD_TXPLL 0x80 // bit position #define HDMI_TX_SYS_PD_TMDS 0x40 // bit position #define HDMI_TX_SYS_PD_TMDS_CLK 0x20 // bit position #define HDMI_TX_SYS_PD_MISC 0x10 // bit position #define HDMI_TX_SYS_PD_LINK 0x08 // bit position #define HDMI_TX_SYS_PD_IDCK 0x04 // bit position #define HDMI_TX_SYS_PD_AUD 0x02 // bit position #define HDMI_TX_SYS_PD_PLLF 0x01 // bit position #define HDMI_TX_PLLF_CTRL1_REG 0x91 #define HDMI_TX_PLLF_CTRL1_PLLF_LOCK 0x80 #define HDMI_TX_PLLF_CTRL1_PLLF_IND_H 0x40 #define HDMI_TX_PLLF_CTRL1_PLLF_IND_L 0x20 #define HDMI_TX_PLLF_CTRL1_PLLF_TEST_EN 0x01 #define HDMI_TX_PLLF_CTRL2_REG 0x92 #define HDMI_TX_PLLF_CTRL2_SEL_PLLF_TX 0x80 #define HDMI_TX_PLLF_CTRL2_PLLF_RCORER 0x40 #define HDMI_TX_TX_PLL_CTRL1_REG 0x93 #define HDMI_TX_TX_PLL_CTRL1_TX_PLL_LOCK 0x80 #define HDMI_TX_TX_PLL_CTRL1_IND_H 0x40 #define HDMI_TX_TX_PLL_CTRL1_IND_L 0x20 #define HDMI_TX_TX_PLL_CTRL1_TX_PLL_TEST_EN 0x01 #define HDMI_TX_TX_PLL_CTRL2_REG 0x94 #define HDMI_TX_TX_PLL_CTRL2_PD_CLK_TEST 0x80 #define HDMI_TX_TX_PLL_CTRL2_TXPLL_CPREG_BLEED 0x40 #define HDMI_TX_OSC_CTRL_REG 0x95 #define HDMI_TX_OSC_CTRL_SEL_BG 0x80 // bit position #define HDMI_TX_TMDS_CH0_CONFIG_REG 0x96 #define HDMI_TX_TMDS_CH0_TESTEN 0x20 // bit position //#define HDMI_TX_TMDS_CH0_AMP 0x1C // bit position //#define HDMI_TX_TMDS_CHO_EMP 0x03 // bit position #define HDMI_TX_TMDS_CH1_CONFIG_REG 0x97 #define HDMI_TX_TMDS_CH1_TESTEN 0x20 // bit position //#define HDMI_TX_TMDS_CH1_AMP 0x1C // bit position //#define HDMI_TX_TMDS_CH1_EMP 0x03 // bit position #define HDMI_TX_TMDS_CH2_CONFIG_REG 0x98 #define HDMI_TX_TMDS_CH2_TESTEN 0x20 // bit position #define HDMI_TX_TMDS_CH2_AMP 0x1C // bit position #define HDMI_TX_TMDS_CH2_EMP 0x03 // bit position #define HDMI_TX_TMDS_CLKCH_CONFIG_REG 0x99 #define HDMI_TX_TMDS_CLKCH_MUTE 0x80 // bit position #define HDMI_TX_TMDS_CLKCH_ST_EN 0x40 //bit position #define HDMI_TX_TMDS_CLKCH_TESTEN 0x20 // bit position //#define HDMI_TX_TMDS_CLKCH_AMP 0x07 // bit position #define HDMI_TX_CHIP_CTRL_REG 0x9A #define HDMI_TX_CHIP_CTRL_PRBS_GENEN 0x80 // bit position //#define HDMI_TX_CHIP_CTRL_LINK_DBGSEL 0x70 // bit position #define HDMI_TX_CHIP_CTRL_VID_IF_CHK_EN 0x08 // bit position //#define HDMI_TX_CHIP_CTRL_MISC_TIMER 0x04 // bit position #define HDMI_TX_CHIP_CTRL_DDC_LEVEL 0x02 // bit position #define HDMI_TX_CHIP_CTRL_DDC_SMI 0x01 // bit position #define HDMI_TX_CHIP_STATUS_REG 0x9B #define HDMI_TX_CHIP_STATUS_GPIO_DEV_ADDR_IN 0x80 // bit position #define HDMI_TX_CHIP_STATUS_SDA_ST 0x40 // bit position #define HDMI_TX_CHIP_STATUS_SCL_ST 0x20 // bit position #define HDMI_TX_CHIP_STATUS_VFIFO_OVER 0x10 // bit position #define HDMI_TX_CHIP_STATUS_VFIFO_UNDER 0x08 // bit position #define HDMI_TX_DBG_PINGPIO_CTRL_REG 0x9C #define HDMI_TX_DBG_PINGPIO_VDLOW_SHAREDEN 0x04 // bit position #define HDMI_TX_DBG_PINGPIO_GPIO_ADDREN 0x02 // bit position #define HDMI_TX_DBG_PINGPIO_GPIO_OUT 0x01 // bit position #define HDMI_TX_CHIP_DEBUG0_CTRL_REG 0x9D #define HDMI_TX_CHIP_DEBUG0_PRBS_ERR 0xE0 // bit position #define HDMI_TX_CHIP_DEBUG0_CAPST 0x1F // bit position #define HDMI_TX_CHIP_DEBUG1_CTRL_REG 0x9E #define HDMI_TX_CHIP_DEBUG1_SDA_SW 0x80 // bit position #define HDMI_TX_CHIP_DEBUG1_SCL_SW 0x40 // bit position #define HDMI_TX_CHIP_DEBUG1_SERDES_TESTEN 0x20 // bit position #define HDMI_TX_CHIP_DEBUG1_CLK_BYPASS 0x10 // bit position #define HDMI_TX_CHIP_DEBUG1_INV_INTER_IDCK 0x08 // bit position #define HDMI_TX_CHIP_DEBUG1_PLLLOCK_BYPASS 0x04 // bit position #define HDMI_TX_CHIP_DEBUG1_FORCE_HP 0x02 // bit position #define HDMI_TX_CHIP_DEBUG1_HP_DEGLITCH 0x01 // bit position #define HDMI_TX_CHIP_DEBUG2_CTRL_REG 0x9F #define HDMI_TX_CHIP_DEBUG2_EXEMB_SYNCEN 0x04 // bit position #define HDMI_TX_CHIP_DEBUG2_VIDBIST 0x02 // bit position #define HDMI_TX_VID_INCLK_REG 0x5F #define HDMI_TX_HDCP_STATUS_REG 0xA0 #define HDMI_TX_HDCP_STATUS_ADV_CIPHER 0x80 // bit position #define HDMI_TX_HDCP_STATUS_R0_READY 0x10 // bit position #define HDMI_TX_HDCP_STATUS_AKSV_ACT 0x08 // bit position #define HDMI_TX_HDCP_STATUS_ENCRYPT 0x04 // bit position #define HDMI_TX_HDCP_STATUS_AUTH_PASS 0x02 // bit position #define HDMI_TX_HDCP_STATUS_KEY_DONE 0x01 // bit position #define HDMI_TX_HDCP_CTRL0_REG 0xA1 #define HDMI_TX_HDCP_CTRL0_STORE_AN 0x80 // bit position #define HDMI_TX_HDCP_CTRL0_RX_REP 0x40 // bit position #define HDMI_TX_HDCP_CTRL0_RE_AUTH 0x20 // bit position #define HDMI_TX_HDCP_CTRL0_SW_AUTHOK 0x10 // bit position #define HDMI_TX_HDCP_CTRL0_HW_AUTHEN 0x08 // bit position #define HDMI_TX_HDCP_CTRL0_ENC_EN 0x04 // bit position #define HDMI_TX_HDCP_CTRL0_BKSV_SRM 0x02 // bit position #define HDMI_TX_HDCP_CTRL0_KSV_VLD 0x01 // bit position #define HDMI_TX_HDCP_CTRL1_REG 0xA2 #define HDMI_TX_HDCP_CTRL1_SYNC_CHK_TIME_SEL 0x80 // bit position #define HDMI_TX_LINK_CHK_12_EN 0x40 #define HDMI_TX_HDCP_CTRL1_DDC_NOSTOP 0x20 // bit position #define HDMI_TX_HDCP_CTRL1_DDC_NOACK 0x10 // bit position #define HDMI_TX_HDCP_CTRL1_EDDC_NOACK 0x08 // bit position #define HDMI_TX_HDCP_CTRL1_BLUE_SCREEN_EN 0x04 // bit position #define HDMI_TX_HDCP_CTRL1_RCV11_EN 0x02 // bit position #define HDMI_TX_HDCP_CTRL1_HDCP11_EN 0x01 // bit position #define HDMI_TX_HDCP_Link_Check_FRAME_NUM_REG 0xA3 #define HDMI_TX_HDCP_CTRL2_REG 0xA4 #define HDMI_TX_HDCP_CTRL2_LINK_AUTO_CHK_EN 0x80 #define HDMI_TX_HDCP_CTRL2_LINK_DBL_CHK_EN 0x40 #define HDMI_TX_HDCP_CTRL2_DERIVE_NEXT_AN 0x04 #define HDMI_TX_HDCP_CTRL2_SOFT_LINK_AUTOCHK_EN 0x02 #define HDMI_TX_HDCP_CTRL2_LINK_CHK_SOFT_JUDGE 0x01 #define HDMI_TX_HDCP_AKSV1_REG 0xA5 #define HDMI_TX_HDCP_AKSV2_REG 0xA6 #define HDMI_TX_HDCP_AKSV3_REG 0xA7 #define HDMI_TX_HDCP_AKSV4_REG 0xA8 #define HDMI_TX_HDCP_AKSV5_REG 0xA9 #define HDMI_TX_HDCP_AN1_REG 0xAA #define HDMI_TX_HDCP_AN2_REG 0xAB #define HDMI_TX_HDCP_AN3_REG 0xAC #define HDMI_TX_HDCP_AN4_REG 0xAD #define HDMI_TX_HDCP_AN5_REG 0xAE #define HDMI_TX_HDCP_AN6_REG 0xAF #define HDMI_TX_HDCP_AN7_REG 0xB0 #define HDMI_TX_HDCP_AN8_REG 0xB1 #define HDMI_TX_HDCP_BKSV1_REG 0xB2 #define HDMI_TX_HDCP_BKSV2_REG 0xB3 #define HDMI_TX_HDCP_BKSV3_REG 0xB4 #define HDMI_TX_HDCP_BKSV4_REG 0xB5 #define HDMI_TX_HDCP_BKSV5_REG 0xB6 #define HDMI_TX_HDCP_RI1_REG 0xB7 #define HDMI_TX_HDCP_RI2_REG 0xB8 #define HDMI_TX_HDCP_PJ_REG 0xB9 #define HDMI_TX_HDCP_RX_CAPS_REG 0xBA #define HDMI_TX_HDCP_BSTATUS0_REG 0xBB #define HDMI_TX_HDCP_BSTATUS1_REG 0xBC #define HDMI_TX_HDCP_AMO0_REG 0xD0 #define HDMI_TX_HDCP_AMO1_REG 0xD1 #define HDMI_TX_HDCP_AMO2_REG 0xD2 #define HDMI_TX_HDCP_AMO3_REG 0xD3 #define HDMI_TX_HDCP_AMO4_REG 0xD4 #define HDMI_TX_HDCP_AMO5_REG 0xD5 #define HDMI_TX_HDCP_AMO6_REG 0xD6 #define HDMI_TX_HDCP_AMO7_REG 0xD7 #define HDMI_TX_HDCP_DBG_CTRL_REG 0xBD #define HDMI_TX_HDCP_DBG_CTRL_FORCE_RI_INV 0x20 // bit position #define HDMI_TX_HDCP_DBG_CTRL_HLD_RI_VALUE 0X10 // bit position #define HDMI_TX_HDCP_DBG_ENC_WIN_INC 0x08 // bit position //#define HDMI_TX_HDCP_DBG_DDC_SPEED 0x06 // bit position #define HDMI_TX_HDCP_DBG_SKIP_RPT 0x01 // bit position #define HDMI_TX_HDCP_KEY_STATUS_REG 0xBE #define HDMI_TX_HDCP_KEY_BIST_EN 0x04 // bit position #define HDMI_TX_HDCP_KEY_BIST_ERR 0x02 // bit position #define HDMI_TX_HDCP_KEY_CMD_DONE 0x01 // bit position #define HDMI_TX_KEY_CMD_REGISTER 0xBF //added #define HDMI_TX_HDCP_AUTHDBG_STATUS_REG 0xC7 #define HDMI_TX_HDCP_ENCRYPTDBG_STATUS_REG 0xC8 #define HDMI_TX_HDCP_FRAME_NUM_REG 0xC9 #define HDMI_TX_DDC_MSTR_INTER_REG 0xCA #define HDMI_TX_DDC_MSTR_LINK_REG 0xCB #define HDMI_TX_HDCP_BLUESCREEN0_REG 0xCC #define HDMI_TX_HDCP_BLUESCREEN1_REG 0xCD #define HDMI_TX_HDCP_BLUESCREEN2_REG 0xCE #define HDMI_TX_HDCP_WAIT_R0_TIMING_REG 0xE0 #define HDMI_TX_HDCP_LINK_INTEGRITY_CHK_TIMER_REG 0xE1 #define HDMI_TX_HDCP_REPEATER_READY_WAIT_TIMER_REG 0xE2 #define HDMI_TX_HDCP_REPEATER_WAIT_TIMING0_REG 0xE3 #define HDMI_TX_HDCP_REPEATER_WAIT_TIMING1_REG 0xE4 // DEV_ADDR = 0x7A or 0x7E #define HDMI_TX_INFO_PKTCTRL1_REG 0xC0 #define HDMI_TX_INFO_PKTCTRL1_SPD_RPT 0x80 // bit position #define HDMI_TX_INFO_PKTCTRL1_SPD_EN 0x40 // bit position #define HDMI_TX_INFO_PKTCTRL1_AVI_RPT 0x20 // bit position #define HDMI_TX_INFO_PKTCTRL1_AVI_EN 0x10 // bit position #define HDMI_TX_INFO_PKTCTRL1_GCP_RPT 0x08 // bit position #define HDMI_TX_INFO_PKTCTRL1_GCP_EN 0x04 // bit position #define HDMI_TX_INFO_PKTCTRL1_ACR_NEW 0x02 // bit position #define HDMI_TX_INFO_PKTCTRL1_ACR_EN 0x01 // bit position #define HDMI_TX_INFO_PKTCTRL2_REG 0xC1 #define HDMI_TX_INFO_PKTCTRL2_UD1_RPT 0x80 // bit position #define HDMI_TX_INFO_PKTCTRL2_UD1_EN 0x40 // bit position #define HDMI_TX_INFO_PKTCTRL2_UD0_RPT 0x20 // bit position #define HDMI_TX_INFO_PKTCTRL2_UD0_EN 0x10 // bit position #define HDMI_TX_INFO_PKTCTRL2_MPEG_RPT 0x08 // bit position #define HDMI_TX_INFO_PKTCTRL2_MPEG_EN 0x04 // bit position #define HDMI_TX_INFO_PKTCTRL2_AIF_RPT 0x02 // bit position #define HDMI_TX_INFO_PKTCTRL2_AIF_EN 0x01 // bit position #define HDMI_TX_ACR_N1_SW_REG 0xC2 #define HDMI_TX_ACR_N2_SW_REG 0xC3 #define HDMI_TX_ACR_N3_SW_REG 0xC4 #define HDMI_TX_ACR_CTS1_SW_REG 0xC5 #define HDMI_TX_ACR_CTS2_SW_REG 0xC6 #define HDMI_TX_ACR_CTS3_SW_REG 0xC7 #define HDMI_TX_ACR_CTS1_HW_REG 0xC8 #define HDMI_TX_ACR_CTS2_HW_REG 0xC9 #define HDMI_TX_ACR_CTS3_HW_REG 0xCA #define HDMI_TX_ACR_CTS_CTRL_REG 0xCB #define HDMI_TX_GNRL_CTRL_PKT_REG 0xCC #define HDMI_TX_GNRL_CTRL_PKT_GCP_DCP_CTRL 0x80 // bit position #define HDMI_TX_GNRL_CTRL_PKT_DC_PKT_EN 0x40 // bit position #define HDMI_TX_GNRL_CTRL_CLR_AVMUTE 0x02 // bit position #define HDMI_TX_GNRL_CTRL_SET_AVMUTE 0x01 // bit position #define HDMI_TX_AUD_PKT_FLATCTRL_REG 0xCD #define HDMI_TX_AUD_PKT_AUTOFLAT_EN 0x80 // bit position #define HDMI_TX_AUD_PKT_FLATCTRL_GCP_DCP_OR_DER_CTRL 0x20 // bit position #define HDMI_TX_AUD_PKT_FLATCTRL_GCP_DCP_CONTENT_CTRL 0x10 // bit position #define HDMI_TX_AUD_PKT_FLAT 0x07 // bit position #define HDMI_TX_GCP_HEADER_ID_REG 0xCE #define HDMI_TX_AUD_PACKET_HEADER_ID_REG 0xCF #define HDMI_TX_CEC_CTRL_REG 0xD0 #define HDMI_TX_CEC_CTRL_RX_EN 0x08 // bit position #define HDMI_TX_CEC_CTRL_TX_ST 0x04 // bit position #define HDMI_TX_CEC_CTRL_PIN_SEL 0x02 // bit position #define HDMI_TX_CEC_CTRL_RESET 0x01 // bit position #define HDMI_TX_CEC_RX_STATUS_REG 0xD1 #define HDMI_TX_CEC_RX_STATUS_RX_BUSY 0x80 // bit position #define HDMI_TX_CEC_RX_STATUS_RX_FULL 0x20 // bit position #define HDMI_TX_CEC_RX_STATUS_RX_EMP 0x10 // bit position #define HDMI_TX_CEC_TX_STATUS_REG 0xD2 #define HDMI_TX_CEC_TX_STATUS_TX_BUSY 0x80 // bit position #define HDMI_TX_CEC_TX_STATUS_TX_FAIL 0x40 // bit position #define HDMI_TX_CEC_TX_STATUS_TX_FULL 0x20 // bit position #define HDMI_TX_CEC_TX_STATUS_TX_EMPTY 0x10 // bit position #define HDMI_TX_CEC_TX_FIFO_REG 0xD3 #define HDMI_TX_CEC_SPEED_CTRL_REG 0xD4 //InfoFrame and Control Packet Registers // 0x7A or 0X7E #define AVI_HB0 0x00 #define AVI_HB1 0x01 #define AVI_HB2 0x02 #define AVI_PB0 0x03 #define AVI_PB1 0x04 #define AVI_PB2 0x05 #define AVI_PB3 0x06 #define AVI_PB4 0x07 #define AVI_PB5 0x08 #define AVI_PB6 0x09 #define AVI_PB7 0x0A #define AVI_PB8 0x0B #define AVI_PB9 0x0C #define AVI_PB10 0x0D #define AVI_PB11 0x0E #define AVI_PB12 0x0F #define AVI_PB13 0x10 #define AVI_PB14 0x11 #define AVI_PB15 0x12 #define AUD_HBO 0x20 #define AUD_HB1 0x21 #define AUD_HB2 0x22 #define AUD_PB0 0x23 #define AUD_PB1 0x24 #define AUD_PB2 0x25 #define AUD_PB3 0x26 #define AUD_PB4 0x27 #define AUD_PB5 0x28 #define AUD_PB6 0x29 #define AUD_PB7 0x2A #define AUD_PB8 0x2B #define AUD_PB9 0x2C #define AUD_PB10 0x2D #define SPD_HBO 0x40 #define SPD_HB1 0x41 #define SPD_HB2 0x42 #define SPD_PB0 0x43 #define SPD_PB1 0x44 #define SPD_PB2 0x45 #define SPD_PB3 0x46 #define SPD_PB4 0x47 #define SPD_PB5 0x48 #define SPD_PB6 0x49 #define SPD_PB7 0x4A #define SPD_PB8 0x4B #define SPD_PB9 0x4C #define SPD_PB10 0x4D #define SPD_PB11 0x4E #define SPD_PB12 0x4F #define SPD_PB13 0x50 #define SPD_PB14 0x51 #define SPD_PB15 0x52 #define SPD_PB16 0x53 #define SPD_PB17 0x54 #define SPD_PB18 0x55 #define SPD_PB19 0x56 #define SPD_PB20 0x57 #define SPD_PB21 0x58 #define SPD_PB22 0x59 #define SPD_PB23 0x5A #define SPD_PB24 0x5B #define SPD_PB25 0x5C #define SPD_PB26 0x5D #define SPD_PB27 0x5E #define MPEG_HBO 0x60 #define MPEG_HB1 0x61 #define MPEG_HB2 0x62 #define MPEG_PB0 0x63 #define MPEG_PB1 0x64 #define MPEG_PB2 0x65 #define MPEG_PB3 0x66 #define MPEG_PB4 0x67 #define MPEG_PB5 0x68 #define MPEG_PB6 0x69 #define MPEG_PB7 0x6A #define MPEG_PB8 0x6B #define MPEG_PB9 0x6C #define MPEG_PB10 0x6D #define MPEG_PB11 0x6E #define MPEG_PB12 0x6F #define MPEG_PB13 0x70 #define MPEG_PB14 0x71 #define MPEG_PB15 0x72 #define MPEG_PB16 0x73 #define MPEG_PB17 0x74 #define MPEG_PB18 0x75 #define MPEG_PB19 0x76 #define MPEG_PB20 0x77 #define MPEG_PB21 0x78 #define MPEG_PB22 0x79 #define MPEG_PB23 0x7A #define MPEG_PB24 0x7B #define MPEG_PB25 0x7C #define MPEG_PB26 0x7D #define MPEG_PB27 0x7E #define USRDF0_HBO 0x80 #define USRDF0_HB1 0x81 #define USRDF0_HB2 0x82 #define USRDF0_PB0 0x83 #define USRDF0_PB1 0x84 #define USRDF0_PB2 0x85 #define USRDF0_PB3 0x86 #define USRDF0_PB4 0x87 #define USRDF0_PB5 0x88 #define USRDF0_PB6 0x89 #define USRDF0_PB7 0x8A #define USRDF0_PB8 0x8B #define USRDF0_PB9 0x8C #define USRDF0_PB10 0x8D #define USRDF0_PB11 0x8E #define USRDF0_PB12 0x8F #define USRDF0_PB13 0x90 #define USRDF0_PB14 0x91 #define USRDF0_PB15 0x92 #define USRDF0_PB16 0x93 #define USRDF0_PB17 0x94 #define USRDF0_PB18 0x95 #define USRDF0_PB19 0x96 #define USRDF0_PB20 0x97 #define USRDF0_PB21 0x98 #define USRDF0_PB22 0x99 #define USRDF0_PB23 0x9A #define USRDF0_PB24 0x9B #define USRDF0_PB25 0x9C #define USRDF0_PB26 0x9D #define USRDF0_PB27 0x9E #define USRDF1_HBO 0xA0 #define USRDF1_HB1 0xA1 #define USRDF1_HB2 0xA2 #define USRDF1_PB0 0xA3 #define USRDF1_PB1 0xA4 #define USRDF1_PB2 0xA5 #define USRDF1_PB3 0xA6 #define USRDF1_PB4 0xA7 #define USRDF1_PB5 0xA8 #define USRDF1_PB6 0xA9 #define USRDF1_PB7 0xAA #define USRDF1_PB8 0xAB #define USRDF1_PB9 0xAC #define USRDF1_PB10 0xAD #define USRDF1_PB11 0xAE #define USRDF1_PB12 0xAF #define USRDF1_PB13 0xB0 #define USRDF1_PB14 0xB1 #define USRDF1_PB15 0xB2 #define USRDF1_PB16 0xB3 #define USRDF1_PB17 0xB4 #define USRDF1_PB18 0xB5 #define USRDF1_PB19 0xB6 #define USRDF1_PB20 0xB7 #define USRDF1_PB21 0xB8 #define USRDF1_PB22 0xB9 #define USRDF1_PB23 0xBA #define USRDF1_PB24 0xBB #define USRDF1_PB25 0xBC #define USRDF1_PB26 0xBD #define USRDF1_PB27 0xBE #define init_timer_slot() do { timer_slot = 0; } while (0) void HDMI_TX_Timer_Process (); void HDMI_TX_Config_Video(void); void HDMI_TX_Parse_Video_Format(void); void HDMI_TX_Get_Video_Timing(void); void HDMI_TX_DE_Generator(void); void HDMI_TX_Embed_Sync_Decode(void); void HDMI_TX_Show_Video_Parameter(void); void HDMI_TX_Clean_HDCP(void); BYTE HDMI_TX_Config_Packet(); BYTE HDMI_TX_Load_Infoframe(packet_type member, infoframe_struct *p); BYTE HDMI_TX_Checksum(infoframe_struct *p); BYTE HDMI_TX_Config_Audio(); BYTE HDMI_TX_Config_I2s(); BYTE HDMI_TX_Config_Spdif(); BYTE HDMI_TX_Config_Super_Audio(); void HDMI_TX_HDCP_Process(void); void HDMI_TX_PLAYBACK_Process(void); void HDMI_TX_Timer_Slot1(void); void HDMI_TX_Timer_Slot2(void); void HDMI_TX_Timer_Slot3(void); void HDMI_TX_Timer_Slot4(void); void HDMI_TX_Hotplug_Change_Interrupt(void); void HDMI_TX_Variable_Initial(void); void HDMI_TX_HW_Interface_Variable_Initial(); //void HDMI_TX_Config_Bist_Video(WORD bist_select_number); //** void HDMI_TX_Config_Clock_Generator_Frequency(WORD bist_select_number); void HDMI_TX_Video_Format_Change_Interrupt(void); void HDMI_TX_Video_Clock_Change_Interrupt(void); void HDMI_TX_Audio_CLK_Change_Interrupt(void); void HDMI_TX_Set_AVMute(void); void HDMI_TX_Clear_AVMute(void); BYTE HDMI_TX_BKSV_SRM(void); void HDMI_TX_Auth_Done_Interrupt(void); void HDMI_TX_Auth_Change_Interrupt(void); void HDMI_TX_Blue_Screen_Format_Config(void); void HDMI_TX_Blue_Screen_Enable(void); void HDMI_TX_Blue_Screen_Disable(void); void HDMI_TX_HDCP_Encryption_Enable(void); void HDMI_TX_HDCP_Encryption_Disable(void); void HDMI_TX_AFIFO_Overrun_Interrupt(void); void HDMI_TX_PllLock_Interrupt(void); //void HDMI_TX_Rx_Sense_Interrupt(void); void HDMI_TX_SPDIF_Error_Interrupt(BYTE int1, BYTE int3); void HDMI_TX_RST_DDCChannel(void); void HDMI_TX_Hardware_HDCP_Auth_Init(void); void HDMI_TX_Hardware_Reset(void); void HDMI_TX_Set_System_State(BYTE ss); void HDMI_TX_Hardware_Initial(void); void HDMI_TX_API_Initial(void); void HDMI_TX_Interrupt_Process(void); void HDMI_TX_Interrupt_Information(BYTE c, BYTE n); BYTE HDMI_TX_Parse_EDID(void); void HDMI_TX_Read_EDID(void); BYTE HDMI_TX_Parse_EDIDHeader(void); BYTE HDMI_TX_Parse_EDIDVersion(void); void HDMI_TX_Parse_DTD(void); //void HDMI_TX_Parse_BasicDis(void); void HDMI_TX_Parse_VendorSTD(void); void HDMI_TX_Parse_SpeakerSTD(void); void HDMI_TX_Parse_VideoSTD(void); void HDMI_TX_Parse_AudioSTD(void); void HDMI_TX_Parse_STD(void); void HDMI_TX_Parse_NativeFormat(void); void HDMI_TX_Parse_DTDinBlockONE(void); void HDMI_TX_Parse_DTDinExtBlock(void); BYTE HDMI_TX_Parse_ExtBlock(void); void HDMI_TX_GetEDIDLength(void); void HDMI_TX_EDID_Parsing_Result(void); BYTE HDMI_TX_EDID_Checksum(BYTE block_number) ; void HDMI_TX_InitDDC_Read(BYTE devaddr, BYTE segmentpointer,BYTE offset, BYTE access_num_Low,BYTE access_num_high); BYTE HDMI_TX_Read_RealEDID_BYTE(BYTE segmentpointer,BYTE offset); BYTE HDMI_TX_Read_EDID_BYTE(BYTE segmentpointer,BYTE offset); void HDMI_TX_DDC_Mass_Read(WORD length, BYTE *buf); //void Write_data_to_EE(); void HDMI_TX_Config_Auto_Video_Format(void); void HDMI_TX_Config_Manual_Video_Format(WORD bist_select_number); #if BIST_MODE_USED void HDMI_TX_BIST(); #endif void HDMI_TX_Config_Clock_Generator_Frequency(WORD bist_select_number); //void HDMI_TX_Config_Bist_Video_RefreshF(BYTE switch_value); void HDMI_TX_Reset_AVI(void) ; void HDMI_TX_Reset_BIST_Setting(void) ; void HDMI_TX_Config_Bist_Video(WORD bist_select_number); BYTE HDMI_TX_IS_KSVList_VLD(void); //void HDMI_TX_IS_KSVFIFO_Ready(void); BYTE HDMI_TX_Check_KSV_SRM(void); void HDMI_TX_Task(); void HDMI_TX_BIST_Task(void); void HDMI_TX_PLLFilter_Reset(void); void HDMI_TX_MuteTMDS_CLK(void); //void HDMI_TX_InitDDC_Write(BYTE devaddr, BYTE segmentpointer, // BYTE offset, BYTE access_num_Low,BYTE access_num_high); void HDMI_TX_HW_Vid_Testing(void); void HDMI_TX_CSCandColorDepth_Setting(void); void HDMI_TX_RepeatTimes_Setting(void); void HDMI_TX_Video_Interface_HW_Setting(void); #if (HDMI_TX_USE_NATIVE_CODE) void HDMI_RPT_Set_BCAPS_Repeater(BIT is_repeater); void HDMI_RPT_Set_KSVList_Init(BYTE start_addr,BYTE length); void HDMI_RPT_Set_BSTATUS1(BYTE bstatus1); void HDMI_RPT_Set_BSTATUS2(BYTE bstatus2); void HDMI_RPT_Set_SHA_Calc_Start(void); BIT HDMI_RPT_Get_SHA_Ready(void); void HDMI_RPT_Set_BCAPS_Ready(BIT ready); DS_BOOL HDMI_TX_GetCorrectMuteState(DS_BOOL mute); BYTE HDMI_TX_Get_System_State(void); //void HDMI_RPT_Get_KSV(void); #endif #endif