source: svn/trunk/zas_dstar/devices/includes/HDMI_TX_DRV.h @ 2

Last change on this file since 2 was 2, checked in by phkim, 11 years ago

1.phkim

  1. revision copy newcon3sk r27
File size: 52.5 KB
Line 
1//  ANALOGIX Company
2//  HDMI_TX Demo Firmware on SST
3
4
5#ifndef _HDMI_TX_Sys_H
6#define _HDMI_TX_Sys_H
7
8#define HDMI_TX_FW_VER 1.01
9
10typedef unsigned char BYTE;
11typedef unsigned char BIT;
12typedef unsigned short WORD;
13
14extern BYTE timer_slot,misc_reset_needed;
15extern BYTE bist_switch_value_pc,switch_value;
16extern BYTE switch_value_sw_backup,switch_value_pc_backup;
17extern BYTE HDMI_TX_system_state;
18extern BIT hdmi_tx_srm_checked;
19extern BIT hdmi_tx_HDCP_enable;
20
21extern BYTE FREQ_MCLK;
22
23struct Video_Timing {
24    //BYTE number;
25    WORD h_total_length;
26    WORD h_active_length;
27    WORD v_total_length;
28    WORD v_active_length;
29    WORD h_front_porch;
30    WORD h_sync_width;
31    WORD h_back_porch;
32    BYTE v_front_porch;
33    BYTE v_sync_width;
34    BYTE v_back_porch;
35    BYTE h_sync_polarity;
36    BYTE v_sync_polarity;
37    BYTE is_interlaced;
38    BYTE video_mode;
39};
40
41typedef struct 
42{
43    BYTE is_HDMI;
44    BYTE ycbcr444_supported;
45    BYTE ycbcr422_supported;
46    BYTE supported_1080p_60Hz;
47    BYTE supported_1080p_50Hz;
48    BYTE supported_1080i_60Hz;
49    BYTE supported_1080i_50Hz;
50    BYTE supported_720p_60Hz;
51    BYTE supported_720p_50Hz;
52    BYTE supported_576p_50Hz;
53    BYTE supported_576i_50Hz;
54    BYTE supported_640x480p_60Hz;
55    BYTE supported_720x480p_60Hz;
56    BYTE supported_720x480i_60Hz;
57    BYTE AudioFormat[10];//MAX audio STD block is 10(0x1f / 3)
58    BYTE AudioChannel[10];
59    BYTE AudioFs[10];
60    BYTE AudioLength[10];
61    BYTE SpeakerFormat;
62    BYTE edid_errcode;
63    BYTE RGB30bit;
64    BYTE RGB36bit;
65    BYTE RGB48bit;
66    BYTE DC_Y444;
67
68    }hdmi_tx_edid_result_4_system;
69    extern hdmi_tx_edid_result_4_system hdmi_tx_edid_result;
70
71// 8 type of packets are legal, It is possible to sent 6 types in the same time;
72// So select 6 types below at most;
73// avi_infoframe and audio_infoframe have fixxed address;
74// config other selected types of packet to the rest 4 address with no limits.
75typedef enum
76{
77    HDMI_TX_avi_infoframe,
78    HDMI_TX_audio_infoframe,
79    HDMI_TX_spd_infoframe,
80    HDMI_TX_mpeg_infoframe,
81    HDMI_TX_acp_packet,
82    HDMI_TX_isrc1_packet,
83    HDMI_TX_isrc2_packet,
84    HDMI_TX_vendor_infoframe
85}packet_type;
86
87typedef struct
88{
89    unsigned char type;
90    unsigned char version; 
91    unsigned char length;
92    unsigned char pb_byte[28];   
93}infoframe_struct;
94
95typedef struct
96{
97    BYTE packets_need_config;    //which infoframe packet is need updated
98    infoframe_struct avi_info;
99    infoframe_struct audio_info;   
100    infoframe_struct spd_info;
101    infoframe_struct mpeg_info;
102    infoframe_struct acp_pkt;
103    infoframe_struct isrc1_pkt;
104    infoframe_struct isrc2_pkt;
105    infoframe_struct vendor_info; 
106   
107} config_packets;
108/*
109    BYTE i2s_format;
110
111    Bit(s)      Name    Type    Default         Description
112    7   EXT_VUCP        R/W             0x0     
113            Enable indicator of VUCP BITs extraction from input
114            I2S audio stream. 0 = disable; 1 = enable.
115    6:5 MCLK_PHS_CTRL   R/W         0x0
116            MCLK phase control for audio SPDIF input, which value
117            is depended on the value of MCLK frequency set and not great than it.
118    4   Reserved                       
119    3   SHIFT_CTRL      R/W     0x0     
120            WS to SD shift first BIT. 0 = fist BIT shift (Philips Spec); 1 = no shift.
121    2   DIR_CTRL        R/W         0x0
122            SD data Indian (MSB or LSB first) control. 0 = MSB first; 1 = LSB first.
123    1   WS_POL      R/W         0x0     
124            Word select left/right polarity select. 0 = left polarity
125            when works select is low; 1 = left polarity when word select is high.
126    0   JUST_CTRL       R/W     0x0     
127            SD Justification control. 1 = data is right justified;
128            0 = data is left justified.
129
130*/
131/*
132    BYTE audio_channel
133Bit(s)  Name    Type Default    Description   
1345       AUD_SD3_IN      R/W     0x0     Set I2S input channel #3 enable. 0 = disable; 1 = enable.
1354       AUD_SD2_IN      R/W     0x0     Set I2S input channel #2 enable. 0 = disable; 1 = enable.
1363       AUD_SD1_IN      R/W     0x0     Set I2S input channel #1 enable. 0 = disable; 1 = enable.
1372       AUD_SD0_IN      R/W     0x0     Set I2S input channel #0 enable. 0 = disable; 1 = enable.
138
139
140*/
141/*
142    BYTE i2s_map0
143Bit(s)  Name    Type    Default         Description
1447:6     FIFO3_SEL       R/W     0x3     I2S Channel data stream select for audio FIFO 3. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;
1455:4     FIFO2_SEL       R/W     0x2     I2S Channel data stream select for audio FIFO 2. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;
1463:2     FIFO1_SEL       R/W     0x1     I2S Channel data stream select for audio FIFO 1. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;
1471:0     FIFO0_SEL       R/W     0x0     I2S Channel data stream select for audio FIFO 0. 0 = SD 0; 1 = SD 1; 2 = SD 2; 3 = SD 3;
148
149    BYTE i2s_map1
150Bit(s)  Name    Type    Default         Description
1517       SW3     R/W     0x0     Swap left/right channel on I2S channel 3. 1 = swap; 0 = no swap.
1526       SW2     R/W     0x0     Swap left/right channel on I2S channel 2. 1 = swap; 0 = no swap.
1535       SW1     R/W     0x0     Swap left/right channel on I2S channel 1. 1 = swap; 0 = no swap.
1544       SW0     R/W     0x0     Swap left/right channel on I2S channel 0. 1 = swap; 0 = no swap.
1553:1     IN_WORD_LEN     R/W     0x5     Input I2S audio word length (corresponding to channel status BITs [35:33]).  When IN_WORD_MAX = 0, 001 = 16 BITs; 010 = 18 BITs; 100 = 19 BITs; 101 = 20 BITs; 110 = 17 BITs; when IN_WORD_MAX = 1, 001 = 20 BITs; 010 = 22 BITs; 100 = 23 BITs; 101 = 24 BITs; 110 = 21 BITs.
1560       IN_WORD_MAX     R/W     0x1     Input I2S audio word length Max (corresponding to channel status BITs 32). 0 = maximal word length is 20 BITs; 1 = maximal word length is 24 BITs.
157*/
158/*
159    BYTE Channel_status1
160Bit(s)  Name    Type    Default         Description
1617:6     MODE    R/W     0x0     00 = PCM Audio
1625:3     PCM_MODE        R/W     0x0     000 = 2 audio channels without pre-emphasis;
163                        001 = 2 audio channels with 50/15 usec pre-emphasis
1642       SW_CPRGT        R/W     0x0     0 = software for which copyright is asserted;
165                        1 = software for which no copyright is asserted
1661       NON_PCM R/W     0x0     0 = audio sample word represents linear PCM samples;
167                    1 = audio sample word used for other purposes.
1680       PROF_APP        R/W     0x0     0 = consumer applications; 1 = professional applications.
169
170    BYTE Channel_status2
171Bit(s)  Name    Type    Default         Description
1727:0     CAT_CODE        R/W     0x0     Category code (corresponding to channel status BITs [15:8])
173
174    BYTE Channel_status3
175Bit(s)  Name    Type    Default         Description
1767:4     CH_NUM  R/W     0x0     Channel number (corresponding to channel status BITs [23:20])
1773:0     SOURCE_NUM      R/W     0x0     Source number (corresponding to channel status BITs [19:16])
178
179    BYTE Channel_status4
180Bit(s)  Name    Type    Default         Description
1817:6     CHNL_BIT1       R/W     0x0     corresponding to channels status BITs [31:30]
1825:4     CLK_ACCUR       R/W     0x0     Clock accuracy (corresponding to channels status BITs [29:28]). These two BITs define the sampling frequency tolerance. The BITs are set in the transmitter.
1833:0     FS_FREQ R/W     0x0     Sampling clock frequency (corresponding to channel status BITs [27:24]). 0000 = 44.1 KHz; 0010 = 48 KHz; 0011 = 32 KHz; 1000 = 88.2 KHz; 1010 = 96 KHz; 176.4 KHz; 1110 = 192 KHz; others = reserved.
184
185    BYTE Channel_status5
186Bit(s)  Name    Type    Default         Description
1877:4     CHNL_BIT2       R/W     0x0     corresponding to channels status BITs [39:36]
1883:1     WORD_LENGTH     R/W     0x5     Audio word length (corresponding to channel status BITs [35:33]).  When WORD_MAX = 0, 001 = 16 BITs; 010 = 18 BITs; 100 = 19 BITs; 101 = 20 BITs; 110 = 17 BITs; when WORD_MAX = 1, 001 = 20 BITs; 010 = 22 BITs; 100 = 23 BITs; 101 = 24 BITs; 110 = 21 BITs.
1890       WORD_MAX        R/W     0x1     Audio word length Max (corresponding to channel status BITs 32). 0 = maximal word length is 20 BITs; 1 = maximal word length is 24 BITs.
190
191*/
192typedef struct
193{
194    BYTE audio_channel;
195    BYTE i2s_format;
196    BYTE i2s_swap;
197    BYTE Channel_status1;
198    BYTE Channel_status2;
199    BYTE Channel_status3;
200    BYTE Channel_status4;
201    BYTE Channel_status5;
202} i2s_config_struct;
203/*
204    BYTE FS_FREQ;
205
206    7:4 FS_FREQ R       0x0     
207        Sampling clock frequency (corresponding to channel status BITs [27:24]).
208        0000 = 44.1 KHz; 0010 = 48 KHz; 0011 = 32 KHz; 1000 = 88.2 KHz; 1010 = 96 KHz;
209        176.4 KHz; 1110 = 192 KHz; others = reserved.
210*/
211
212typedef struct
213{
214    BYTE one_BIT_ctrl;
215
216} super_audio_config_struct;
217
218typedef struct
219{
220    BYTE audio_type;            // audio type
221                                // #define HDMI_TX_i2s_input 0x01
222                                // #define HDMI_TX_spdif_input 0x02
223                                // #define HDMI_TX_super_audio_input 0x04
224
225    BYTE down_sample;     // 0x72:0x50
226                                // 0x00:    00  no down sample
227                                // 0x20:    01  2 to 1 down sample
228                                // 0x60:    11  4 to 1 down sample
229                                // 0x40:    10  reserved
230
231    i2s_config_struct i2s_config;
232    super_audio_config_struct super_audio_config;
233   
234} audio_config_struct;
235
236/*added by gerard.zhu*/
237/*DDC type*/
238typedef enum {
239    DDC_Hdcp,
240    DDC_Edid
241}Anx8560_DDC_Type;
242
243/*Read DDC status type*/
244typedef enum {
245    report,
246    Judge
247}Anx8560_DDC_Status_Check_Type;
248
249/*Define DDC address struction*/
250typedef struct {
251    BYTE dev_addr;
252    BYTE sgmt_addr;
253    BYTE offset_addr;
254}Anx8560_DDC_Addr;
255
256/*DDC status bit*/
257#define DDC_Error_bit   0x07
258#define DDC_Occup_bit  0x06
259#define DDC_Fifo_Full_bit  0x05
260#define DDC_Fifo_Empt_bit  0x04
261#define DDC_No_Ack_bit 0x03
262#define DDC_Fifo_Rd_bit    0x02
263#define DDC_Fifo_Wr_bit    0x01
264#define DDC_Progress_bit   0x00
265
266#define YCbCr422 0x20
267#define null 0
268#define source_ratio 0x08
269
270/*DDC Command*/
271#define Abort_Current_Operation 0x00
272#define Sequential_Byte_Read 0x01
273#define Sequential_Byte_Write 0x02
274#define Implicit_Offset_Address_Read 0x3
275#define Enhanced_DDC_Sequenital_Read 0x04
276#define Clear_DDC_Fifo 0x05
277#define I2c_reset 0x06
278
279/*DDC result*/
280#define DDC_NO_Err 0x00
281#define DDC_Status_Err 0x01
282#define DDC_Data_Addr_Err 0x02
283#define DDC_Length_Err  0x03
284
285/*checksum result*/
286#define Edid_Checksum_No_Err     0x00
287#define Edid_Checksum_Err   0x01
288
289/*HDCP device base address*/
290#define HDCP_Dev_Addr   0x74
291
292/*HDCP Bksv offset*/
293#define HDCP_Bksv_Offset 0x00
294
295/*HDCP Bcaps offset*/
296#define HDCP_Bcaps_Offset   0x40
297
298/*HDCP Bstatus offset*/
299#define HDCP_Bstatus_offset     0x41
300
301/*HDCP KSV Fifo offset */
302#define HDCP_Ksv_Fifo_Offset    0x43
303
304/*HDCP bksv data nums*/
305#define Bksv_Data_Nums  5
306
307/*HDCP ksvs data number by defult*/
308#define ksvs_data_nums 50
309
310/*DDC Max bytes*/
311#define DDC_Max_Length 1024
312
313/*DDC fifo depth*/
314#define DDC_Fifo_Depth  16
315
316/*DDC read delay ms*/
317#define DDC_Read_Delay 3
318
319/*DDC Write delay ms*/
320#define DDC_Write_Delay 3
321/*end*/
322
323extern BIT hdmi_tx_parse_edid_done;
324extern BIT hdmi_tx_system_config_video_done,hdmi_tx_system_config_audio_done,hdmi_tx_system_config_gamut_data_done;
325extern BYTE hdmi_tx_video_format_config,hdmi_tx_video_timing_id;
326extern BIT hdmi_tx_new_csc,hdmi_tx_new_vid_id,hdmi_tx_new_HW_interface;
327extern BIT hdmi_tx_ddr_edge;
328extern BYTE hdmi_tx_in_pix_rpt_bkp,hdmi_tx_tx_pix_rpt_bkp;
329extern BYTE hdmi_tx_in_pix_rpt,hdmi_tx_tx_pix_rpt;
330extern BIT hdmi_tx_pix_rpt_set_by_sys;
331extern BYTE hdmi_tx_RGBorYCbCr;
332extern audio_config_struct s_hdmi_tx_audio_config;
333extern config_packets s_hdmi_tx_packet_config;
334extern BIT hdmi_tx_app_hold_video_config,hdmi_tx_app_hold_audio_config;
335extern BIT hdmi_tx_shutdown;
336//********************** BIST Enable***********************************
337#define BIST_MODE_USED 1
338#define HDMI_RX_USED 0
339#define HDMI_TX_CLK_SOURCE 1
340#define BIST_EN g_BIST_OnOff
341#define BIST_MODE3 ((g_BIST_Resolution >> 3) & 0x01)
342#define BIST_MODE2 ((g_BIST_Resolution >> 2) & 0x01)
343#define BIST_MODE1 ((g_BIST_Resolution >> 1) & 0x01)
344#define BIST_MODE0 ((g_BIST_Resolution >> 0) & 0x01)
345#define HDMI_TX_USE_NATIVE_CODE 1
346#define rpt_auto_setting 0
347#define rpt_manual_setting 1
348#define ddr_falling_edge 1
349#define ddr_rising_edge 0
350
351#define input_pixel_clk_1x_repeatition 0x00
352#define input_pixel_clk_2x_repeatition 0x01
353#define input_pixel_clk_4x_repeatition 0x03
354
355//***********************Video Config***********************************
356#define hdmi_tx_RGB_YCrCb444_SepSync 0
357#define hdmi_tx_YCrCb422_SepSync 1
358#define hdmi_tx_YCrCb422_EmbSync 2
359#define hdmi_tx_YCMux422_SepSync_Mode1 3
360#define hdmi_tx_YCMux422_SepSync_Mode2 4
361#define hdmi_tx_YCMux422_EmbSync_Mode1 5
362#define hdmi_tx_YCMux422_EmbSync_Mode2 6
363#define hdmi_tx_YCMux422_EmbSync_Mode3 12
364#define hdmi_tx_YCMux422_SepSync_Mode3 11
365#define hdmi_tx_RGB_YCrCb444_DDR_SepSync 7
366#define hdmi_tx_RGB_YCrCb444_DDR_EmbSync 8
367
368#define hdmi_tx_RGB_YCrCb444_SepSync_No_DE 9
369#define hdmi_tx_YCrCb422_SepSync_No_DE 10
370
371#define hdmi_tx_Progressive 0
372#define hdmi_tx_Interlace 0x08
373#define hdmi_tx_Neg_Hsync_pol 0x20
374#define hdmi_tx_Pos_Hsync_pol 0
375#define hdmi_tx_Neg_Vsync_pol 0x40
376#define hdmi_tx_Pos_Vsync_pol 0
377
378//Use for digital video output fomat   
379#define RGB444 0x00
380#define RGB444_CLK48B 0x80
381#define YCbCr444 0x01
382#define YCbCr444_CLK48B 0x81
383#define YCbCR422 0x03
384#define YCbCr422_656 0x0b
385#define YCbCr422_YCMUX 0x07
386#define YCbCr422_656_YCMUX 0x0f
387
388#define HDMI_TX_RGB 0x00
389#define HDMI_TX_YCbCr422 0x01
390#define HDMI_TX_YCbCr444 0x02
391#define HDMI_TX_CSC_BT709 1
392#define HDMI_TX_CSC_BT601 0
393
394#define HDMI_TX_EMBEDED_BLUE_SCREEN_ENABLE 1
395#define HDMI_TX_HDCP_FAIL_THRESHOLD 3
396
397#define HDMI_TX_avi_sel 0x01
398#define HDMI_TX_audio_sel 0x02
399#define HDMI_TX_spd_sel 0x04
400#define HDMI_TX_mpeg_sel 0x08
401#define HDMI_TX_acp_sel 0x10
402#define HDMI_TX_isrc1_sel 0x20
403#define HDMI_TX_isrc2_sel 0x40
404#define HDMI_TX_vendor_sel 0x80
405
406#define sim
407// audio type
408#define HDMI_TX_i2s_input 0x01
409#define HDMI_TX_spdif_input 0x02
410#define HDMI_TX_super_audio_input 0x04
411// freq_mclk
412#define HDMI_TX_mclk_128_Fs 0x00
413#define HDMI_TX_mclk_256_Fs 0x01
414#define HDMI_TX_mclk_384_Fs 0x02
415#define HDMI_TX_mclk_512_Fs 0x03
416// thresholds
417#define HDMI_TX_spdif_stable_th 0x03
418// fs -> N(ACR)
419#define HDMI_TX_N_32k 0x1000
420#define HDMI_TX_N_44k 0x1880
421#define HDMI_TX_N_88k 0x3100
422#define HDMI_TX_N_176k 0x6200
423#define HDMI_TX_N_48k 0x1800
424#define HDMI_TX_N_96k 0x3000
425#define HDMI_TX_N_192k 0x6000
426
427#define HDMI_TX_INITIAL 0x01
428#define HDMI_TX_WAIT_HOTPLUG 0x02
429#define HDMI_TX_READ_PARSE_EDID 0x03
430//#define HDMI_TX_WAIT_RX_SENSE 0x04
431#define HDMI_TX_CONFIG_VIDEO 0x05
432#define HDMI_TX_CONFIG_AUDIO 0x07
433#define HDMI_TX_CONFIG_PACKETS 0x08
434#define HDMI_TX_HDCP_AUTHENTICATION 0x06
435#define HDMI_TX_PLAY_BACK 0x09
436#define HDMI_TX_RESET_LINK 0x0a
437
438#define spdif_error_th 0x0a
439
440#define Hresolution_1920 1920
441#define Vresolution_540 540
442#define Vresolution_1080 1080
443#define Hresolution_1280 1280
444#define Vresolution_720 720
445#define Hresolution_640 640
446#define Vresolution_480 480
447#define Hresolution_720 720
448#define Vresolution_240 240
449#define Vresolution_576 576
450#define Vresolution_288 288
451#define Hz_50 50
452#define Hz_60 60
453#define Interlace_EDID 0
454#define Progressive_EDID 1
455#define ratio_16_9 1.777778
456#define ratio_4_3 1.333333
457
458#define HDMI_TX_EDID_BadHeader 0x01;
459#define HDMI_TX_EDID_861B_not_supported 0x02;
460#define HDMI_TX_EDID_CheckSum_ERR 0x03;
461#define HDMI_TX_EDID_No_ExtBlock 0x04;
462#define HDMI_TX_EDID_ExtBlock_NotFor_861B 0x05;
463
464
465
466//Reg difine
467
468// DEV_ADDR = 0x72 or 0x76
469#define HDMI_TX_VND_IDL_REG 0x00
470#define HDMI_TX_VND_IDH_REG 0x01
471#define HDMI_TX_DEV_IDL_REG 0x02
472#define HDMI_TX_DEV_IDH_REG 0x03
473#define HDMI_TX_DEV_REV_REG 0x04
474
475#define HDMI_TX_SRST_REG 0x05
476#define HDMI_TX_SRST_MISC_TXPLL_RST 0x80
477#define HDMI_TX_TMDS_CHNL_ALIGN 0x40
478#define HDMI_TX_SRST_VIDCAP_RST         0x20    // bit position
479#define HDMI_TX_SRST_AFIFO_RST           0x10   // bit position
480#define HDMI_TX_SRST_HDCP_RST                   0x08    // bit position
481#define HDMI_TX_SRST_VID_FIFO_RST                0x04   // bit position
482#define HDMI_TX_SRST_AUD_RST             0x02   // bit position
483#define HDMI_TX_SRST_SW_RST                      0x01   // bit position
484
485#define HDMI_TX_SYS_STATE_REG 0x06
486#define HDMI_TX_SYS_STATE_PLLF_MISC_LOCK                0x80
487#define HDMI_TX_SYS_STATE_TXPLL_MISC_LOCK       0x40
488#define HDMI_TX_SYS_STATE_AUD_CLK_DET           0x20    // bit position
489#define HDMI_TX_SYS_STATE_AVMUTE                 0x10   // bit position
490#define HDMI_TX_SYS_STATE_HP                     0x08   // bit position
491#define HDMI_TX_SYS_STATE_VSYNC                          0x04   // bit position
492#define HDMI_TX_SYS_STATE_CLK_DET                        0x02   // bit position
493#define HDMI_TX_SYS_STATE_RSV_DET                        0x01   // bit position
494
495#define HDMI_TX_SYS_CTRL1_REG 0x07
496#define HDMI_TX_SYS_CTRL1_LINKMUTE_EN           0x80    // bit position
497#define HDMI_TX_SYS_CTRL1_HDCPHPD_RST            0x40   // bit position
498#define HDMI_TX_SYS_CTRL1_PDINT_SEL              0x20   // bit position
499#define HDMI_TX_SYS_CTRL1_DDC_FAST                       0x10   // bit position
500#define HDMI_TX_SYS_CTRL1_DDC_SWCTRL            0x08    // bit position
501#define HDMI_TX_SYS_CTRL1_HDCPMODE               0x04   // bit position
502#define HDMI_TX_SYS_CTRL1_HDMI                           0x02   // bit position
503#define HDMI_TX_SYS_CTRL1_PWDN_CTRL             0x01    // bit position
504
505#define HDMI_TX_SYS_CTRL2_REG 0x08
506#define HDMI_TX_SYS_CTRL2_DDC_RST                         0x08  // bit position
507#define HDMI_TX_SYS_CTRL2_TMDSBIST_RST    0x04  // bit position
508#define HDMI_TX_SYS_CTRL2_MISC_RST                        0x02  // bit position
509#define HDMI_TX_SYS_CTRL2_HW_RST                          0x01  // bit position
510
511#define HDMI_TX_SYS_CTRL3_REG           0x09
512#define HDMI_TX_SYS_CTRL3_PD_MACRO_ALL  0x04    // bit position
513#define HDMI_TX_SYS_CTRL3_I2C_PWON      0x02    // bit position
514#define HDMI_TX_SYS_CTRL3_PWON_ALL      0x01    // bit position
515
516#define HDMI_TX_SYS_CTRL4_REG           0x0A
517#define HDMI_TX_SYS_CTRL4_VID_BIT_CTRL_SHR      0x80    // bit position
518#define HDMI_TX_SYS_CTRL4_VH_SYNC_ALIGN_EN      0x04    // bit position
519#define HDMI_TX_SYS_CTRL4_AUD_MUTE      0x02    // bit position
520#define HDMI_TX_SYS_CTRL4_VID_MUTE      0x01    // bit position
521
522#define HDMI_TX_VID_STATUS_REG 0x10
523#define HDMI_TX_VID_STATUS_VID_STABLE            0x20   // bit position
524#define HDMI_TX_VID_STATUS_EMSYNC_ERR           0x10    // bit position
525#define HDMI_TX_VID_STATUS_FLD_POL                       0x08   // bit position
526#define HDMI_TX_VID_STATUS_TYPE                  0x04   // bit position
527#define HDMI_TX_VID_STATUS_VSYNC_POL             0x02   // bit position
528#define HDMI_TX_VID_STATUS_HSYNC_POL            0x01    // bit position
529
530#define HDMI_TX_VID_MODE_REG 0x11
531#define HDMI_TX_VID_MODE_CHKSHARED_EN    0x80   // bit position
532#define HDMI_TX_VID_MODE_LINKVID_EN              0x40   // bit position
533#define HDMI_TX_VID_MODE_RANGE_Y2R               0x20   // bit position
534#define HDMI_TX_VID_MODE_CSPACE_Y2R             0x10    // bit position
535#define HDMI_TX_VID_MODE_CSC_MODE_SEL                    0x08   // bit position
536#define HDMI_TX_VID_MODE_UPSAMPLE                        0x04   // bit position
537
538#define HDMI_TX_VID_CTRL_REG  0x12
539#define HDMI_TX_VID_CTRL_IN_EN                   0x10   // bit position
540#define HDMI_TX_VID_CTRL_DEF_PHS_AUTORST_EN              0x08   // bit position
541#define HDMI_TX_VID_CTRL_BITCTRL_EN                     0x04    // bit position
542
543#define HDMI_TX_VID_CAPCTRL0_REG  0x13
544#define HDMI_TX_VID_CAPCTRL0_DEGEN_EN            0x80   // bit position
545#define HDMI_TX_VID_CAPCTRL0_EMSYNC_EN   0x40   // bit position
546#define HDMI_TX_VID_CAPCTRL0_DEMUX_EN            0x20   // bit position
547#define HDMI_TX_VID_CAPCTRL0_INV_IDCK           0x10    // bit position
548#define HDMI_TX_VID_CAPCTRL0_DV_BUSMODE  0x08   // bit position
549#define HDMI_TX_VID_CAPCTRL0_DDR_EDGE            0x04   // bit position
550#define HDMI_TX_VID_CAPCTRL0_VIDBIT_SWAP         0x02   // bit position
551#define HDMI_TX_VID_CAPCTRL0_VIDBIST_EN  0x01   // bit position
552       
553#define HDMI_TX_VID_CAPCTRL1_REG 0x14
554#define HDMI_TX_VID_CAPCTRL1_FORMAT_SEL          0x80   // bit position
555#define HDMI_TX_VID_CAPCTRL1_VSYNC_POL           0x40   // bit position
556#define HDMI_TX_VID_CAPCTRL1_HSYNC_POL           0x20   // bit position
557#define HDMI_TX_VID_CAPCTRL1_INV_ESYNC_FLDPOL           0x10    // bit position
558#define HDMI_TX_VID_CAPCTRL1_VID_TYPE                   0x08    // bit position
559
560#define HDMI_TX_H_RESL_REG 0x15
561#define HDMI_TX_H_RESH_REG 0x16
562#define HDMI_TX_VID_PIXL_REG 0x17
563#define HDMI_TX_VID_PIXH_REG 0x18
564#define HDMI_TX_H_FRONTPORCHL_REG 0x19
565#define HDMI_TX_H_FRONTPORCHH_REG 0x1A
566#define HDMI_TX_HSYNC_ACT_WIDTHL_REG 0x1B
567#define HDMI_TX_HSYNC_ACT_WIDTHH_REG 0x1C
568#define HDMI_TX_H_BACKPORCHL_REG 0x1D
569#define HDMI_TX_H_BACKPORCHH_REG 0x1E
570#define HDMI_TX_V_RESL_REG 0x1F
571#define HDMI_TX_V_RESH_REG 0x20
572#define HDMI_TX_ACT_LINEL_REG 0x21
573#define HDMI_TX_ACT_LINEH_REG 0x22
574#define HDMI_TX_ACT_LINE2VSYNC_REG 0x23
575#define HDMI_TX_VSYNC_WID_REG 0x24
576#define HDMI_TX_VSYNC_TAIL2VIDLINE_REG 0x25
577#define HDMI_TX_VIDF_HRESL_REG 0x26
578#define HDMI_TX_VIDF_HRESH_REG 0x27
579#define HDMI_TX_VIDF_PIXL_REG 0x28
580#define HDMI_TX_VIDF_PIXH_REG 0x29
581#define HDMI_TX_VIDF_HFORNTPORCHL_REG 0x2A
582#define HDMI_TX_VIDF_HFORNTPORCHH_REG 0x2B
583#define HDMI_TX_VIDF_HSYNCWIDL_REG 0x2C
584#define HDMI_TX_VIDF_HSYNCWIDH_REG 0x2D
585#define HDMI_TX_VIDF_HBACKPORCHL_REG 0x2E
586#define HDMI_TX_VIDF_HBACKPORCHH_REG 0x2F
587#define HDMI_TX_VIDF_VRESL_REG 0x30
588#define HDMI_TX_VIDF_VRESH_REG 0x31
589#define HDMI_TX_VIDF_ACTVIDLINEL_REG 0x32
590#define HDMI_TX_VIDF_ACTVIDLINEH_REG 0x33
591#define HDMI_TX_VIDF_ACTLINE2VSYNC_REG 0x34
592#define HDMI_TX_VIDF_VSYNCWIDLINE_REG 0x35
593#define HDMI_TX_VIDF_VSYNCTAIL2VIDLINE_REG 0x36
594
595#define HDMI_TX_VIDEO_MODE_REG  0x37
596#define HDMI_TX_VIDEO_MODE_DC_LINK_HRES_SEL             0x80    // bit position
597#define HDMI_TX_VIDEO_MODE_DC_DEFAULT_PHASE     0x40    // bit position
598#define HDMI_TX_VIDEO_MODE_XVYCC_RNG_LMT                0x20    // bit position
599#define HDMI_TX_VIDEO_MODE_RGB_RNG_LMT                  0x10    // bit position
600#define HDMI_TX_VIDEO_MODE_YC_RNG_LMT                   0x08    // bit position
601#define HDMI_TX_VIDEO_MODE_DOWN_SAMPLE                  0x04    // bit position
602#define HDMI_TX_VIDEO_MODE_RANGE_R2Y                    0x02    // bit position
603#define HDMI_TX_VIDEO_MODE_CSPACE_R2Y                   0x01    // bit position
604
605#define HDMI_TX_VID_CLK_FREQ_COUNTER                            0x38
606
607
608/*
609
610//Video input data bit control registers   
611
612//#define VID_BIT_CTRL0 0x37      //added
613#define VID_BIT_CTRL1 0x38
614#define VID_BIT_CTRL2 0x39
615#define VID_BIT_CTRL3 0x3A
616#define VID_BIT_CTRL4 0x3B
617#define VID_BIT_CTRL5 0x3C
618#define VID_BIT_CTRL6 0x3D
619#define VID_BIT_CTRL7 0x3E
620#define VID_BIT_CTRL8 0x3F
621#define VID_BIT_CTRL9 0x48
622#define VID_BIT_CTRL10 0x49
623#define VID_BIT_CTRL11 0x4A
624#define VID_BIT_CTRL12 0x4B
625#define VID_BIT_CTRL13 0x4C
626#define VID_BIT_CTRL14 0x4D
627#define VID_BIT_CTRL15 0x4E
628#define VID_BIT_CTRL16 0x4F
629#define VID_BIT_CTRL17 0x89
630#define VID_BIT_CTRL18 0x8A
631#define VID_BIT_CTRL19 0x8B
632#define VID_BIT_CTRL20 0x8C
633
634*/
635
636
637#define HDMI_TX_VID_CAP_CTRL2_REG                                               0x39
638#define HDMI_TX_VID_CAP_CTRL2_FRM_CHK_INV_FLD           0x80    // bit position
639#define HDMI_TX_VID_CAP_CTRL2_ADJ_V_INV_FLD                     0x40    // bit position
640#define HDMI_TX_VID_CAP_CTRL2_ADJ_VSYNC_EN                      0x02    // bit position
641#define HDMI_TX_VID_CAP_CTRL2_ADJ_VSYNC_VALUE           0x01    // bit position
642
643#define HDMI_TX_VID_CAP_CTRL3_REG                                               0x3A
644#define HDMI_TX_VID_CAP_CTRL3_VSYNC_FPOS_SIGN           0x80    // bit position
645
646#define HDMI_TX_LINK_FORMAT_LINES_OFFSET0_REG           0x3B
647#define HDMI_TX_LINK_FORMAT_LINES_OFFSET0_VSYNC_BPOS_SIGN0              0x80    // bit position
648#define HDMI_TX_LINK_FORMAT_LINES_OFFSET0_VSYNC_BPOS_SIGN1              0x08    // bit position
649
650#define HDMI_TX_LINK_FORMAT_LINES_OFFSET1_REG           0x3C
651#define HDMI_TX_LINK_FORMAT_LINES_OFFSET1_ACT_LINEOS_SIGN0              0x80    // bit position
652#define HDMI_TX_LINK_FORMAT_LINES_OFFSET1_ACT_LINEOS_SIGN1              0X08    // bit position
653
654#define HDMI_TX_VID_MODE2_REG           0x3D
655#define HDMI_TX_VID_MODE2_OUTPUT_LIMIT_EN               0x80    // bit position
656#define HDMI_TX_VID_MODE2_OUTPUT_LIMIT_RANGE    0x40    // bit position
657#define HDMI_TX_VID_MODE2_O_YC422                               0x20    // bit position
658#define HDMI_TX_VID_MODE2_O_YCBCR                               0x10    // bit position
659#define HDMI_TX_VID_MODE2_VID_US_MODE                   0x02    // bit position
660#define HDMI_TX_VID_MODE2_VID_DS_MODE                   0x01    // bit position
661
662#define HDMI_TX_VID_MODE3_REG           0x3E
663#define HDMI_TX_VID_MODE3_YC422_BUS_ADJ_EN              0x80
664#define HDMI_TX_VID_MODE3_BRU_EN                                        0x10
665#define HDMI_TX_VID_MODE3_BRU_RND_DIR                   0x02
666#define HDMI_TX_VID_MODE3_DE_DEALY                              0x01
667
668
669
670
671
672
673
674
675#define HDMI_TX_INTR_STATE_REG 0x40
676
677#define HDMI_TX_INTR_CTRL_REG 0x41
678#define HDMI_TX_INTR_CTRL_SOFT_INTR      0x04   // bit position
679#define HDMI_TX_INTR_CTRL_TYPE                   0x02   // bit position
680#define HDMI_TX_INTR_CTRL_POL                    0x01   // bit position
681
682#define HDMI_TX_INTR1_STATUS_REG 0x42
683#define HDMI_TX_INTR1_STATUS_CTS_CHG             0x80   // bit position
684#define HDMI_TX_INTR1_STATUS_AFIFO_UNDER         0x40   // bit position
685#define HDMI_TX_INTR1_STATUS_AFIFO_OVER  0x20   // bit position
686#define HDMI_TX_INTR1_STATUS_SPDIF_ERR          0x10    // bit position
687#define HDMI_TX_INTR1_STATUS_SW_INT             0x08    // bit position
688#define HDMI_TX_INTR1_STATUS_HP_CHG              0x04   // bit position
689#define HDMI_TX_INTR1_STATUS_CTS_OVRWR          0x02    // bit position
690#define HDMI_TX_INTR1_STATUS_CLK_CHG             0x01   // bit position
691
692#define HDMI_TX_INTR2_STATUS_REG 0x43
693#define HDMI_TX_INTR2_STATUS_ENCEN_CHG          0x80    // bit position
694#define HDMI_TX_INTR2_STATUS_HDCPLINK_CHK               0x40    // bit position
695#define HDMI_TX_INTR2_STATUS_HDCPENHC_CHK       0x20    // bit position
696#define HDMI_TX_INTR2_STATUS_BKSV_RDY                   0x10    // bit position
697#define HDMI_TX_INTR2_STATUS_PLLLOCK_CHG                0x08    // bit position
698#define HDMI_TX_INTR2_STATUS_SHA_DONE                    0x04   // bit position
699#define HDMI_TX_INTR2_STATUS_AUTH_CHG                   0x02    // bit position
700#define HDMI_TX_INTR2_STATUS_AUTH_DONE           0x01   // bit position
701
702#define HDMI_TX_INTR3_STATUS_REG 0x44
703#define HDMI_TX_INTR3_STATUS_SPDIFBI_ERR                0x80    // bit position
704#define HDMI_TX_INTR3_STATUS_VIDF_CHG                   0x40    // bit position
705#define HDMI_TX_INTR3_STATUS_AUDCLK_CHG                 0x20    // bit position
706#define HDMI_TX_INTR3_STATUS_DDCACC_ERR         0x10    // bit position
707#define HDMI_TX_INTR3_STATUS_DDC_NOACK          0x08    // bit position
708#define HDMI_TX_INTR3_STATUS_VSYNC_DET           0x04   // bit position
709#define HDMI_TX_INTR3_STATUS_RXSEN_CHG          0x02    // bit position
710#define HDMI_TX_INTR3_STATUS_SPDIF_UNSTBL                0x01   // bit position
711
712#define HDMI_TX_INTR1_MASK_REG 0x45
713#define HDMI_TX_INTR2_MASK_REG 0x46
714#define HDMI_TX_INTR3_MASK_REG 0x47
715
716#define HDMI_TX_INTR4_STATUS_REG        0x48
717#define HDMI_TX_INTR4_STATUS_DDC_FIFO_FULL      0x80    // bit position
718#define HDMI_TX_INTR4_STATUS_DDC_FIFO_EMPTY     0x40    // bit position
719#define HDMI_TX_INTR4_STATUS_DDC_FIFO_HALF      0x20    // bit position
720#define HDMI_TX_INTR4_STATUS_DDC_ACC_DONE       0x10    // bit position
721#define HDMI_TX_INTR4_STATUS_CEC_MSG_READY      0x08    // bit position
722#define HDMI_TX_INTR4_STATUS_CEC_TX_DONE        0x04    // bit position
723#define HDMI_TX_INTR4_STATUS_SAUD_STATIC_DET    0x02    // bit position
724#define HDMI_TX_INTR4_STATUS_SAUD_INVAL_DET             0x01    // bit position
725
726#define HDMI_TX_INTR5_STATUS_REG        0x49
727#define HDMI_TX_INTR5_STATUS_DEFAULT_PHASE_ERR          0x80    // bit position
728#define HDMI_TX_INTR5_STATUS_R0_CHK_FLAG                        0x40    // bit position
729#define HDMI_TX_INTR5_STATUS_LINK_CHK_TIMEOUT           0x20    // bit position
730#define HDMI_TX_INTR5_STATUS_RI_NO_UPDATE                       0x10    // bit position
731#define HDMI_TX_INTR5_STATUS_SYNC_PRE_CHK_FAIL          0x08    // bit position
732#define HDMI_TX_INTR5_STATUS_SYNC_POST_CHK_FAIL 0x04    // bit position
733#define HDMI_TX_INTR5_STATUS_HDCP_LNK_CHK_FAIL          0x02    // bit position
734#define HDMI_TX_INTR5_STATUS_HDCP_ENHC_CHK_FAIL 0x01    // bit position
735
736#define HDMI_TX_INTR4_MASK_REG 0x4A
737#define HDMI_TX_INTR5_MASK_REG 0x4B
738
739
740
741#define HDMI_TX_HDMI_AUDCTRL0_REG 0x50
742#define HDMI_TX_HDMI_AUDCTRL0_LAYOUT            0x80    // bit position
743#define HDMI_TX_HDMI_AUDCTRL0_DOWN_SMPL         0x60    // bit position
744#define HDMI_TX_HDMI_AUDCTRL0_CTSGEN_SC0                0x10    // bit position
745#define HDMI_TX_HDMI_AUDCTRL0_INV_AUDCLK                0x08    // bit position
746
747#define HDMI_TX_HDMI_AUDCTRL1_REG 0x51
748#define HDMI_TX_HDMI_AUDCTRL1_IN_EN                     0x80    // bit position
749#define HDMI_TX_HDMI_AUDCTRL1_SPDIFIN_EN                0x40    // bit position
750#define HDMI_TX_HDMI_AUDCTRL1_SD3IN_EN          0x20    // bit position
751#define HDMI_TX_HDMI_AUDCTRL1_SD2IN_EN          0x10    // bit position
752#define HDMI_TX_HDMI_AUDCTRL1_SD1IN_EN          0x08    // bit position
753#define HDMI_TX_HDMI_AUDCTRL1_SD0IN_EN           0x04   // bit position
754#define HDMI_TX_HDMI_AUDCTRL1_SPDIFFS_OVRWR     0x02    // bit position
755#define HDMI_TX_HDMI_AUDCTRL1_CLK_SEL0           0x01   // bit position
756
757#define HDMI_TX_I2S_CTRL_REG 0x52
758#define HDMI_TX_I2S_CTRL_VUCP                   0x80    // bit position
759#define HDMI_TX_I2S_CTRL_SHIFT_CTRL             0x08    // bit position
760#define HDMI_TX_I2S_CTRL_DIR_CTRL                0x04   // bit position
761#define HDMI_TX_I2S_CTRL_WS_POL         0x02    // bit position
762#define HDMI_TX_I2S_CTRL_JUST_CTRL               0x01   // bit position
763
764#define HDMI_TX_I2SCH_CTRL_REG 0x53
765#define HDMI_TX_I2SCH_FIFO3_SEL         0xC0    // bit position
766#define HDMI_TX_I2SCH_FIFO2_SEL  0x30   // bit position
767#define HDMI_TX_I2SCH_FIFO1_SEL  0x0C   // bit position
768#define HDMI_TX_I2SCH_FIFO0_SEL  0x03   // bit position
769
770#define HDMI_TX_I2SCH_SWCTRL_REG 0x54
771#define HDMI_TX_I2SCH_SWCTRL_SW3                        0x80    // bit position
772#define HDMI_TX_I2SCH_SWCTRL_SW2                0x40    // bit position
773#define HDMI_TX_I2SCH_SWCTRL_SW1                0x20    // bit position
774#define HDMI_TX_I2SCH_SWCTRL_SW0                0x10    // bit position
775#define HDMI_TX_I2SCH_SWCTRL_INWD_LEN           0xE0    // bit position
776#define HDMI_TX_I2SCH_SWCTRL_INWD_MAX            0x01   // bit position
777
778#define HDMI_TX_SPDIFCH_STATUS_REG 0x55
779#define HDMI_TX_SPDIFCH_STATUS_FS_FREG  0xF0    // bit position
780#define HDMI_TX_SPDIFCH_STATUS_WD_LEN 0x0E      // bit position
781#define HDMI_TX_SPDIFCH_STATUS_WD_MX 0x01       // bit position
782
783#define HDMI_TX_I2SCH_STATUS1_REG 0x56
784#define HDMI_TX_I2SCH_STATUS1_MODE       0xC0   // bit position
785#define HDMI_TX_I2SCH_STATUS1_PCM_MODE   0x38   // bit position
786#define HDMI_TX_I2SCH_STATUS1_SW_CPRGT   0x04   // bit position
787#define HDMI_TX_I2SCH_STATUS1_NON_PCM   0x02    // bit position
788#define HDMI_TX_I2SCH_STATUS1_PROF_APP   0x01   // bit position
789
790#define HDMI_TX_I2SCH_STATUS2_REG 0x57
791
792#define HDMI_TX_I2SCH_STATUS3_REG 0x58
793#define HDMI_TX_I2SCH_STATUS3_CH_NUM    0xF0    // bit position
794#define HDMI_TX_I2SCH_STATUS3_SRC_NUM   0x0F    // bit position
795
796
797
798#define HDMI_TX_I2SCH_STATUS4_REG 0x59
799
800#define HDMI_TX_I2SCH_STATUS5_REG 0x5A
801
802#define HDMI_TX_I2SCH_STATUS5_WORD_MAX 0x01     // bit position
803
804#define HDMI_TX_HDMI_AUDSTATUS_REG 0x5B
805
806#define HDMI_TX_HDMI_AUDSTATUS_SPDIF_DET 0x01   // bit position
807
808#define HDMI_TX_HDMI_AUDBIST_CTRL_REG 0x5C
809
810#define HDMI_TX_HDMI_AUDBIST_EN3                0x08    // bit position
811#define HDMI_TX_HDMI_AUDBIST_EN2                 0x04   // bit position
812#define HDMI_TX_HDMI_AUDBIST_EN1                0x02    // bit position
813#define HDMI_TX_HDMI_AUDBIST_EN0                 0x01   // bit position
814
815#define HDMI_TX_AUD_INCLK_CNT_REG 0x5D
816#define HDMI_TX_AUD_DEBUG_STATUS_REG 0x5E
817
818#define HDMI_TX_AUD_CTRL2_REG           0x5F
819#define HDMI_TX_AUD_CTRL2_AUD_LAYOUT_CTRL       0x80    // bit position
820#define HDMI_TX_AUD_CTRL2_AUD_HBR_EN            0x40    // bit position
821#define HDMI_TX_AUD_CTRL2_CTS_GEN_SC1           0x08    // bit position
822#define HDMI_TX_AUD_CTRL2_AUD_CLK_SEL1          0x04    // bit position
823#define HDMI_TX_AUD_CTRL2_AUD_CS_CTRL           0x02    // bit position
824#define HDMI_TX_AUD_CTRL2_AUD_VBIT                      0x01    // bit position
825
826
827#define HDMI_TX_ONEBIT_AUD_CTRL_REG 0x60
828
829#define HDMI_TX_ONEBIT_AUD_CTRL_SEN7            0x80    // bit position
830#define HDMI_TX_ONEBIT_AUD_CTRL_SEN6            0x40    // bit position
831#define HDMI_TX_ONEBIT_AUD_CTRL_SEN5            0x20    // bit position
832#define HDMI_TX_ONEBIT_AUD_CTRL_SEN4        0x10        // bit position
833#define HDMI_TX_ONEBIT_AUD_CTRL_SEN3            0x08    // bit position
834#define HDMI_TX_ONEBIT_AUD_CTRL_SEN2            0x04    // bit position
835#define HDMI_TX_ONEBIT_AUD_CTRL_SEN1            0x02    // bit position
836#define HDMI_TX_ONEBIT_AUD_CTRL_SEN0            0x01    // bit position
837
838#define HDMI_TX_ONEBIT_AUD0_CTRL_REG 0x61
839#define HDMI_TX_ONEBIT_AUD1_CTRL_REG 0x62
840#define HDMI_TX_ONEBIT_AUD2_CTRL_REG 0x63
841#define HDMI_TX_ONEBIT_AUD3_CTRL_REG 0x64
842
843#define HDMI_TX_ONEBIT_AUDCLK_CTRL_REG 0x65
844#define HDMI_TX_ONEBIT_AUDCLK_DET       0x08    // bit position
845
846#define HDMI_TX_SPDIF_ERR_THRSHLD_REG 0x66
847#define HDMI_TX_SPDIF_ERR_CNT_REG 0x67
848
849#define HDMI_TX_HBIT_AUD_CTRL_REG       0x68
850
851#define HDMI_TX_HDMI_LINK_CTRL_REG 0x70
852#define HDMI_TX_HDMI_LINK_DATA_MUTEEN1          0x80    // bit position
853#define HDMI_TX_HDMI_LINK_DATA_MUTEEN0          0x40    // bit position
854#define HDMI_TX_HDMI_LINK_CLK_MUTEEN2           0x20    // bit position
855#define HDMI_TX_HDMI_LINK_CLK_MUTEEN1       0x10        // bit position
856#define HDMI_TX_HDMI_LINK_CLK_MUTEEN0           0x08    // bit position
857#define HDMI_TX_HDMI_LINK_DEC_DE                        0x04    // bit position
858#define HDMI_TX_HDMI_LINK_PRMB_INC                      0x02    // bit position
859#define HDMI_TX_HDMI_LINK_AUTO_PROG                     0x01    // bit position
860
861#define HDMI_TX_VID_CAPCTRL2_REG  0x71
862
863#define HDMI_TX_VID_CAPCTRL2_CHK_UPDATEEN    0x10       // bit position
864
865#define HDMI_TX_LINK_MUTEEE_REG 0x72
866
867#define HDMI_TX_LINK_MUTEEE_AVMUTE_EN2          0x20    // bit position
868#define HDMI_TX_LINK_MUTEEE_AVMUTE_EN1      0x10        // bit position
869#define HDMI_TX_LINK_MUTEEE_AVMUTE_EN0          0x08    // bit position
870#define HDMI_TX_LINK_MUTEEE_AUDMUTE_EN2         0x04    // bit position
871#define HDMI_TX_LINK_MUTEEE_AUDMUTE_EN1         0x02    // bit position
872#define HDMI_TX_LINK_MUTEEE_AUDMUTE_EN0         0x01    // bit position
873
874#define HDMI_TX_SERDES_TEST0_REG 0x73
875#define HDMI_TX_SERDES_TEST1_REG 0x74
876#define HDMI_TX_SERDES_TEST2_REG 0x75
877
878#define HDMI_TX_I2C_US_COUNTER0_REG     0x76
879#define HDMI_TX_I2C_US_COUNTER1_REG     0x77
880
881#define HDMI_TX_PLL_MISC_CTRL0_REG      0x78
882#define HDMI_TX_PLL_MISC_CTRL0_TIMER_SEL                0x20    // bit position
883#define HDMI_TX_PLL_MISC_CTRL0_RNGCHK_EN                0x10    // bit position
884#define HDMI_TX_PLL_MISC_CTRL0_FORCE_PLLF_LOCK  0x02    // bit position
885#define HDMI_TX_PLL_MISC_CTRL0_PLLF_MAN_RNG             0x01    // bit position
886
887#define HDMI_TX_PLL_MISC_CTRL1_REG      0x79
888#define HDMI_TX_PLL_MISC_CTRL1_MISC_MODE_SEL    0x80    // bit position
889#define HDMI_TX_PLL_MISC_CTRL1_FORCE_TXPLL_LOCK 0x02    // bit position
890#define HDMI_TX_PLL_MISC_CTRL1_TXPLL_MAN_RNG    0x01    // bit position
891
892#define HDMI_TX_ANALOG_BLK_CTRL_REG             0x7A
893
894
895
896
897#define HDMI_TX_DDC_SLV_ADDR_REG 0x80
898#define HDMI_TX_DDC_SLV_SEGADDR_REG 0x81
899#define HDMI_TX_DDC_SLV_OFFADDR_REG 0x82
900#define HDMI_TX_DDC_ACC_CMD_REG 0x83
901#define HDMI_TX_DDC_ACCNUM0_REG 0x84
902#define HDMI_TX_DDC_ACCNUM1_REG 0x85
903
904#define HDMI_TX_DDC_CHSTATUS_REG 0x86
905
906#define HDMI_TX_DDC_CHSTATUS_DDCERR             0x80    // bit position
907#define HDMI_TX_DDC_CHSTATUS_DDC_OCCUPY         0x40    // bit position
908#define HDMI_TX_DDC_CHSTATUS_FIFO_FULL          0x20    // bit position
909#define HDMI_TX_DDC_CHSTATUS_FIFO_EMPT      0x10        // bit position
910#define HDMI_TX_DDC_CHSTATUS_NOACK              0x08    // bit position
911#define HDMI_TX_DDC_CHSTATUS_FIFO_RD                    0x04    // bit position
912#define HDMI_TX_DDC_CHSTATUS_FIFO_WR                    0x02    // bit position
913#define HDMI_TX_DDC_CHSTATUS_INPRO                      0x01    // bit position
914
915#define HDMI_TX_DDC_FIFO_ACC_REG 0x87
916#define HDMI_TX_DDC_FIFOCNT_REG 0x88
917
918#define HDMI_TX_ANA_BLK_CTRL0_REG       0x8A
919#define HDMI_TX_ANA_BLK_CTRL0_OSC_CLK_TEST_EN   0x80    // bit position
920#define HDMI_TX_ANA_BLK_CTRL0_PLL_CLK_TEST_EN   0x40    // bit position
921#define HDMI_TX_ANA_BLK_CTRL0_ST_EN                             0x10    // bit position
922
923#define HDMI_TX_PLLF_CTRL0_REG  0x8B
924#define HDMI_TX_PLLF_CTRL0_PLLF_BYPASS  0x80
925#define HDMI_TX_PLLF_CTRL0_PLLF_SELREG  0x40
926
927#define HDMI_TX_LINK_PLL_CTRL0_REG      0x8C
928#define HDMI_TX_LINK_PLL_CTRL0_SEL_DIV2 0x80
929
930#define HDMI_TX_PLLF_PLL_CTRL_REG               0x8D
931#define HDMI_TX_PLLF_PLL_CTRL_TXPLL_RCNER       0x80
932#define HDMI_TX_PLLF_PLL_CTRL_TXPLL_SELREG      0x10
933
934#define HDMI_TX_ANA_BLK_CTRL1_REG       0x8E
935#define HDMI_TX_ANA_BLK_CTRL2_REG       0x8F
936
937
938
939#define HDMI_TX_SYS_PD_REG 0x90
940#define HDMI_TX_SYS_PD_TXPLL            0x80    // bit position
941#define HDMI_TX_SYS_PD_TMDS             0x40    // bit position
942#define HDMI_TX_SYS_PD_TMDS_CLK         0x20    // bit position
943#define HDMI_TX_SYS_PD_MISC         0x10        // bit position
944#define HDMI_TX_SYS_PD_LINK             0x08    // bit position
945#define HDMI_TX_SYS_PD_IDCK                     0x04    // bit position
946#define HDMI_TX_SYS_PD_AUD                      0x02    // bit position
947#define HDMI_TX_SYS_PD_PLLF     0x01    // bit position
948
949#define HDMI_TX_PLLF_CTRL1_REG 0x91
950#define HDMI_TX_PLLF_CTRL1_PLLF_LOCK    0x80
951#define HDMI_TX_PLLF_CTRL1_PLLF_IND_H           0x40
952#define HDMI_TX_PLLF_CTRL1_PLLF_IND_L           0x20
953#define HDMI_TX_PLLF_CTRL1_PLLF_TEST_EN 0x01
954
955#define HDMI_TX_PLLF_CTRL2_REG 0x92
956#define HDMI_TX_PLLF_CTRL2_SEL_PLLF_TX  0x80
957#define HDMI_TX_PLLF_CTRL2_PLLF_RCORER  0x40
958
959#define HDMI_TX_TX_PLL_CTRL1_REG 0x93
960#define HDMI_TX_TX_PLL_CTRL1_TX_PLL_LOCK        0x80
961#define HDMI_TX_TX_PLL_CTRL1_IND_H      0x40
962#define HDMI_TX_TX_PLL_CTRL1_IND_L      0x20
963#define HDMI_TX_TX_PLL_CTRL1_TX_PLL_TEST_EN     0x01
964
965
966#define HDMI_TX_TX_PLL_CTRL2_REG 0x94
967#define HDMI_TX_TX_PLL_CTRL2_PD_CLK_TEST                0x80
968#define HDMI_TX_TX_PLL_CTRL2_TXPLL_CPREG_BLEED  0x40
969
970#define HDMI_TX_OSC_CTRL_REG 0x95
971#define HDMI_TX_OSC_CTRL_SEL_BG         0x80    // bit position
972
973#define HDMI_TX_TMDS_CH0_CONFIG_REG 0x96
974#define HDMI_TX_TMDS_CH0_TESTEN         0x20    // bit position
975//#define HDMI_TX_TMDS_CH0_AMP          0x1C    // bit position
976//#define HDMI_TX_TMDS_CHO_EMP          0x03    // bit position
977
978#define HDMI_TX_TMDS_CH1_CONFIG_REG 0x97
979#define HDMI_TX_TMDS_CH1_TESTEN         0x20    // bit position
980//#define HDMI_TX_TMDS_CH1_AMP          0x1C    // bit position
981//#define HDMI_TX_TMDS_CH1_EMP          0x03    // bit position
982
983#define HDMI_TX_TMDS_CH2_CONFIG_REG 0x98
984#define HDMI_TX_TMDS_CH2_TESTEN         0x20    // bit position
985#define HDMI_TX_TMDS_CH2_AMP            0x1C    // bit position
986#define HDMI_TX_TMDS_CH2_EMP            0x03    // bit position
987
988#define HDMI_TX_TMDS_CLKCH_CONFIG_REG 0x99
989#define HDMI_TX_TMDS_CLKCH_MUTE         0x80    // bit position
990#define HDMI_TX_TMDS_CLKCH_ST_EN                0x40    //bit position
991#define HDMI_TX_TMDS_CLKCH_TESTEN       0x20    // bit position
992//#define HDMI_TX_TMDS_CLKCH_AMP                0x07    // bit position
993
994#define HDMI_TX_CHIP_CTRL_REG 0x9A
995#define HDMI_TX_CHIP_CTRL_PRBS_GENEN            0x80    // bit position
996//#define HDMI_TX_CHIP_CTRL_LINK_DBGSEL         0x70    // bit position
997#define HDMI_TX_CHIP_CTRL_VID_IF_CHK_EN                 0x08    // bit position
998//#define HDMI_TX_CHIP_CTRL_MISC_TIMER          0x04    // bit position
999#define HDMI_TX_CHIP_CTRL_DDC_LEVEL             0x02    // bit position
1000#define HDMI_TX_CHIP_CTRL_DDC_SMI               0x01    // bit position
1001
1002#define HDMI_TX_CHIP_STATUS_REG 0x9B
1003#define HDMI_TX_CHIP_STATUS_GPIO_DEV_ADDR_IN            0x80    // bit position
1004#define HDMI_TX_CHIP_STATUS_SDA_ST                      0x40    // bit position
1005#define HDMI_TX_CHIP_STATUS_SCL_ST                      0x20    // bit position
1006#define HDMI_TX_CHIP_STATUS_VFIFO_OVER  0x10    // bit position
1007#define HDMI_TX_CHIP_STATUS_VFIFO_UNDER 0x08    // bit position
1008
1009#define HDMI_TX_DBG_PINGPIO_CTRL_REG  0x9C
1010#define HDMI_TX_DBG_PINGPIO_VDLOW_SHAREDEN              0x04    // bit position
1011#define HDMI_TX_DBG_PINGPIO_GPIO_ADDREN                 0x02    // bit position
1012#define HDMI_TX_DBG_PINGPIO_GPIO_OUT                    0x01    // bit position
1013
1014#define HDMI_TX_CHIP_DEBUG0_CTRL_REG  0x9D
1015#define HDMI_TX_CHIP_DEBUG0_PRBS_ERR 0xE0               // bit position
1016#define HDMI_TX_CHIP_DEBUG0_CAPST        0x1F           // bit position
1017
1018#define HDMI_TX_CHIP_DEBUG1_CTRL_REG  0x9E
1019#define HDMI_TX_CHIP_DEBUG1_SDA_SW              0x80    // bit position
1020#define HDMI_TX_CHIP_DEBUG1_SCL_SW              0x40    // bit position
1021#define HDMI_TX_CHIP_DEBUG1_SERDES_TESTEN               0x20    // bit position
1022#define HDMI_TX_CHIP_DEBUG1_CLK_BYPASS      0x10        // bit position
1023#define HDMI_TX_CHIP_DEBUG1_INV_INTER_IDCK              0x08    // bit position
1024#define HDMI_TX_CHIP_DEBUG1_PLLLOCK_BYPASS                      0x04    // bit position
1025#define HDMI_TX_CHIP_DEBUG1_FORCE_HP                    0x02    // bit position
1026#define HDMI_TX_CHIP_DEBUG1_HP_DEGLITCH                 0x01    // bit position
1027
1028#define HDMI_TX_CHIP_DEBUG2_CTRL_REG  0x9F
1029#define HDMI_TX_CHIP_DEBUG2_EXEMB_SYNCEN                0x04    // bit position
1030#define HDMI_TX_CHIP_DEBUG2_VIDBIST                     0x02    // bit position
1031
1032#define HDMI_TX_VID_INCLK_REG  0x5F
1033
1034#define HDMI_TX_HDCP_STATUS_REG  0xA0
1035#define HDMI_TX_HDCP_STATUS_ADV_CIPHER          0x80    // bit position
1036#define HDMI_TX_HDCP_STATUS_R0_READY        0x10        // bit position
1037#define HDMI_TX_HDCP_STATUS_AKSV_ACT            0x08    // bit position
1038#define HDMI_TX_HDCP_STATUS_ENCRYPT                     0x04    // bit position
1039#define HDMI_TX_HDCP_STATUS_AUTH_PASS                   0x02    // bit position
1040#define HDMI_TX_HDCP_STATUS_KEY_DONE                    0x01    // bit position
1041
1042#define HDMI_TX_HDCP_CTRL0_REG  0xA1
1043#define HDMI_TX_HDCP_CTRL0_STORE_AN             0x80    // bit position
1044#define HDMI_TX_HDCP_CTRL0_RX_REP               0x40    // bit position
1045#define HDMI_TX_HDCP_CTRL0_RE_AUTH              0x20    // bit position
1046#define HDMI_TX_HDCP_CTRL0_SW_AUTHOK        0x10        // bit position
1047#define HDMI_TX_HDCP_CTRL0_HW_AUTHEN            0x08    // bit position
1048#define HDMI_TX_HDCP_CTRL0_ENC_EN                       0x04    // bit position
1049#define HDMI_TX_HDCP_CTRL0_BKSV_SRM                     0x02    // bit position
1050#define HDMI_TX_HDCP_CTRL0_KSV_VLD                      0x01    // bit position
1051
1052#define HDMI_TX_HDCP_CTRL1_REG  0xA2
1053#define HDMI_TX_HDCP_CTRL1_SYNC_CHK_TIME_SEL    0x80    // bit position
1054#define HDMI_TX_LINK_CHK_12_EN  0x40
1055#define HDMI_TX_HDCP_CTRL1_DDC_NOSTOP           0x20    // bit position
1056#define HDMI_TX_HDCP_CTRL1_DDC_NOACK        0x10        // bit position
1057#define HDMI_TX_HDCP_CTRL1_EDDC_NOACK           0x08    // bit position
1058#define HDMI_TX_HDCP_CTRL1_BLUE_SCREEN_EN                       0x04    // bit position
1059#define HDMI_TX_HDCP_CTRL1_RCV11_EN                     0x02    // bit position
1060#define HDMI_TX_HDCP_CTRL1_HDCP11_EN                    0x01    // bit position
1061
1062#define HDMI_TX_HDCP_Link_Check_FRAME_NUM_REG  0xA3
1063
1064#define HDMI_TX_HDCP_CTRL2_REG  0xA4
1065#define HDMI_TX_HDCP_CTRL2_LINK_AUTO_CHK_EN             0x80
1066#define HDMI_TX_HDCP_CTRL2_LINK_DBL_CHK_EN              0x40
1067#define HDMI_TX_HDCP_CTRL2_DERIVE_NEXT_AN               0x04
1068#define HDMI_TX_HDCP_CTRL2_SOFT_LINK_AUTOCHK_EN 0x02
1069#define HDMI_TX_HDCP_CTRL2_LINK_CHK_SOFT_JUDGE          0x01
1070
1071#define HDMI_TX_HDCP_AKSV1_REG  0xA5
1072#define HDMI_TX_HDCP_AKSV2_REG  0xA6
1073#define HDMI_TX_HDCP_AKSV3_REG  0xA7
1074#define HDMI_TX_HDCP_AKSV4_REG  0xA8
1075#define HDMI_TX_HDCP_AKSV5_REG  0xA9
1076
1077#define HDMI_TX_HDCP_AN1_REG  0xAA
1078#define HDMI_TX_HDCP_AN2_REG  0xAB
1079#define HDMI_TX_HDCP_AN3_REG  0xAC
1080#define HDMI_TX_HDCP_AN4_REG  0xAD
1081#define HDMI_TX_HDCP_AN5_REG  0xAE
1082#define HDMI_TX_HDCP_AN6_REG  0xAF
1083#define HDMI_TX_HDCP_AN7_REG  0xB0
1084#define HDMI_TX_HDCP_AN8_REG  0xB1
1085
1086#define HDMI_TX_HDCP_BKSV1_REG  0xB2
1087#define HDMI_TX_HDCP_BKSV2_REG  0xB3
1088#define HDMI_TX_HDCP_BKSV3_REG  0xB4
1089#define HDMI_TX_HDCP_BKSV4_REG  0xB5
1090#define HDMI_TX_HDCP_BKSV5_REG  0xB6
1091
1092#define HDMI_TX_HDCP_RI1_REG  0xB7
1093#define HDMI_TX_HDCP_RI2_REG  0xB8
1094
1095#define HDMI_TX_HDCP_PJ_REG  0xB9
1096#define HDMI_TX_HDCP_RX_CAPS_REG  0xBA
1097#define HDMI_TX_HDCP_BSTATUS0_REG  0xBB
1098#define HDMI_TX_HDCP_BSTATUS1_REG  0xBC
1099
1100#define HDMI_TX_HDCP_AMO0_REG  0xD0
1101#define HDMI_TX_HDCP_AMO1_REG  0xD1
1102#define HDMI_TX_HDCP_AMO2_REG  0xD2
1103#define HDMI_TX_HDCP_AMO3_REG  0xD3
1104#define HDMI_TX_HDCP_AMO4_REG  0xD4
1105#define HDMI_TX_HDCP_AMO5_REG  0xD5
1106#define HDMI_TX_HDCP_AMO6_REG  0xD6
1107#define HDMI_TX_HDCP_AMO7_REG  0xD7
1108
1109#define HDMI_TX_HDCP_DBG_CTRL_REG  0xBD
1110#define HDMI_TX_HDCP_DBG_CTRL_FORCE_RI_INV              0x20    // bit position
1111#define HDMI_TX_HDCP_DBG_CTRL_HLD_RI_VALUE              0X10    // bit position
1112#define HDMI_TX_HDCP_DBG_ENC_WIN_INC    0x08    // bit position
1113//#define HDMI_TX_HDCP_DBG_DDC_SPEED    0x06    // bit position
1114#define HDMI_TX_HDCP_DBG_SKIP_RPT       0x01    // bit position
1115
1116#define HDMI_TX_HDCP_KEY_STATUS_REG  0xBE
1117#define HDMI_TX_HDCP_KEY_BIST_EN        0x04    // bit position
1118#define HDMI_TX_HDCP_KEY_BIST_ERR       0x02    // bit position
1119#define HDMI_TX_HDCP_KEY_CMD_DONE       0x01    // bit position
1120
1121#define HDMI_TX_KEY_CMD_REGISTER 0xBF   //added
1122
1123#define HDMI_TX_HDCP_AUTHDBG_STATUS_REG  0xC7
1124#define HDMI_TX_HDCP_ENCRYPTDBG_STATUS_REG  0xC8
1125#define HDMI_TX_HDCP_FRAME_NUM_REG  0xC9
1126
1127#define HDMI_TX_DDC_MSTR_INTER_REG  0xCA
1128#define HDMI_TX_DDC_MSTR_LINK_REG  0xCB
1129
1130#define HDMI_TX_HDCP_BLUESCREEN0_REG  0xCC
1131#define HDMI_TX_HDCP_BLUESCREEN1_REG  0xCD
1132#define HDMI_TX_HDCP_BLUESCREEN2_REG  0xCE
1133
1134#define HDMI_TX_HDCP_WAIT_R0_TIMING_REG 0xE0
1135#define HDMI_TX_HDCP_LINK_INTEGRITY_CHK_TIMER_REG       0xE1
1136#define HDMI_TX_HDCP_REPEATER_READY_WAIT_TIMER_REG      0xE2
1137#define HDMI_TX_HDCP_REPEATER_WAIT_TIMING0_REG          0xE3
1138#define HDMI_TX_HDCP_REPEATER_WAIT_TIMING1_REG          0xE4
1139
1140
1141
1142//      DEV_ADDR = 0x7A or 0x7E
1143#define HDMI_TX_INFO_PKTCTRL1_REG  0xC0
1144#define HDMI_TX_INFO_PKTCTRL1_SPD_RPT           0x80    // bit position
1145#define HDMI_TX_INFO_PKTCTRL1_SPD_EN            0x40    // bit position
1146#define HDMI_TX_INFO_PKTCTRL1_AVI_RPT           0x20    // bit position
1147#define HDMI_TX_INFO_PKTCTRL1_AVI_EN        0x10        // bit position
1148#define HDMI_TX_INFO_PKTCTRL1_GCP_RPT           0x08    // bit position
1149#define HDMI_TX_INFO_PKTCTRL1_GCP_EN            0x04    // bit position
1150#define HDMI_TX_INFO_PKTCTRL1_ACR_NEW           0x02    // bit position
1151#define HDMI_TX_INFO_PKTCTRL1_ACR_EN            0x01    // bit position
1152
1153#define HDMI_TX_INFO_PKTCTRL2_REG  0xC1
1154#define HDMI_TX_INFO_PKTCTRL2_UD1_RPT           0x80    // bit position
1155#define HDMI_TX_INFO_PKTCTRL2_UD1_EN            0x40    // bit position
1156#define HDMI_TX_INFO_PKTCTRL2_UD0_RPT           0x20    // bit position
1157#define HDMI_TX_INFO_PKTCTRL2_UD0_EN        0x10        // bit position
1158#define HDMI_TX_INFO_PKTCTRL2_MPEG_RPT          0x08    // bit position
1159#define HDMI_TX_INFO_PKTCTRL2_MPEG_EN           0x04    // bit position
1160#define HDMI_TX_INFO_PKTCTRL2_AIF_RPT           0x02    // bit position
1161#define HDMI_TX_INFO_PKTCTRL2_AIF_EN            0x01    // bit position
1162
1163#define HDMI_TX_ACR_N1_SW_REG  0xC2
1164#define HDMI_TX_ACR_N2_SW_REG  0xC3
1165#define HDMI_TX_ACR_N3_SW_REG  0xC4
1166
1167#define HDMI_TX_ACR_CTS1_SW_REG  0xC5
1168#define HDMI_TX_ACR_CTS2_SW_REG  0xC6
1169#define HDMI_TX_ACR_CTS3_SW_REG  0xC7
1170
1171#define HDMI_TX_ACR_CTS1_HW_REG  0xC8
1172#define HDMI_TX_ACR_CTS2_HW_REG  0xC9
1173#define HDMI_TX_ACR_CTS3_HW_REG  0xCA
1174
1175#define HDMI_TX_ACR_CTS_CTRL_REG  0xCB
1176
1177#define HDMI_TX_GNRL_CTRL_PKT_REG  0xCC
1178#define HDMI_TX_GNRL_CTRL_PKT_GCP_DCP_CTRL      0x80    // bit position
1179#define HDMI_TX_GNRL_CTRL_PKT_DC_PKT_EN         0x40    // bit position
1180#define HDMI_TX_GNRL_CTRL_CLR_AVMUTE            0x02    // bit position
1181#define HDMI_TX_GNRL_CTRL_SET_AVMUTE            0x01    // bit position
1182
1183#define HDMI_TX_AUD_PKT_FLATCTRL_REG  0xCD
1184#define HDMI_TX_AUD_PKT_AUTOFLAT_EN             0x80    // bit position
1185#define HDMI_TX_AUD_PKT_FLATCTRL_GCP_DCP_OR_DER_CTRL    0x20    // bit position
1186#define HDMI_TX_AUD_PKT_FLATCTRL_GCP_DCP_CONTENT_CTRL   0x10    // bit position
1187#define HDMI_TX_AUD_PKT_FLAT                            0x07    // bit position
1188
1189#define HDMI_TX_GCP_HEADER_ID_REG       0xCE
1190#define HDMI_TX_AUD_PACKET_HEADER_ID_REG        0xCF
1191
1192#define HDMI_TX_CEC_CTRL_REG    0xD0
1193#define HDMI_TX_CEC_CTRL_RX_EN  0x08    // bit position
1194#define HDMI_TX_CEC_CTRL_TX_ST  0x04    // bit position
1195#define HDMI_TX_CEC_CTRL_PIN_SEL        0x02    // bit position
1196#define HDMI_TX_CEC_CTRL_RESET  0x01    // bit position
1197
1198#define HDMI_TX_CEC_RX_STATUS_REG       0xD1
1199#define HDMI_TX_CEC_RX_STATUS_RX_BUSY   0x80    // bit position
1200#define HDMI_TX_CEC_RX_STATUS_RX_FULL   0x20    // bit position
1201#define HDMI_TX_CEC_RX_STATUS_RX_EMP            0x10    // bit position
1202
1203#define HDMI_TX_CEC_TX_STATUS_REG       0xD2
1204#define HDMI_TX_CEC_TX_STATUS_TX_BUSY   0x80    // bit position
1205#define HDMI_TX_CEC_TX_STATUS_TX_FAIL   0x40    // bit position
1206#define HDMI_TX_CEC_TX_STATUS_TX_FULL   0x20    // bit position
1207#define HDMI_TX_CEC_TX_STATUS_TX_EMPTY  0x10    // bit position
1208
1209#define HDMI_TX_CEC_TX_FIFO_REG 0xD3
1210
1211#define HDMI_TX_CEC_SPEED_CTRL_REG      0xD4
1212
1213
1214
1215//InfoFrame and Control Packet Registers
1216// 0x7A or 0X7E
1217
1218#define AVI_HB0  0x00
1219#define AVI_HB1  0x01
1220#define AVI_HB2  0x02
1221#define AVI_PB0   0x03
1222#define AVI_PB1   0x04
1223#define AVI_PB2   0x05
1224#define AVI_PB3   0x06
1225#define AVI_PB4   0x07
1226#define AVI_PB5   0x08
1227#define AVI_PB6   0x09
1228#define AVI_PB7   0x0A
1229#define AVI_PB8   0x0B
1230#define AVI_PB9   0x0C
1231#define AVI_PB10   0x0D
1232#define AVI_PB11   0x0E
1233#define AVI_PB12   0x0F
1234#define AVI_PB13   0x10
1235#define AVI_PB14   0x11
1236#define AVI_PB15   0x12
1237
1238#define AUD_HBO  0x20
1239#define AUD_HB1  0x21
1240#define AUD_HB2  0x22
1241#define AUD_PB0  0x23
1242#define AUD_PB1  0x24
1243#define AUD_PB2  0x25
1244#define AUD_PB3  0x26
1245#define AUD_PB4  0x27
1246#define AUD_PB5  0x28
1247#define AUD_PB6  0x29
1248#define AUD_PB7  0x2A
1249#define AUD_PB8  0x2B
1250#define AUD_PB9  0x2C
1251#define AUD_PB10  0x2D
1252
1253#define SPD_HBO  0x40
1254#define SPD_HB1  0x41
1255#define SPD_HB2  0x42
1256#define SPD_PB0  0x43
1257#define SPD_PB1  0x44
1258#define SPD_PB2  0x45
1259#define SPD_PB3  0x46
1260#define SPD_PB4  0x47
1261#define SPD_PB5  0x48
1262#define SPD_PB6  0x49
1263#define SPD_PB7  0x4A
1264#define SPD_PB8  0x4B
1265#define SPD_PB9  0x4C
1266#define SPD_PB10  0x4D
1267#define SPD_PB11  0x4E
1268#define SPD_PB12  0x4F
1269#define SPD_PB13  0x50
1270#define SPD_PB14  0x51
1271#define SPD_PB15  0x52
1272#define SPD_PB16  0x53
1273#define SPD_PB17  0x54
1274#define SPD_PB18  0x55
1275#define SPD_PB19  0x56
1276#define SPD_PB20  0x57
1277#define SPD_PB21  0x58
1278#define SPD_PB22  0x59
1279#define SPD_PB23  0x5A
1280#define SPD_PB24  0x5B
1281#define SPD_PB25  0x5C
1282#define SPD_PB26  0x5D
1283#define SPD_PB27  0x5E
1284
1285#define MPEG_HBO  0x60
1286#define MPEG_HB1  0x61
1287#define MPEG_HB2  0x62
1288#define MPEG_PB0  0x63
1289#define MPEG_PB1  0x64
1290#define MPEG_PB2  0x65
1291#define MPEG_PB3  0x66
1292#define MPEG_PB4  0x67
1293#define MPEG_PB5  0x68
1294#define MPEG_PB6  0x69
1295#define MPEG_PB7  0x6A
1296#define MPEG_PB8  0x6B
1297#define MPEG_PB9  0x6C
1298#define MPEG_PB10  0x6D
1299#define MPEG_PB11  0x6E
1300#define MPEG_PB12  0x6F
1301#define MPEG_PB13  0x70
1302#define MPEG_PB14  0x71
1303#define MPEG_PB15  0x72
1304#define MPEG_PB16  0x73
1305#define MPEG_PB17  0x74
1306#define MPEG_PB18  0x75
1307#define MPEG_PB19  0x76
1308#define MPEG_PB20  0x77
1309#define MPEG_PB21  0x78
1310#define MPEG_PB22  0x79
1311#define MPEG_PB23  0x7A
1312#define MPEG_PB24  0x7B
1313#define MPEG_PB25  0x7C
1314#define MPEG_PB26  0x7D
1315#define MPEG_PB27  0x7E
1316
1317#define USRDF0_HBO  0x80
1318#define USRDF0_HB1  0x81
1319#define USRDF0_HB2  0x82
1320#define USRDF0_PB0  0x83
1321#define USRDF0_PB1  0x84
1322#define USRDF0_PB2  0x85
1323#define USRDF0_PB3  0x86
1324#define USRDF0_PB4  0x87
1325#define USRDF0_PB5  0x88
1326#define USRDF0_PB6  0x89
1327#define USRDF0_PB7  0x8A
1328#define USRDF0_PB8  0x8B
1329#define USRDF0_PB9  0x8C
1330#define USRDF0_PB10  0x8D
1331#define USRDF0_PB11  0x8E
1332#define USRDF0_PB12  0x8F
1333#define USRDF0_PB13  0x90
1334#define USRDF0_PB14  0x91
1335#define USRDF0_PB15  0x92
1336#define USRDF0_PB16  0x93
1337#define USRDF0_PB17  0x94
1338#define USRDF0_PB18  0x95
1339#define USRDF0_PB19  0x96
1340#define USRDF0_PB20  0x97
1341#define USRDF0_PB21  0x98
1342#define USRDF0_PB22  0x99
1343#define USRDF0_PB23  0x9A
1344#define USRDF0_PB24  0x9B
1345#define USRDF0_PB25  0x9C
1346#define USRDF0_PB26  0x9D
1347#define USRDF0_PB27  0x9E
1348
1349#define USRDF1_HBO  0xA0
1350#define USRDF1_HB1  0xA1
1351#define USRDF1_HB2  0xA2
1352#define USRDF1_PB0  0xA3
1353#define USRDF1_PB1  0xA4
1354#define USRDF1_PB2  0xA5
1355#define USRDF1_PB3  0xA6
1356#define USRDF1_PB4  0xA7
1357#define USRDF1_PB5  0xA8
1358#define USRDF1_PB6  0xA9
1359#define USRDF1_PB7  0xAA
1360#define USRDF1_PB8  0xAB
1361#define USRDF1_PB9  0xAC
1362#define USRDF1_PB10  0xAD
1363#define USRDF1_PB11  0xAE
1364#define USRDF1_PB12  0xAF
1365#define USRDF1_PB13  0xB0
1366#define USRDF1_PB14  0xB1
1367#define USRDF1_PB15  0xB2
1368#define USRDF1_PB16  0xB3
1369#define USRDF1_PB17  0xB4
1370#define USRDF1_PB18  0xB5
1371#define USRDF1_PB19  0xB6
1372#define USRDF1_PB20  0xB7
1373#define USRDF1_PB21  0xB8
1374#define USRDF1_PB22  0xB9
1375#define USRDF1_PB23  0xBA
1376#define USRDF1_PB24  0xBB
1377#define USRDF1_PB25  0xBC
1378#define USRDF1_PB26  0xBD
1379#define USRDF1_PB27  0xBE
1380
1381
1382#define init_timer_slot()   do { timer_slot = 0; } while (0)
1383void HDMI_TX_Timer_Process ();
1384
1385void HDMI_TX_Config_Video(void);
1386void HDMI_TX_Parse_Video_Format(void);
1387void HDMI_TX_Get_Video_Timing(void);
1388void HDMI_TX_DE_Generator(void);
1389void HDMI_TX_Embed_Sync_Decode(void);
1390void HDMI_TX_Show_Video_Parameter(void);
1391void HDMI_TX_Clean_HDCP(void);
1392
1393BYTE HDMI_TX_Config_Packet();
1394BYTE HDMI_TX_Load_Infoframe(packet_type member,
1395                            infoframe_struct *p);
1396
1397BYTE HDMI_TX_Checksum(infoframe_struct *p);
1398BYTE HDMI_TX_Config_Audio();
1399BYTE HDMI_TX_Config_I2s();
1400BYTE HDMI_TX_Config_Spdif();
1401BYTE HDMI_TX_Config_Super_Audio();
1402void HDMI_TX_HDCP_Process(void);
1403void HDMI_TX_PLAYBACK_Process(void);
1404void HDMI_TX_Timer_Slot1(void);
1405void HDMI_TX_Timer_Slot2(void);
1406void HDMI_TX_Timer_Slot3(void);
1407void HDMI_TX_Timer_Slot4(void);
1408void HDMI_TX_Hotplug_Change_Interrupt(void);
1409void HDMI_TX_Variable_Initial(void);
1410void HDMI_TX_HW_Interface_Variable_Initial();
1411//void HDMI_TX_Config_Bist_Video(WORD bist_select_number);
1412//** void HDMI_TX_Config_Clock_Generator_Frequency(WORD bist_select_number);
1413void HDMI_TX_Video_Format_Change_Interrupt(void);
1414void HDMI_TX_Video_Clock_Change_Interrupt(void);
1415void HDMI_TX_Audio_CLK_Change_Interrupt(void);
1416void HDMI_TX_Set_AVMute(void);
1417void HDMI_TX_Clear_AVMute(void);
1418BYTE HDMI_TX_BKSV_SRM(void);
1419void HDMI_TX_Auth_Done_Interrupt(void);
1420void HDMI_TX_Auth_Change_Interrupt(void);
1421void HDMI_TX_Blue_Screen_Format_Config(void);
1422void HDMI_TX_Blue_Screen_Enable(void);
1423void HDMI_TX_Blue_Screen_Disable(void);
1424void HDMI_TX_HDCP_Encryption_Enable(void);
1425void HDMI_TX_HDCP_Encryption_Disable(void);
1426void HDMI_TX_AFIFO_Overrun_Interrupt(void); 
1427void HDMI_TX_PllLock_Interrupt(void);
1428//void HDMI_TX_Rx_Sense_Interrupt(void);
1429void HDMI_TX_SPDIF_Error_Interrupt(BYTE int1, BYTE int3);
1430void HDMI_TX_RST_DDCChannel(void);
1431void HDMI_TX_Hardware_HDCP_Auth_Init(void);
1432void HDMI_TX_Hardware_Reset(void);
1433void HDMI_TX_Set_System_State(BYTE ss);
1434void HDMI_TX_Hardware_Initial(void);
1435void HDMI_TX_API_Initial(void);
1436void HDMI_TX_Interrupt_Process(void);
1437void HDMI_TX_Interrupt_Information(BYTE c, BYTE n);
1438
1439BYTE HDMI_TX_Parse_EDID(void);
1440void HDMI_TX_Read_EDID(void); 
1441BYTE HDMI_TX_Parse_EDIDHeader(void);
1442BYTE HDMI_TX_Parse_EDIDVersion(void);
1443void HDMI_TX_Parse_DTD(void);
1444//void HDMI_TX_Parse_BasicDis(void);
1445void HDMI_TX_Parse_VendorSTD(void);
1446void HDMI_TX_Parse_SpeakerSTD(void);
1447void HDMI_TX_Parse_VideoSTD(void);
1448void HDMI_TX_Parse_AudioSTD(void);
1449void HDMI_TX_Parse_STD(void);
1450void HDMI_TX_Parse_NativeFormat(void);
1451void HDMI_TX_Parse_DTDinBlockONE(void);
1452void HDMI_TX_Parse_DTDinExtBlock(void);
1453BYTE HDMI_TX_Parse_ExtBlock(void);
1454void HDMI_TX_GetEDIDLength(void);
1455void HDMI_TX_EDID_Parsing_Result(void);
1456BYTE HDMI_TX_EDID_Checksum(BYTE block_number) ;
1457void HDMI_TX_InitDDC_Read(BYTE devaddr, BYTE segmentpointer,BYTE offset, BYTE  access_num_Low,BYTE access_num_high);
1458BYTE HDMI_TX_Read_RealEDID_BYTE(BYTE segmentpointer,BYTE offset);
1459BYTE HDMI_TX_Read_EDID_BYTE(BYTE segmentpointer,BYTE offset);
1460void HDMI_TX_DDC_Mass_Read(WORD length, BYTE *buf);
1461//void Write_data_to_EE();
1462void HDMI_TX_Config_Auto_Video_Format(void);
1463void HDMI_TX_Config_Manual_Video_Format(WORD bist_select_number);
1464
1465#if BIST_MODE_USED
1466void HDMI_TX_BIST();
1467#endif
1468void HDMI_TX_Config_Clock_Generator_Frequency(WORD bist_select_number);
1469//void HDMI_TX_Config_Bist_Video_RefreshF(BYTE switch_value);
1470void HDMI_TX_Reset_AVI(void) ;
1471void HDMI_TX_Reset_BIST_Setting(void) ;
1472void HDMI_TX_Config_Bist_Video(WORD bist_select_number); 
1473
1474BYTE HDMI_TX_IS_KSVList_VLD(void);
1475//void HDMI_TX_IS_KSVFIFO_Ready(void);
1476BYTE HDMI_TX_Check_KSV_SRM(void);
1477void HDMI_TX_Task();
1478void HDMI_TX_BIST_Task(void);
1479void HDMI_TX_PLLFilter_Reset(void);
1480void HDMI_TX_MuteTMDS_CLK(void);
1481//void HDMI_TX_InitDDC_Write(BYTE devaddr, BYTE segmentpointer,
1482//    BYTE offset, BYTE  access_num_Low,BYTE access_num_high);
1483void HDMI_TX_HW_Vid_Testing(void);
1484void HDMI_TX_CSCandColorDepth_Setting(void);
1485void HDMI_TX_RepeatTimes_Setting(void);
1486void HDMI_TX_Video_Interface_HW_Setting(void);
1487#if (HDMI_TX_USE_NATIVE_CODE)
1488void HDMI_RPT_Set_BCAPS_Repeater(BIT is_repeater);
1489void HDMI_RPT_Set_KSVList_Init(BYTE start_addr,BYTE length);
1490void HDMI_RPT_Set_BSTATUS1(BYTE bstatus1);
1491void HDMI_RPT_Set_BSTATUS2(BYTE bstatus2);
1492void HDMI_RPT_Set_SHA_Calc_Start(void);
1493BIT HDMI_RPT_Get_SHA_Ready(void);
1494void HDMI_RPT_Set_BCAPS_Ready(BIT ready);
1495DS_BOOL HDMI_TX_GetCorrectMuteState(DS_BOOL mute);
1496BYTE HDMI_TX_Get_System_State(void);
1497
1498//void HDMI_RPT_Get_KSV(void);
1499#endif
1500#endif
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