source: svn/trunk/zas_dstar/hal/os/src/module/dstmodule.h

/****************************************************************************
 * Copyright (c) 2006 DST Technologies Inc.  All Rights Reserved.   
 *
 * Module:      DSTMODULE
 *
 * Description: This file contains module interface definitions that are 
 *              shared between kernel and user mode
 *
 * Notes:       
 *
 ***************************************************************************/
#ifndef _DSTMODULE_H
#define _DSTMODULE_H

/*==========================
 * OS include
 *=========================*/
#include "dsthallocal.h"
#include "oem_opt.h"

#define DSTMOD_VERSION_NUMBER   0x0010

/*===========================================================================
 * Number of devices that are supported
 *===========================================================================*/
#define MAX_DEVICES             1
#define DST_DEV_NAME            "dstmod"

/*===========================================================================
 * DST Module Version String
 *===========================================================================*/
#define DSTMOD_VERSION_STRING   "D1.00"

/*===========================================================================
 * DST_IOC_MAGIC is an arbitrary IOCTL magic
 * number that was pulled out of thin air.
 *===========================================================================*/
#define DST_IOC_MAGIC               0xD7

#define DSTHWIOC_TIME_STAMP         _IOWR (DST_IOC_MAGIC,  7, DS_S64 *)
#define DSTHWIOC_SET_DBG_LEVEL      _IOR (DST_IOC_MAGIC,  22, DST_SET_DBG_LEVEL_MESSAGE_PARAMS *)
#define DSTHWIOC_SEM_OP             _IOR (DST_IOC_MAGIC,  25, DS_U32)
#define DSTHWIOC_EVENT_OP           _IOR (DST_IOC_MAGIC,  26, DS_U32)
#define DSTHWIOC_ATOMIC_REG_ACCESS  _IOWR (DST_IOC_MAGIC, 27, DS_U32)
#define DSTHWIOC_GET_VERSION        _IOR  (DST_IOC_MAGIC, 39, DS_U32)
#define DSTHWIOC_GET_LOADER_VER                 _IOR    (DST_IOC_MAGIC, 40, DS_U32)
#define DSTHWIOC_IRQ_DISABLE        _IOWR (DST_IOC_MAGIC, 67, DS_U32)
#define DSTHWIOC_IRQ_ENABLE         _IOWR (DST_IOC_MAGIC, 68, DS_U32)
#define DSTHWIOC_IRQ_RESTORE        _IOWR (DST_IOC_MAGIC, 69, DS_U32)

/*===========================================================================
 * Types and defines PCI bus
 *==========================================================================*/
typedef struct
{
    DS_U32 Offset;      /* Offset in PCI config Space   */
    DS_U32 Data;        /* Data to r/w                  */
    DS_U32 Size;        /* R/W size. 1, 2 or 4.         */
    DS_U32 ChipIndex;   /* Required chip index          */
    DS_U32 DevId;       /* Device PCI ID                */
} PCI_DATA;

/*===========================================================================
 * Types and defines for semaphores and events library
 *==========================================================================*/
typedef enum
{
    OBJ_OPCODE_CREATE = 0,
    OBJ_OPCODE_DELETE,
    OBJ_OPCODE_LOCK,
    OBJ_OPCODE_UNLOCK,
    OBJ_OPCODE_WAIT,
    OBJ_OPCODE_SET,
    OBJ_OPCODE_RESET,
    OBJ_OPCODE_INFO,
    OBJ_OPCODE_READ,
    OBJ_OPCODE_WRITE
}OBJ_OPCODE;

typedef enum
{
    OBJ_OK = 0,
    OBJ_INVALID_OP,
    OBJ_INVALID_ID,
    OBJ_TIMEOUT,
    OBJ_MAX_PROCS,
    OBJ_MAX_OBJS,
    OBJ_SIGNAL_RCV,
    OBJ_BAD_COUNT,
    OBJ_COUNT_MISMATCH
}OBJ_ERR_CODE;

typedef struct
{
    DS_U32  Opcode;
    DS_U32  Prm1;
    DS_U32  Prm2;
    DS_U32  RetCode;
}OBJ_OPER;

typedef struct _msg_set_dbg_level_params
{
    DS_U32  qh;
    DS_U32  level;
} DST_SET_DBG_LEVEL_MESSAGE_PARAMS;

#endif /* _DSTMODULE_H */