/*************************************************************************
**	Broadcom Corp. Confidential
**	Copyright 2010 Broadcom Corp.  All Rights Reserved.
**
**	THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
**	AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
**	EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
**
**	File:			bls1.S
**	Description:	stage 1 of two stage bootloader for 755x chip.
**	Created:		alexp
**
**	REVISION:
**
***************************************************************************/

#include "bmips3300.h"
#include "bchp.h"
#include "bchp_common.h"
#include "bchp_sun_top_ctrl.h"
#include "bchp_memc_ddr23_aphy_ac_0.h"
#include "memc_0_config.h"
#include "chip_secure.physical_7550.h"
        
#define SHMOO_STACK_START 0x80000000
#define SHMOO_STACK_SIZE 0x4000

#define BCHP_REG_BASE PHYS_TO_K1(BCHP_PHYSICAL_OFFSET)
#define INITIAL_SR		((CP0_STATUS_SR_MASK | CP0_STATUS_CU1_MASK | CP0_STATUS_BEV_MASK | CP0_STATUS_IE_MASK) & ~( CP0_STATUS_ERL_MASK | CP0_STATUS_EXL_MASK))
		BL_STACK_SIZE = 0x1000
#if defined(RSA_BITS)
		RSA_KEY_SIZE = (RSA_BITS/8)
#else
		RSA_KEY_SIZE = 0x80
#endif
		.lcomm bl_stack, BL_STACK_SIZE
		.text
		.globl __start
		.set	noreorder

__start:
		b init_cpu
		nop
		nop
		nop
/* size of stage1+stage2 */
		.word _bootloader_size
		.org __start+0x380
rom_gen_ex:		# general exception will loop here
		b rom_gen_ex
		nop
		nop
		nop
		.org __start+0x400
		.globl key1
key1:
.include "BCM7572_UDTA_key1_m0.S"
/* .include "test_key1_m0.S" */
/* .include "test1024_key1.S" */
/* .include "example_key1.S"*/
external_root_key:
		.fill RSA_KEY_SIZE, 1, 0xdd
bootloader_signature:
		.fill RSA_KEY_SIZE, 1, 0xee
bootloader_header:
		.fill 0x40, 1, 0x55
init_cpu:
		li t0, INITIAL_SR
		mtc0 t0, CP0_STATUS
		nop
		nop

		move $28, $0
.if 0 /* Surendra and Andrew indicate this is needed in the bootloader */
		/* DRAM for HD DTA */
		li t0, BCHP_REG_BASE | BCHP_MEMC_DDR23_APHY_AC_0_PLL_FREQ_CNTL
		lw t2, 0(t0)
		and t3, t2, ~BCHP_MEMC_DDR23_APHY_AC_0_PLL_FREQ_CNTL_MDIV_MASK
		or t3, (5 << BCHP_MEMC_DDR23_APHY_AC_0_PLL_FREQ_CNTL_MDIV_SHIFT)
		sw t3, 0(t0)
		sync
.endif
/* check if otp_rom_uart_disable bit is set */
		li t0, BCHP_REG_BASE | XPT_OTP_MSP_WORD_8
		lw t2, 0(t0)
		andi t2, 0x10
		bnez t2, skip_uart_init
		nop

		bal init_serial
		nop

		bal _writeasm
		li a0, '$'
skip_uart_init:
		bal do_chip_init
		nop

		bal _writeasm
		li a0, '?'

		bal init_mips
		nop

		bal _writeasm
		li a0, '+'

		li		a0, SHMOO_STACK_START
		li		a1, SHMOO_STACK_SIZE
		bal		lock_d_cache
		nop

		/* now initialize sp to stack start */
		la		sp, (SHMOO_STACK_START + SHMOO_STACK_SIZE - 48)
		# create a stack space for the the memc_init arguments.
		addiu	sp, -16
		# load parameters in a0-a3 for memc_init

		/*int memc_init(int32_t memc_num_to_shmoo, int32_t write_dqs_shmoo_range, uint32_t num_byte_slices, uint32_t gate_value)
*/
		li		a0, 0x0
		lui		a1, MEMC_0_DEFAULT_WRITE_DQS_PHASE_RANGE_UPPER
		ori		a1, MEMC_0_DEFAULT_WRITE_DQS_PHASE_RANGE_LOWER
		li		a2, 2 #16bit DDR
		li		a3, MEMC_0_DEFAULT_GATE_VALUE

		la		t0, memc_init
		jalr	t0
		nop
#if defined(BOOT_SCRAMBLE_DRAM)
#if (BCHP_VER>=BCHP_VER_B0)
		la		t0, do_dram_scramble
#else
		la		t0, scramble_dram
#endif
		jalr	t0
		nop
#endif
		bal _writeasm
		li a0, 'H'

/* index-writeback-invalidate-d */
		bal clear_all_d_cache
		nop

		bal _writeasm
		li a0, 'E'
		bal _writeasm
		li a0, 'L'

/* clear bss segment */
		la	a0,_fbss
		la	a1,_end
		subu	a1,a1,a0

		beqz a1, 2f
		nop
1:
		sw zero,0(a0)
		sub a1, a1, 4
		addi a0, a0, 4
		bnez a1, 1b
		nop
2:
		la sp, (bl_stack + BL_STACK_SIZE - 48)

		la a0, _stage2_start
		la a1, __start_s2
		la a2, _stage2_size
		bal aligned_copy
		nop
		bal _writeasm
		li a0, 'L'

/* index-writeback-invalidate-d */
		bal clear_all_d_cache
		nop
		jal stage1_main
		nop
		bal _writeasm
		li a0, 'O'

		la t0,__start_s2
		or t0, 0x20000000
		jalr t0
		nop
loop:
		b loop
		nop


LEAF(aligned_copy)

1:
		lw		v0, 0(a0)
		addiu	a2, a2, -4
		sw		v0, 0(a1)
		addiu	a0, a0, 4
		bnez	a2, 1b
		addiu	a1, a1, 4

		jr		ra
		nop

END(aligned_copy)

.if 0
/* test routine */
LEAF(word_compare)

1:
		lw		v0, 0(a0)
		addiu	a2, a2, -4
		lw		v1, 0(a1)
2:
		bne		v0,v1, 2b
		nop

		addiu	a0, a0, 4
		bnez	a2, 1b
		addiu	a1, a1, 4

		jr		ra
		nop

END(word_compare)
.endif

#include "uart.s"
#include "chip.s"
#undef RelAddrPrintChar
#undef RelAddrPrintHex32
#undef SHMOO_STACK_START
#undef SHMOO_STACK_SIZE
#include "common_routines.s"
#include "memc_0_client_prog.s"
#include "memc_0_access.s"
#include "run_shmoo.s"
#include "cache_lib.s"
#include "mips_libs.s"
#if defined(BOOT_SCRAMBLE_DRAM)
#undef REG
#if (BCHP_VER<BCHP_VER_B0)
#include "scramble_dram.s"
#endif
#endif