OUTPUT_ARCH(mips)
ENTRY(__start)
/* Flash is located at 0xb8c00000 when boot_rom_enable=1 */
flash_start = 0x98c00000;

MEMORY
{
	FLASH(R)	: ORIGIN = 0x98c00000, LENGTH = 0x0007C000
	RAM(RW)		: ORIGIN = (0x80000000+0x01000000), LENGTH = (0x2000000-((0x80000000+0x01000000)-0x80000000))
	S2_RAM(RW): ORIGIN = (0x80100000), LENGTH = (0x16000)
}

SECTIONS
{
	.stage1 :	AT ( flash_start )
	{
		bootloader12_s1l.o(.text)
		bootloader12_s1l.o(.text.*)
		bootloader12_s1l.o(.rodata)
		bootloader12_s1l.o(.rodata1)
		bootloader12_s1l.o(.rodata.str1.4)
		bootloader12_s1l.o(.rodata.cst4)
		bootloader12_s1l.o(.rodata.cst8)
		bootloader12_s1l.o(.fini)
		bootloader12_s1l.o(.reginfo)
		. = ALIGN(0x40);
	} > FLASH
	
	.text : AT ( LOADADDR(.stage1) + SIZEOF(.stage1) )
	{
		_ftext = .;
		*(.text)
		*(.text.*)
		*(.rodata)
		*(.rodata1)
		*(.rodata.str1.4)
		*(.rodata.cst4)
		*(.rodata.cst8)
		*(.fini)
		*(.reginfo)
	 	. = ALIGN(0x40);
	} > S2_RAM
	_etext = ( LOADADDR(.text) + SIZEOF(.text) );
	etext = ( LOADADDR(.text) + SIZEOF(.text) );
	
	.data : AT (_etext)
	{
		_fdata = .;
		*(data)
		SORT(CONSTRUCTORS)
	 	. = ALIGN(0x40);
	} > RAM

	
	_edata  =  .;
	_fbss = .;
	_stage2_start = LOADADDR(.text);
	_stage2_size = ( LOADADDR(.data) + SIZEOF(.data) - LOADADDR(.text));
	_bootloader_size = LOADADDR(.data) + SIZEOF(.data) - LOADADDR(.stage1);

	_ram_image_start = flash_start + 0x20000;
	_ram_image2_start = _ram_image_start + (29 * 0x10000);

	.sbss (NOLOAD) : 
	{
		*(.sbss)
		*(.scommon)
	}
	
	.bss (NOLOAD) :
	{
		_bss_start = .;
		*(.bss)
		*(COMMON)
		. = ALIGN(4);
	} > RAM
	
	. = ALIGN(4);
	_end = .;
	PROVIDE(_end = .);
	end = .;
	PROVIDE(end = .);
}