/************************************************************************* ** Broadcom Corp. Confidential ** Copyright 2010 Broadcom Corp. All Rights Reserved. ** ** THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE ** AGREEMENT BETWEEN THE USER AND BROADCOM. YOU HAVE NO RIGHT TO USE OR ** EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT. ** ** File: bls1.S ** Description: stage 1 of two stage bootloader for 755x chip. ** Created: alexp ** ** REVISION: ** ***************************************************************************/ #include "bmips3300.h" #include "bchp.h" #include "bchp_common.h" #include "bchp_sca.h" #include "bchp_scb.h" #include "bchp_sun_top_ctrl.h" #include "bchp_bsp_glb_control.h" #if defined(MEMSYSINIT) #include "bchp_memc_gen_0.h" #include "bchp_ddr40_phy_control_regs_0.h" #include "bchp_memc_ddr23_shim_addr_cntl_0.h" #else #include "memc_0_config.h" #endif #define BCHP_REG_BASE PHYS_TO_K1(BCHP_PHYSICAL_OFFSET) #define INITIAL_SR ((CP0_STATUS_SR_MASK | CP0_STATUS_CU0_MASK | CP0_STATUS_CU1_MASK | CP0_STATUS_BEV_MASK | CP0_STATUS_IE_MASK) & ~( CP0_STATUS_ERL_MASK | CP0_STATUS_EXL_MASK)) BL_STACK_SIZE = 0x1000 #if (BCHP_VER == BCHP_VER_A0) #define PARTB_OFFSET 0xc60 #endif #if (BCHP_VER == BCHP_VER_B0) #define PARTB_OFFSET 0xc80 #endif .lcomm bl_stack, BL_STACK_SIZE .text .globl __start .set noreorder .func __start __start: b nmi_check nop nop nop /* size of stage1+stage2 */ .word _bootloader_size .org __start+0x180 except1: b except1 nop .org __start+0x200 except2: b except2 nop .org __start+0x380 rom_gen_ex: # general exception will loop here b rom_gen_ex nop /* Starting at offset 0x400 various fields for BSP must be placed in the flash image.*/ .org __start+0x400 #if (BCHP_VER == BCHP_VER_A0) .word 0x000073a0 /* flash block size */ .word 0x80 /* flags */ .word 0x07000202 /* stage 2 boot code size */ .word 0x12345678 .org __start+0x420 /* bsec parameter signature */ .fill 0x100,1,0x22 /* stage 1 signature */ .fill 0x100,1,0x33 /* key 1 */ .fill 0x100,1,0x44 /* key 1 parameters */ .word 0x08000100 /* market id */ .word 0x00000000 /* filler data, can be anything */ .word 0xf111f111, 0xf111f111 /* key 1 signature calculated from 0x620 to 0x72f */ .fill 0x100,1,0x55 .fill 0x20, 1, 0x66 #endif #if (BCHP_VER == BCHP_VER_B0) /* stage 1 part b size, hardcoded to max size */ .word 0x00006F80 /* reserved, must be this value */ .word 0x00000080 /* flags */ .word 0x07000202 /* stage 2 boot code size */ .word 0x12345678 .org __start+0x440 /* bsec parameter signature */ .fill 0x100,1,0x22 /* stage 1 signature 0x540*/ .fill 0x100,1,0x33 /* include oem key file */ #include "dummy_key1.S" #endif /* bsp pointers */ .word __bsp_key0 .word __bsp_fw .org __start + PARTB_OFFSET .align 4 nmi_check: mfc0 k0, CP0_STATUS nop nop li k1, 0x00080000 and k0, k0, k1 beqz k0, start1 nop /* NMI handler */ mfc0 k0, CP0_STATUS nop nop li k1, ~0x00080000 and k0, k0, k1 mtc0 k0, CP0_STATUS nop nop li k0, 0x1 li k1, PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_SCA_SC_IF_CMD_1) sw k0, 0(k1) li k1, PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_SCB_SC_IF_CMD_1) sw k0, 0(k1) eret nop start1: li t0, INITIAL_SR mtc0 t0, CP0_STATUS nop nop /* Clear software interrupts */ mtc0 zero, CP0_CAUSE nop nop /* Allow NMI from BSP */ li t0, PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_BSP_GLB_CONTROL_MIPS_NMI_STATUS) lw t1, 0(t0) or t1, t1, BCHP_BSP_GLB_CONTROL_MIPS_NMI_STATUS_NMI_STATUS_MASK sw t1, 0(t0) bal init_serial nop bal _writeasm li a0, '$' bal do_chip_init nop bal _writeasm li a0, '>' bal read_pc lui t1,0x2000 read_pc: and t1, t1, ra beqz t1, running_from_cache nop /* we are running from uncached space. initialize mips and cache*/ bal init_mips nop la t1, running_from_cache jr t1 nop running_from_cache: #if defined(MEMSYSINIT) #define SHMOO_STACK_SIZE (32 * 1024) #define SHMOO_STACK_START (0x80000000) li a0, SHMOO_STACK_START li a1, SHMOO_STACK_SIZE bal validate_dcache_data nop la sp, (SHMOO_STACK_START + SHMOO_STACK_SIZE - 24) #if defined(AVS_ENABLE) la t0, AvsStart jalr t0 nop #endif li a0, 0xbfc00000+MCB0_OFFSET li a1, PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_MEMC_GEN_0_CORE_REV_ID) // MEMC_TOP register base addr li a2, PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION) // DDR40_PHY register base addr li a3, PHYS_TO_K1(BCHP_PHYSICAL_OFFSET+BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG) // DDR23_SHIM register base addr li t0, 0x0 sw t0, 16(sp) jal memsys_init nop // check v0 here beqz v0, shmoo_step nop 1: /* infinite loop */ b 1b nop shmoo_step: bal run_shmoo nop beqz v0, shmoo_done nop 1: /* infinite loop */ b 1b nop #else bal memc_0_ddr_init nop bal _writeasm li a0, '=' #if BCHP_VER == BCHP_VER_A0 /* DUMMY SCB0 write from MIPS */ li a0, 0xa0000000 sw zero, 0(a0) #endif bal run_shmoo nop #endif shmoo_done: #if defined(BOOT_SCRAMBLE_DRAM) bal scramble_sdram nop #endif /* mips boot rom must be hidden otherwise BSP will reboot MIPS upon transferring execution to the ram address */ bal hide_mips_boot_rom nop la a0, _stage2_start or a0, 0x20000000 la a1, __start_s2 la a2, _stage2_size addiu a2, a2, 0x100 bal aligned_copy nop /* flush invalidate d cache */ bal clear_all_d_cache nop #if 0 /* authenticate stage 2 */ la a0, __start_s2 and a0, 0xffff move a1, a0 addiu a0, a0, 2 la a3, _stage2_size add a1, a1, a3 move a2, a1 addiu a1, a1, -1 li a3, 0x01ff0000 bal aegis_arch_r2_setup nop #endif la t0,__start_s2 or t0, 0x20000000 jalr t0 nop loop: b loop nop .endfunc LEAF(aligned_copy) 1: lw v0, 0(a0) addiu a2, a2, -4 sw v0, 0(a1) addiu a0, a0, 4 bnez a2, 1b addiu a1, a1, 4 jr ra nop END(aligned_copy) #include "uart.s" #include "chip.s" #include "cache_lib.s" #if !defined(MEMSYSINIT) #include "memc_0_ddr_init.s" #endif #undef SHMOO_STACK_START #include "run_shmoo.s" #if defined(BOOT_SCRAMBLE_DRAM) #include "scramble.s" #endif #define delay_loop dl1 #include "hide_rom.s" #include "bsp_util.s" #include "mips_libs.s"